2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt2800pci module.
24 Supported chipsets: RT2800E & RT2800ED.
35 * E2PROM_CSR: EEPROM control register.
36 * RELOAD: Write 1 to reload eeprom content.
37 * TYPE: 0: 93c46, 1:93c66.
38 * LOAD_STATUS: 1:loading, 0:done.
40 #define E2PROM_CSR 0x0004
41 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
42 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
43 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
44 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
45 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
46 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
47 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
50 * Queue register offset macros
52 #define TX_QUEUE_REG_OFFSET 0x10
53 #define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
54 #define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
55 #define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
56 #define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
59 * EFUSE_CSR: RT3090 EEPROM
61 #define EFUSE_CTRL 0x0580
62 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
63 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
64 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
65 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
70 #define EFUSE_DATA0 0x0590
75 #define EFUSE_DATA1 0x0594
80 #define EFUSE_DATA2 0x0598
85 #define EFUSE_DATA3 0x059c
88 * 8051 firmware image.
90 #define FIRMWARE_RT2860 "rt2860.bin"
91 #define FIRMWARE_IMAGE_BASE 0x2000
94 * DMA descriptor defines.
96 #define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
97 #define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
100 * TX descriptor format for TX, PRIO and Beacon Ring.
106 #define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
111 #define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
112 #define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
113 #define TXD_W1_BURST FIELD32(0x00008000)
114 #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
115 #define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
116 #define TXD_W1_DMA_DONE FIELD32(0x80000000)
121 #define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
125 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
126 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
127 * 0:MGMT, 1:HCCA 2:EDCA
129 #define TXD_W3_WIV FIELD32(0x01000000)
130 #define TXD_W3_QSEL FIELD32(0x06000000)
131 #define TXD_W3_TCO FIELD32(0x20000000)
132 #define TXD_W3_UCO FIELD32(0x40000000)
133 #define TXD_W3_ICO FIELD32(0x80000000)
136 * RX descriptor format for RX Ring.
142 #define RXD_W0_SDP0 FIELD32(0xffffffff)
147 #define RXD_W1_SDL1 FIELD32(0x00003fff)
148 #define RXD_W1_SDL0 FIELD32(0x3fff0000)
149 #define RXD_W1_LS0 FIELD32(0x40000000)
150 #define RXD_W1_DMA_DONE FIELD32(0x80000000)
155 #define RXD_W2_SDP1 FIELD32(0xffffffff)
159 * AMSDU: RX with 802.3 header, not 802.11 header.
160 * DECRYPTED: This frame is being decrypted.
162 #define RXD_W3_BA FIELD32(0x00000001)
163 #define RXD_W3_DATA FIELD32(0x00000002)
164 #define RXD_W3_NULLDATA FIELD32(0x00000004)
165 #define RXD_W3_FRAG FIELD32(0x00000008)
166 #define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
167 #define RXD_W3_MULTICAST FIELD32(0x00000020)
168 #define RXD_W3_BROADCAST FIELD32(0x00000040)
169 #define RXD_W3_MY_BSS FIELD32(0x00000080)
170 #define RXD_W3_CRC_ERROR FIELD32(0x00000100)
171 #define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
172 #define RXD_W3_AMSDU FIELD32(0x00000800)
173 #define RXD_W3_HTC FIELD32(0x00001000)
174 #define RXD_W3_RSSI FIELD32(0x00002000)
175 #define RXD_W3_L2PAD FIELD32(0x00004000)
176 #define RXD_W3_AMPDU FIELD32(0x00008000)
177 #define RXD_W3_DECRYPTED FIELD32(0x00010000)
178 #define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
179 #define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
181 #endif /* RT2800PCI_H */