drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 1;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                                H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  71                                 const unsigned int word, const u8 value)
  72 {
  73         u32 reg;
  74
  75         mutex_lock(&rt2x00dev->csr_mutex);
  76
  77         /*
  78          * Wait until the BBP becomes available, afterwards we
  79          * can safely write the new data into the register.
  80          */
  81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  82                 reg = 0;
  83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  87
  88                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  89         }
  90
  91         mutex_unlock(&rt2x00dev->csr_mutex);
  92 }
  93
  94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  95                                const unsigned int word, u8 *value)
  96 {
  97         u32 reg;
  98
  99         mutex_lock(&rt2x00dev->csr_mutex);
 100
 101         /*
 102          * Wait until the BBP becomes available, afterwards we
 103          * can safely write the read request into the register.
 104          * After the data has been written, we wait until hardware
 105          * returns the correct value, if at any time the register
 106          * doesn't become available in time, reg will be 0xffffffff
 107          * which means we return 0xff to the caller.
 108          */
 109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110                 reg = 0;
 111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 114
 115                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 116
 117                 WAIT_FOR_BBP(rt2x00dev, &reg);
 118         }
 119
 120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 121
 122         mutex_unlock(&rt2x00dev->csr_mutex);
 123 }
 124
 125 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 126                                   const unsigned int word, const u8 value)
 127 {
 128         u32 reg;
 129
 130         mutex_lock(&rt2x00dev->csr_mutex);
 131
 132         /*
 133          * Wait until the RFCSR becomes available, afterwards we
 134          * can safely write the new data into the register.
 135          */
 136         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 137                 reg = 0;
 138                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 139                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 140                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 141                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 142
 143                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 144         }
 145
 146         mutex_unlock(&rt2x00dev->csr_mutex);
 147 }
 148
 149 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 150                                  const unsigned int word, u8 *value)
 151 {
 152         u32 reg;
 153
 154         mutex_lock(&rt2x00dev->csr_mutex);
 155
 156         /*
 157          * Wait until the RFCSR becomes available, afterwards we
 158          * can safely write the read request into the register.
 159          * After the data has been written, we wait until hardware
 160          * returns the correct value, if at any time the register
 161          * doesn't become available in time, reg will be 0xffffffff
 162          * which means we return 0xff to the caller.
 163          */
 164         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 165                 reg = 0;
 166                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 167                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 168                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 169
 170                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 171
 172                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 173         }
 174
 175         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 176
 177         mutex_unlock(&rt2x00dev->csr_mutex);
 178 }
 179
 180 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 181                                const unsigned int word, const u32 value)
 182 {
 183         u32 reg;
 184
 185         mutex_lock(&rt2x00dev->csr_mutex);
 186
 187         /*
 188          * Wait until the RF becomes available, afterwards we
 189          * can safely write the new data into the register.
 190          */
 191         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 192                 reg = 0;
 193                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 194                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 195                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 196                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 197
 198                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 199                 rt2x00_rf_write(rt2x00dev, word, value);
 200         }
 201
 202         mutex_unlock(&rt2x00dev->csr_mutex);
 203 }
 204
 205 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 206                                   const u8 command, const u8 token,
 207                                   const u8 arg0, const u8 arg1)
 208 {
 209         u32 reg;
 210
 211         mutex_lock(&rt2x00dev->csr_mutex);
 212
 213         /*
 214          * Wait until the MCU becomes available, afterwards we
 215          * can safely write the new data into the register.
 216          */
 217         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 218                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 219                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 220                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 221                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 222                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 223
 224                 reg = 0;
 225                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 226                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 227         }
 228
 229         mutex_unlock(&rt2x00dev->csr_mutex);
 230 }
 231
 232 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 233 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 234         .owner  = THIS_MODULE,
 235         .csr    = {
 236                 .read           = rt2800_register_read,
 237                 .write          = rt2800_register_write,
 238                 .flags          = RT2X00DEBUGFS_OFFSET,
 239                 .word_base      = CSR_REG_BASE,
 240                 .word_size      = sizeof(u32),
 241                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 242         },
 243         .eeprom = {
 244                 .read           = rt2x00_eeprom_read,
 245                 .write          = rt2x00_eeprom_write,
 246                 .word_base      = EEPROM_BASE,
 247                 .word_size      = sizeof(u16),
 248                 .word_count     = EEPROM_SIZE / sizeof(u16),
 249         },
 250         .bbp    = {
 251                 .read           = rt2800usb_bbp_read,
 252                 .write          = rt2800usb_bbp_write,
 253                 .word_base      = BBP_BASE,
 254                 .word_size      = sizeof(u8),
 255                 .word_count     = BBP_SIZE / sizeof(u8),
 256         },
 257         .rf     = {
 258                 .read           = rt2x00_rf_read,
 259                 .write          = rt2800usb_rf_write,
 260                 .word_base      = RF_BASE,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 268 {
 269         u32 reg;
 270
 271         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 272         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 273 }
 274
 275 #ifdef CONFIG_RT2X00_LIB_LEDS
 276 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 277                                      enum led_brightness brightness)
 278 {
 279         struct rt2x00_led *led =
 280             container_of(led_cdev, struct rt2x00_led, led_dev);
 281         unsigned int enabled = brightness != LED_OFF;
 282         unsigned int bg_mode =
 283             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 284         unsigned int polarity =
 285                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 286                                    EEPROM_FREQ_LED_POLARITY);
 287         unsigned int ledmode =
 288                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 289                                    EEPROM_FREQ_LED_MODE);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 293                                       enabled ? 0x20 : 0);
 294         } else if (led->type == LED_TYPE_ASSOC) {
 295                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 296                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 297         } else if (led->type == LED_TYPE_QUALITY) {
 298                 /*
 299                  * The brightness is divided into 6 levels (0 - 5),
 300                  * The specs tell us the following levels:
 301                  *      0, 1 ,3, 7, 15, 31
 302                  * to determine the level in a simple way we can simply
 303                  * work with bitshifting:
 304                  *      (1 << level) - 1
 305                  */
 306                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 307                                       (1 << brightness / (LED_FULL / 6)) - 1,
 308                                       polarity);
 309         }
 310 }
 311
 312 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 313                                unsigned long *delay_on,
 314                                unsigned long *delay_off)
 315 {
 316         struct rt2x00_led *led =
 317             container_of(led_cdev, struct rt2x00_led, led_dev);
 318         u32 reg;
 319
 320         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 321         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 322         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 323         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 324         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 325         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 326         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 327         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 328         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 329
 330         return 0;
 331 }
 332
 333 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 334                                struct rt2x00_led *led,
 335                                enum led_type type)
 336 {
 337         led->rt2x00dev = rt2x00dev;
 338         led->type = type;
 339         led->led_dev.brightness_set = rt2800usb_brightness_set;
 340         led->led_dev.blink_set = rt2800usb_blink_set;
 341         led->flags = LED_INITIALIZED;
 342 }
 343 #endif /* CONFIG_RT2X00_LIB_LEDS */
 344
 345 /*
 346  * Configuration handlers.
 347  */
 348 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 349                                        struct rt2x00lib_crypto *crypto,
 350                                        struct ieee80211_key_conf *key)
 351 {
 352         struct mac_wcid_entry wcid_entry;
 353         struct mac_iveiv_entry iveiv_entry;
 354         u32 offset;
 355         u32 reg;
 356
 357         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 358
 359         rt2800_register_read(rt2x00dev, offset, &reg);
 360         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 361                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 362         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 363                            (crypto->cmd == SET_KEY) * crypto->cipher);
 364         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 365                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 366         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 367         rt2800_register_write(rt2x00dev, offset, reg);
 368
 369         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 370
 371         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 372         if ((crypto->cipher == CIPHER_TKIP) ||
 373             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 374             (crypto->cipher == CIPHER_AES))
 375                 iveiv_entry.iv[3] |= 0x20;
 376         iveiv_entry.iv[3] |= key->keyidx << 6;
 377         rt2800_register_multiwrite(rt2x00dev, offset,
 378                                       &iveiv_entry, sizeof(iveiv_entry));
 379
 380         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 381
 382         memset(&wcid_entry, 0, sizeof(wcid_entry));
 383         if (crypto->cmd == SET_KEY)
 384                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 385         rt2800_register_multiwrite(rt2x00dev, offset,
 386                                       &wcid_entry, sizeof(wcid_entry));
 387 }
 388
 389 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 390                                        struct rt2x00lib_crypto *crypto,
 391                                        struct ieee80211_key_conf *key)
 392 {
 393         struct hw_key_entry key_entry;
 394         struct rt2x00_field32 field;
 395         u32 offset;
 396         u32 reg;
 397
 398         if (crypto->cmd == SET_KEY) {
 399                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 400
 401                 memcpy(key_entry.key, crypto->key,
 402                        sizeof(key_entry.key));
 403                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 404                        sizeof(key_entry.tx_mic));
 405                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 406                        sizeof(key_entry.rx_mic));
 407
 408                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 409                 rt2800_register_multiwrite(rt2x00dev, offset,
 410                                               &key_entry, sizeof(key_entry));
 411         }
 412
 413         /*
 414          * The cipher types are stored over multiple registers
 415          * starting with SHARED_KEY_MODE_BASE each word will have
 416          * 32 bits and contains the cipher types for 2 bssidx each.
 417          * Using the correct defines correctly will cause overhead,
 418          * so just calculate the correct offset.
 419          */
 420         field.bit_offset = 4 * (key->hw_key_idx % 8);
 421         field.bit_mask = 0x7 << field.bit_offset;
 422
 423         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 424
 425         rt2800_register_read(rt2x00dev, offset, &reg);
 426         rt2x00_set_field32(&reg, field,
 427                            (crypto->cmd == SET_KEY) * crypto->cipher);
 428         rt2800_register_write(rt2x00dev, offset, reg);
 429
 430         /*
 431          * Update WCID information
 432          */
 433         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 434
 435         return 0;
 436 }
 437
 438 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 439                                          struct rt2x00lib_crypto *crypto,
 440                                          struct ieee80211_key_conf *key)
 441 {
 442         struct hw_key_entry key_entry;
 443         u32 offset;
 444
 445         if (crypto->cmd == SET_KEY) {
 446                 /*
 447                  * 1 pairwise key is possible per AID, this means that the AID
 448                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 449                  * last possible shared key entry.
 450                  */
 451                 if (crypto->aid > (256 - 32))
 452                         return -ENOSPC;
 453
 454                 key->hw_key_idx = 32 + crypto->aid;
 455
 456                 memcpy(key_entry.key, crypto->key,
 457                        sizeof(key_entry.key));
 458                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 459                        sizeof(key_entry.tx_mic));
 460                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 461                        sizeof(key_entry.rx_mic));
 462
 463                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 464                 rt2800_register_multiwrite(rt2x00dev, offset,
 465                                               &key_entry, sizeof(key_entry));
 466         }
 467
 468         /*
 469          * Update WCID information
 470          */
 471         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 472
 473         return 0;
 474 }
 475
 476 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 477                                     const unsigned int filter_flags)
 478 {
 479         u32 reg;
 480
 481         /*
 482          * Start configuration steps.
 483          * Note that the version error will always be dropped
 484          * and broadcast frames will always be accepted since
 485          * there is no filter for it at this time.
 486          */
 487         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 488         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 489                            !(filter_flags & FIF_FCSFAIL));
 490         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 491                            !(filter_flags & FIF_PLCPFAIL));
 492         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 493                            !(filter_flags & FIF_PROMISC_IN_BSS));
 494         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 495         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 496         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 497                            !(filter_flags & FIF_ALLMULTI));
 498         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 499         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 501                            !(filter_flags & FIF_CONTROL));
 502         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 503                            !(filter_flags & FIF_CONTROL));
 504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 505                            !(filter_flags & FIF_CONTROL));
 506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 507                            !(filter_flags & FIF_CONTROL));
 508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 509                            !(filter_flags & FIF_CONTROL));
 510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 511                            !(filter_flags & FIF_PSPOLL));
 512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 513         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 515                            !(filter_flags & FIF_CONTROL));
 516         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 517 }
 518
 519 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 520                                   struct rt2x00_intf *intf,
 521                                   struct rt2x00intf_conf *conf,
 522                                   const unsigned int flags)
 523 {
 524         unsigned int beacon_base;
 525         u32 reg;
 526
 527         if (flags & CONFIG_UPDATE_TYPE) {
 528                 /*
 529                  * Clear current synchronisation setup.
 530                  * For the Beacon base registers we only need to clear
 531                  * the first byte since that byte contains the VALID and OWNER
 532                  * bits which (when set to 0) will invalidate the entire beacon.
 533                  */
 534                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 535                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 536
 537                 /*
 538                  * Enable synchronisation.
 539                  */
 540                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 541                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 542                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 543                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 544                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 545         }
 546
 547         if (flags & CONFIG_UPDATE_MAC) {
 548                 reg = le32_to_cpu(conf->mac[1]);
 549                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 550                 conf->mac[1] = cpu_to_le32(reg);
 551
 552                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 553                                               conf->mac, sizeof(conf->mac));
 554         }
 555
 556         if (flags & CONFIG_UPDATE_BSSID) {
 557                 reg = le32_to_cpu(conf->bssid[1]);
 558                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 559                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 560                 conf->bssid[1] = cpu_to_le32(reg);
 561
 562                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 563                                               conf->bssid, sizeof(conf->bssid));
 564         }
 565 }
 566
 567 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 568                                  struct rt2x00lib_erp *erp)
 569 {
 570         u32 reg;
 571
 572         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 573         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 574         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 575
 576         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 577         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 578                            !!erp->short_preamble);
 579         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 580                            !!erp->short_preamble);
 581         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 582
 583         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 584         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 585                            erp->cts_protection ? 2 : 0);
 586         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 587
 588         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 589                                  erp->basic_rates);
 590         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 591
 592         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 593         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 594         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 595         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 596
 597         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 598         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 599         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 600         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 601         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 602         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 603         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 604
 605         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 606         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 607                            erp->beacon_int * 16);
 608         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 609 }
 610
 611 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 612                                  struct antenna_setup *ant)
 613 {
 614         u8 r1;
 615         u8 r3;
 616
 617         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 618         rt2800usb_bbp_read(rt2x00dev, 3, &r3);
 619
 620         /*
 621          * Configure the TX antenna.
 622          */
 623         switch ((int)ant->tx) {
 624         case 1:
 625                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 626                 break;
 627         case 2:
 628                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 629                 break;
 630         case 3:
 631                 /* Do nothing */
 632                 break;
 633         }
 634
 635         /*
 636          * Configure the RX antenna.
 637          */
 638         switch ((int)ant->rx) {
 639         case 1:
 640                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 641                 break;
 642         case 2:
 643                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 644                 break;
 645         case 3:
 646                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 647                 break;
 648         }
 649
 650         rt2800usb_bbp_write(rt2x00dev, 3, r3);
 651         rt2800usb_bbp_write(rt2x00dev, 1, r1);
 652 }
 653
 654 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 655                                       struct rt2x00lib_conf *libconf)
 656 {
 657         u16 eeprom;
 658         short lna_gain;
 659
 660         if (libconf->rf.channel <= 14) {
 661                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 662                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 663         } else if (libconf->rf.channel <= 64) {
 664                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 665                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 666         } else if (libconf->rf.channel <= 128) {
 667                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 668                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 669         } else {
 670                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 671                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 672         }
 673
 674         rt2x00dev->lna_gain = lna_gain;
 675 }
 676
 677 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 678                                           struct ieee80211_conf *conf,
 679                                           struct rf_channel *rf,
 680                                           struct channel_info *info)
 681 {
 682         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 683
 684         if (rt2x00dev->default_ant.tx == 1)
 685                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 686
 687         if (rt2x00dev->default_ant.rx == 1) {
 688                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 689                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 690         } else if (rt2x00dev->default_ant.rx == 2)
 691                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 692
 693         if (rf->channel > 14) {
 694                 /*
 695                  * When TX power is below 0, we should increase it by 7 to
 696                  * make it a positive value (Minumum value is -7).
 697                  * However this means that values between 0 and 7 have
 698                  * double meaning, and we should set a 7DBm boost flag.
 699                  */
 700                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 701                                    (info->tx_power1 >= 0));
 702
 703                 if (info->tx_power1 < 0)
 704                         info->tx_power1 += 7;
 705
 706                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 707                                    TXPOWER_A_TO_DEV(info->tx_power1));
 708
 709                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 710                                    (info->tx_power2 >= 0));
 711
 712                 if (info->tx_power2 < 0)
 713                         info->tx_power2 += 7;
 714
 715                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 716                                    TXPOWER_A_TO_DEV(info->tx_power2));
 717         } else {
 718                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 719                                    TXPOWER_G_TO_DEV(info->tx_power1));
 720                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 721                                    TXPOWER_G_TO_DEV(info->tx_power2));
 722         }
 723
 724         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 725
 726         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 727         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 728         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 729         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 730
 731         udelay(200);
 732
 733         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 734         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 735         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 736         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 737
 738         udelay(200);
 739
 740         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 741         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 742         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 743         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 744 }
 745
 746 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 747                                           struct ieee80211_conf *conf,
 748                                           struct rf_channel *rf,
 749                                           struct channel_info *info)
 750 {
 751         u8 rfcsr;
 752
 753         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 754         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 755
 756         rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 757         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 758         rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 759
 760         rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 761         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 762                           TXPOWER_G_TO_DEV(info->tx_power1));
 763         rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 764
 765         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 766         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 767         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 768
 769         rt2800usb_rfcsr_write(rt2x00dev, 24,
 770                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 771
 772         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 773         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 774         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 775 }
 776
 777 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 778                                      struct ieee80211_conf *conf,
 779                                      struct rf_channel *rf,
 780                                      struct channel_info *info)
 781 {
 782         u32 reg;
 783         unsigned int tx_pin;
 784         u8 bbp;
 785
 786         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 787                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 788         else
 789                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 790
 791         /*
 792          * Change BBP settings
 793          */
 794         rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 795         rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 796         rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 797         rt2800usb_bbp_write(rt2x00dev, 86, 0);
 798
 799         if (rf->channel <= 14) {
 800                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 801                         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
 802                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 803                 } else {
 804                         rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
 805                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 806                 }
 807         } else {
 808                 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
 809
 810                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 811                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 812                 else
 813                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 814         }
 815
 816         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 817         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 818         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 819         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 820         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 821
 822         tx_pin = 0;
 823
 824         /* Turn on unused PA or LNA when not using 1T or 1R */
 825         if (rt2x00dev->default_ant.tx != 1) {
 826                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 827                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 828         }
 829
 830         /* Turn on unused PA or LNA when not using 1T or 1R */
 831         if (rt2x00dev->default_ant.rx != 1) {
 832                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 833                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 834         }
 835
 836         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 837         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 838         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 839         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 840         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 841         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 842
 843         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 844
 845         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
 846         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 847         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
 848
 849         rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
 850         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 851         rt2800usb_bbp_write(rt2x00dev, 3, bbp);
 852
 853         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 854                 if (conf_is_ht40(conf)) {
 855                         rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
 856                         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
 857                         rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
 858                 } else {
 859                         rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
 860                         rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
 861                         rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
 862                 }
 863         }
 864
 865         msleep(1);
 866 }
 867
 868 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 869                                      const int txpower)
 870 {
 871         u32 reg;
 872         u32 value = TXPOWER_G_TO_DEV(txpower);
 873         u8 r1;
 874
 875         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 876         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 877         rt2800usb_bbp_write(rt2x00dev, 1, r1);
 878
 879         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 880         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 881         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 882         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 883         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 884         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 885         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 886         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 887         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 888         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 889
 890         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 891         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 892         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 893         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 894         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 895         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 896         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 897         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 898         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 899         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 900
 901         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 902         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 903         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 904         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 905         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 906         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 909         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 910         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 911
 912         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 913         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 921         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 922
 923         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 924         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 928         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 929 }
 930
 931 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 932                                          struct rt2x00lib_conf *libconf)
 933 {
 934         u32 reg;
 935
 936         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 937         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 938                            libconf->conf->short_frame_max_tx_count);
 939         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 940                            libconf->conf->long_frame_max_tx_count);
 941         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 942         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 943         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 944         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 945         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 946 }
 947
 948 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 949                                 struct rt2x00lib_conf *libconf)
 950 {
 951         enum dev_state state =
 952             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 953                 STATE_SLEEP : STATE_AWAKE;
 954         u32 reg;
 955
 956         if (state == STATE_SLEEP) {
 957                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 958
 959                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 960                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 961                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 962                                    libconf->conf->listen_interval - 1);
 963                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 964                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 965
 966                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 967         } else {
 968                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 969
 970                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 971                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 972                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 973                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 974                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 975         }
 976 }
 977
 978 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
 979                              struct rt2x00lib_conf *libconf,
 980                              const unsigned int flags)
 981 {
 982         /* Always recalculate LNA gain before changing configuration */
 983         rt2800usb_config_lna_gain(rt2x00dev, libconf);
 984
 985         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 986                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
 987                                          &libconf->rf, &libconf->channel);
 988         if (flags & IEEE80211_CONF_CHANGE_POWER)
 989                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 990         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 991                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
 992         if (flags & IEEE80211_CONF_CHANGE_PS)
 993                 rt2800usb_config_ps(rt2x00dev, libconf);
 994 }
 995
 996 /*
 997  * Link tuning
 998  */
 999 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1000                                  struct link_qual *qual)
1001 {
1002         u32 reg;
1003
1004         /*
1005          * Update FCS error count from register.
1006          */
1007         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1008         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1009 }
1010
1011 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1012 {
1013         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1014                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1015                         return 0x1c + (2 * rt2x00dev->lna_gain);
1016                 else
1017                         return 0x2e + rt2x00dev->lna_gain;
1018         }
1019
1020         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1021                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1022         else
1023                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1024 }
1025
1026 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1027                                      struct link_qual *qual, u8 vgc_level)
1028 {
1029         if (qual->vgc_level != vgc_level) {
1030                 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1031                 qual->vgc_level = vgc_level;
1032                 qual->vgc_level_reg = vgc_level;
1033         }
1034 }
1035
1036 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1037                                   struct link_qual *qual)
1038 {
1039         rt2800usb_set_vgc(rt2x00dev, qual,
1040                           rt2800usb_get_default_vgc(rt2x00dev));
1041 }
1042
1043 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1044                                  struct link_qual *qual, const u32 count)
1045 {
1046         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1047                 return;
1048
1049         /*
1050          * When RSSI is better then -80 increase VGC level with 0x10
1051          */
1052         rt2800usb_set_vgc(rt2x00dev, qual,
1053                           rt2800usb_get_default_vgc(rt2x00dev) +
1054                           ((qual->rssi > -80) * 0x10));
1055 }
1056
1057 /*
1058  * Firmware functions
1059  */
1060 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1061 {
1062         return FIRMWARE_RT2870;
1063 }
1064
1065 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1066 {
1067         u16 fw_crc;
1068         u16 crc;
1069
1070         /*
1071          * The last 2 bytes in the firmware array are the crc checksum itself,
1072          * this means that we should never pass those 2 bytes to the crc
1073          * algorithm.
1074          */
1075         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1076
1077         /*
1078          * Use the crc ccitt algorithm.
1079          * This will return the same value as the legacy driver which
1080          * used bit ordering reversion on the both the firmware bytes
1081          * before input input as well as on the final output.
1082          * Obviously using crc ccitt directly is much more efficient.
1083          */
1084         crc = crc_ccitt(~0, data, len - 2);
1085
1086         /*
1087          * There is a small difference between the crc-itu-t + bitrev and
1088          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1089          * will be swapped, use swab16 to convert the crc to the correct
1090          * value.
1091          */
1092         crc = swab16(crc);
1093
1094         return fw_crc == crc;
1095 }
1096
1097 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1098                                     const u8 *data, const size_t len)
1099 {
1100         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1101         size_t offset = 0;
1102
1103         /*
1104          * Firmware files:
1105          * There are 2 variations of the rt2870 firmware.
1106          * a) size: 4kb
1107          * b) size: 8kb
1108          * Note that (b) contains 2 seperate firmware blobs of 4k
1109          * within the file. The first blob is the same firmware as (a),
1110          * but the second blob is for the additional chipsets.
1111          */
1112         if (len != 4096 && len != 8192)
1113                 return FW_BAD_LENGTH;
1114
1115         /*
1116          * Check if we need the upper 4kb firmware data or not.
1117          */
1118         if ((len == 4096) &&
1119             (chipset != 0x2860) &&
1120             (chipset != 0x2872) &&
1121             (chipset != 0x3070))
1122                 return FW_BAD_VERSION;
1123
1124         /*
1125          * 8kb firmware files must be checked as if it were
1126          * 2 seperate firmware files.
1127          */
1128         while (offset < len) {
1129                 if (!rt2800usb_check_crc(data + offset, 4096))
1130                         return FW_BAD_CRC;
1131
1132                 offset += 4096;
1133         }
1134
1135         return FW_OK;
1136 }
1137
1138 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1139                                    const u8 *data, const size_t len)
1140 {
1141         unsigned int i;
1142         int status;
1143         u32 reg;
1144         u32 offset;
1145         u32 length;
1146         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1147
1148         /*
1149          * Check which section of the firmware we need.
1150          */
1151         if ((chipset == 0x2860) ||
1152             (chipset == 0x2872) ||
1153             (chipset == 0x3070)) {
1154                 offset = 0;
1155                 length = 4096;
1156         } else {
1157                 offset = 4096;
1158                 length = 4096;
1159         }
1160
1161         /*
1162          * Wait for stable hardware.
1163          */
1164         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1165                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1166                 if (reg && reg != ~0)
1167                         break;
1168                 msleep(1);
1169         }
1170
1171         if (i == REGISTER_BUSY_COUNT) {
1172                 ERROR(rt2x00dev, "Unstable hardware.\n");
1173                 return -EBUSY;
1174         }
1175
1176         /*
1177          * Write firmware to device.
1178          */
1179         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1180                                             USB_VENDOR_REQUEST_OUT,
1181                                             FIRMWARE_IMAGE_BASE,
1182                                             data + offset, length,
1183                                             REGISTER_TIMEOUT32(length));
1184
1185         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1186         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1187
1188         /*
1189          * Send firmware request to device to load firmware,
1190          * we need to specify a long timeout time.
1191          */
1192         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1193                                              0, USB_MODE_FIRMWARE,
1194                                              REGISTER_TIMEOUT_FIRMWARE);
1195         if (status < 0) {
1196                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1197                 return status;
1198         }
1199
1200         msleep(10);
1201         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1202
1203         /*
1204          * Send signal to firmware during boot time.
1205          */
1206         rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1207
1208         if ((chipset == 0x3070) ||
1209             (chipset == 0x3071) ||
1210             (chipset == 0x3572)) {
1211                 udelay(200);
1212                 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1213                 udelay(10);
1214         }
1215
1216         /*
1217          * Wait for device to stabilize.
1218          */
1219         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1220                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1221                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1222                         break;
1223                 msleep(1);
1224         }
1225
1226         if (i == REGISTER_BUSY_COUNT) {
1227                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1228                 return -EBUSY;
1229         }
1230
1231         /*
1232          * Initialize firmware.
1233          */
1234         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1235         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1236         msleep(1);
1237
1238         return 0;
1239 }
1240
1241 /*
1242  * Initialization functions.
1243  */
1244 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1245 {
1246         u32 reg;
1247         unsigned int i;
1248
1249         /*
1250          * Wait untill BBP and RF are ready.
1251          */
1252         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1253                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1254                 if (reg && reg != ~0)
1255                         break;
1256                 msleep(1);
1257         }
1258
1259         if (i == REGISTER_BUSY_COUNT) {
1260                 ERROR(rt2x00dev, "Unstable hardware.\n");
1261                 return -EBUSY;
1262         }
1263
1264         rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1265         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1266
1267         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1268         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1269         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1270         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1271
1272         rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1273
1274         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1275                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1276
1277         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1278
1279         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1280         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1281         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1282         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1283         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1284         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1285
1286         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1287         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1288         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1289         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1290         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1291         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1292
1293         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1294         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1295
1296         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1297
1298         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1299         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1300         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1301         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1302         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1303         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1304         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1305         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1306
1307         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1308                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1309                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1310                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1311         } else {
1312                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1313                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1314         }
1315
1316         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1317         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1318         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1319         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1320         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1321         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1322         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1323         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1324         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1325         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1326
1327         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1328         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1329         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1330         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1331
1332         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1333         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1334         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1335             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1336                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1337         else
1338                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1339         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1340         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1341         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1342
1343         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1344
1345         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1346         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1347         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1348         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1349         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1350         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1351         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1352
1353         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1354         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1355         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1356         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1357         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1358         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1359         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1360         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1361         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1362         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1363         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1364
1365         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1366         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1367         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1368         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1369         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1370         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1371         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1372         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1373         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1374         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1375         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1376
1377         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1378         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1379         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1380         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1381         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1382         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1383         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1384         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1385         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1386         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1387         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1388
1389         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1390         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1391         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1392         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1393         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1394         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1395         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1396         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1397         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1398         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1399         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1400
1401         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1402         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1403         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1404         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1405         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1406         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1407         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1408         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1409         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1410         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1411         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1412
1413         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1414         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1415         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1416         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1417         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1418         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1419         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1420         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1421         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1422         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1423         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1424
1425         rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1426
1427         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1428         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1429         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1430         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1431         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1432         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1433         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1434         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1435         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1436         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1437         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1438
1439         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1440         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1441
1442         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1443         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1444         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1445                            IEEE80211_MAX_RTS_THRESHOLD);
1446         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1447         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1448
1449         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1450         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1451
1452         /*
1453          * ASIC will keep garbage value after boot, clear encryption keys.
1454          */
1455         for (i = 0; i < 4; i++)
1456                 rt2800_register_write(rt2x00dev,
1457                                          SHARED_KEY_MODE_ENTRY(i), 0);
1458
1459         for (i = 0; i < 256; i++) {
1460                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1461                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1462                                               wcid, sizeof(wcid));
1463
1464                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1465                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1466         }
1467
1468         /*
1469          * Clear all beacons
1470          * For the Beacon base registers we only need to clear
1471          * the first byte since that byte contains the VALID and OWNER
1472          * bits which (when set to 0) will invalidate the entire beacon.
1473          */
1474         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1475         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1476         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1477         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1478         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1479         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1480         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1481         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1482
1483         rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1484         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1485         rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1486
1487         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1488         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1489         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1490         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1491         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1492         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1493         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1494         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1495         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1496         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1497
1498         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1499         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1500         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1501         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1502         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1503         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1504         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1505         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1506         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1507         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1508
1509         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1510         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1511         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1512         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1513         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1514         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1515         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1516         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1517         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1518         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1519
1520         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1521         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1522         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1523         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1524         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1525         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1526
1527         /*
1528          * We must clear the error counters.
1529          * These registers are cleared on read,
1530          * so we may pass a useless variable to store the value.
1531          */
1532         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1533         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1534         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1535         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1536         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1537         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1538
1539         return 0;
1540 }
1541
1542 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1543 {
1544         unsigned int i;
1545         u32 reg;
1546
1547         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1548                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1549                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1550                         return 0;
1551
1552                 udelay(REGISTER_BUSY_DELAY);
1553         }
1554
1555         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1556         return -EACCES;
1557 }
1558
1559 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1560 {
1561         unsigned int i;
1562         u8 value;
1563
1564         /*
1565          * BBP was enabled after firmware was loaded,
1566          * but we need to reactivate it now.
1567          */
1568         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1569         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1570         msleep(1);
1571
1572         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1573                 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1574                 if ((value != 0xff) && (value != 0x00))
1575                         return 0;
1576                 udelay(REGISTER_BUSY_DELAY);
1577         }
1578
1579         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1580         return -EACCES;
1581 }
1582
1583 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1584 {
1585         unsigned int i;
1586         u16 eeprom;
1587         u8 reg_id;
1588         u8 value;
1589
1590         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1591                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1592                 return -EACCES;
1593
1594         rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1595         rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1596         rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1597         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1598         rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1599         rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1600         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1601         rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1602         rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1603         rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1604         rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1605         rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1606         rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1607         rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1608
1609         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1610                 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1611                 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1612         }
1613
1614         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1615                 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1616         }
1617
1618         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1619                 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1620                 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1621                 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1622         }
1623
1624         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1625                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1626
1627                 if (eeprom != 0xffff && eeprom != 0x0000) {
1628                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1629                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1630                         rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1631                 }
1632         }
1633
1634         return 0;
1635 }
1636
1637 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1638                                    bool bw40, u8 rfcsr24, u8 filter_target)
1639 {
1640         unsigned int i;
1641         u8 bbp;
1642         u8 rfcsr;
1643         u8 passband;
1644         u8 stopband;
1645         u8 overtuned = 0;
1646
1647         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1648
1649         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1650         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1651         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1652
1653         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1654         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1655         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1656
1657         /*
1658          * Set power & frequency of passband test tone
1659          */
1660         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1661
1662         for (i = 0; i < 100; i++) {
1663                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1664                 msleep(1);
1665
1666                 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1667                 if (passband)
1668                         break;
1669         }
1670
1671         /*
1672          * Set power & frequency of stopband test tone
1673          */
1674         rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1675
1676         for (i = 0; i < 100; i++) {
1677                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1678                 msleep(1);
1679
1680                 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1681
1682                 if ((passband - stopband) <= filter_target) {
1683                         rfcsr24++;
1684                         overtuned += ((passband - stopband) == filter_target);
1685                 } else
1686                         break;
1687
1688                 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1689         }
1690
1691         rfcsr24 -= !!overtuned;
1692
1693         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1694         return rfcsr24;
1695 }
1696
1697 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1698 {
1699         u8 rfcsr;
1700         u8 bbp;
1701
1702         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1703                 return 0;
1704
1705         /*
1706          * Init RF calibration.
1707          */
1708         rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1709         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1710         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1711         msleep(1);
1712         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1713         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1714
1715         rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1716         rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1717         rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1718         rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1719         rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1720         rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1721         rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1722         rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1723         rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1724         rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1725         rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1726         rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1727         rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1728         rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1729         rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1730         rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1731         rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1732         rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1733         rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1734         rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1735
1736         /*
1737          * Set RX Filter calibration for 20MHz and 40MHz
1738          */
1739         rt2x00dev->calibration[0] =
1740             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1741         rt2x00dev->calibration[1] =
1742             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1743
1744         /*
1745          * Set back to initial state
1746          */
1747         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1748
1749         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1750         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1751         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1752
1753         /*
1754          * set BBP back to BW20
1755          */
1756         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1757         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1758         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1759
1760         return 0;
1761 }
1762
1763 /*
1764  * Device state switch handlers.
1765  */
1766 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1767                                 enum dev_state state)
1768 {
1769         u32 reg;
1770
1771         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1772         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1773                            (state == STATE_RADIO_RX_ON) ||
1774                            (state == STATE_RADIO_RX_ON_LINK));
1775         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1776 }
1777
1778 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1779 {
1780         unsigned int i;
1781         u32 reg;
1782
1783         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1784                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1785                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1786                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1787                         return 0;
1788
1789                 msleep(1);
1790         }
1791
1792         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1793         return -EACCES;
1794 }
1795
1796 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1797 {
1798         u32 reg;
1799         u16 word;
1800
1801         /*
1802          * Initialize all registers.
1803          */
1804         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1805                      rt2800usb_init_registers(rt2x00dev) ||
1806                      rt2800usb_init_bbp(rt2x00dev) ||
1807                      rt2800usb_init_rfcsr(rt2x00dev)))
1808                 return -EIO;
1809
1810         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1811         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1812         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1813
1814         udelay(50);
1815
1816         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1817         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1818         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1819         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1820         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1821
1822
1823         rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1824         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1825         /* Don't use bulk in aggregation when working with USB 1.1 */
1826         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1827                            (rt2x00dev->rx->usb_maxpacket == 512));
1828         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1829         /*
1830          * Total room for RX frames in kilobytes, PBF might still exceed
1831          * this limit so reduce the number to prevent errors.
1832          */
1833         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1834                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1835         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1836         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1837         rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1838
1839         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1840         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1841         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1842         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1843
1844         /*
1845          * Initialize LED control
1846          */
1847         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1848         rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1849                               word & 0xff, (word >> 8) & 0xff);
1850
1851         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1852         rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1853                               word & 0xff, (word >> 8) & 0xff);
1854
1855         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1856         rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1857                               word & 0xff, (word >> 8) & 0xff);
1858
1859         return 0;
1860 }
1861
1862 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1863 {
1864         u32 reg;
1865
1866         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1867         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1868         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1869         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1870
1871         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1872         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1873         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1874
1875         /* Wait for DMA, ignore error */
1876         rt2800usb_wait_wpdma_ready(rt2x00dev);
1877
1878         rt2x00usb_disable_radio(rt2x00dev);
1879 }
1880
1881 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1882                                enum dev_state state)
1883 {
1884         if (state == STATE_AWAKE)
1885                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1886         else
1887                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1888
1889         return 0;
1890 }
1891
1892 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1893                                       enum dev_state state)
1894 {
1895         int retval = 0;
1896
1897         switch (state) {
1898         case STATE_RADIO_ON:
1899                 /*
1900                  * Before the radio can be enabled, the device first has
1901                  * to be woken up. After that it needs a bit of time
1902                  * to be fully awake and then the radio can be enabled.
1903                  */
1904                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1905                 msleep(1);
1906                 retval = rt2800usb_enable_radio(rt2x00dev);
1907                 break;
1908         case STATE_RADIO_OFF:
1909                 /*
1910                  * After the radio has been disabled, the device should
1911                  * be put to sleep for powersaving.
1912                  */
1913                 rt2800usb_disable_radio(rt2x00dev);
1914                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1915                 break;
1916         case STATE_RADIO_RX_ON:
1917         case STATE_RADIO_RX_ON_LINK:
1918         case STATE_RADIO_RX_OFF:
1919         case STATE_RADIO_RX_OFF_LINK:
1920                 rt2800usb_toggle_rx(rt2x00dev, state);
1921                 break;
1922         case STATE_RADIO_IRQ_ON:
1923         case STATE_RADIO_IRQ_OFF:
1924                 /* No support, but no error either */
1925                 break;
1926         case STATE_DEEP_SLEEP:
1927         case STATE_SLEEP:
1928         case STATE_STANDBY:
1929         case STATE_AWAKE:
1930                 retval = rt2800usb_set_state(rt2x00dev, state);
1931                 break;
1932         default:
1933                 retval = -ENOTSUPP;
1934                 break;
1935         }
1936
1937         if (unlikely(retval))
1938                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1939                       state, retval);
1940
1941         return retval;
1942 }
1943
1944 /*
1945  * TX descriptor initialization
1946  */
1947 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1948                                     struct sk_buff *skb,
1949                                     struct txentry_desc *txdesc)
1950 {
1951         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1952         __le32 *txi = skbdesc->desc;
1953         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1954         u32 word;
1955
1956         /*
1957          * Initialize TX Info descriptor
1958          */
1959         rt2x00_desc_read(txwi, 0, &word);
1960         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1961                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1962         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1963         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1964         rt2x00_set_field32(&word, TXWI_W0_TS,
1965                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1966         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1967                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1968         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1969         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1970         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1971         rt2x00_set_field32(&word, TXWI_W0_BW,
1972                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1973         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1974                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1975         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1976         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1977         rt2x00_desc_write(txwi, 0, word);
1978
1979         rt2x00_desc_read(txwi, 1, &word);
1980         rt2x00_set_field32(&word, TXWI_W1_ACK,
1981                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1982         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1983                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1984         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1985         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1986                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1987                            txdesc->key_idx : 0xff);
1988         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
1989                            skb->len - txdesc->l2pad);
1990         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1991                            skbdesc->entry->queue->qid + 1);
1992         rt2x00_desc_write(txwi, 1, word);
1993
1994         /*
1995          * Always write 0 to IV/EIV fields, hardware will insert the IV
1996          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
1997          * When TXINFO_W0_WIV is set to 1 it will use the IV data
1998          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
1999          * crypto entry in the registers should be used to encrypt the frame.
2000          */
2001         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2002         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2003
2004         /*
2005          * Initialize TX descriptor
2006          */
2007         rt2x00_desc_read(txi, 0, &word);
2008         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2009                            skb->len + TXWI_DESC_SIZE);
2010         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2011                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2012         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2013         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2014         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2015         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2016                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2017         rt2x00_desc_write(txi, 0, word);
2018 }
2019
2020 /*
2021  * TX data initialization
2022  */
2023 static void rt2800usb_write_beacon(struct queue_entry *entry)
2024 {
2025         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2026         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2027         unsigned int beacon_base;
2028         u32 reg;
2029
2030         /*
2031          * Add the descriptor in front of the skb.
2032          */
2033         skb_push(entry->skb, entry->queue->desc_size);
2034         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2035         skbdesc->desc = entry->skb->data;
2036
2037         /*
2038          * Disable beaconing while we are reloading the beacon data,
2039          * otherwise we might be sending out invalid data.
2040          */
2041         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2042         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2043         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2044
2045         /*
2046          * Write entire beacon with descriptor to register.
2047          */
2048         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2049         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2050                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2051                                             entry->skb->data, entry->skb->len,
2052                                             REGISTER_TIMEOUT32(entry->skb->len));
2053
2054         /*
2055          * Clean up the beacon skb.
2056          */
2057         dev_kfree_skb(entry->skb);
2058         entry->skb = NULL;
2059 }
2060
2061 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2062 {
2063         int length;
2064
2065         /*
2066          * The length _must_ include 4 bytes padding,
2067          * it should always be multiple of 4,
2068          * but it must _not_ be a multiple of the USB packet size.
2069          */
2070         length = roundup(entry->skb->len + 4, 4);
2071         length += (4 * !(length % entry->queue->usb_maxpacket));
2072
2073         return length;
2074 }
2075
2076 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2077                                     const enum data_queue_qid queue)
2078 {
2079         u32 reg;
2080
2081         if (queue != QID_BEACON) {
2082                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2083                 return;
2084         }
2085
2086         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2087         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2088                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2089                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2090                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2091                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2092         }
2093 }
2094
2095 /*
2096  * RX control handlers
2097  */
2098 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2099                                   struct rxdone_entry_desc *rxdesc)
2100 {
2101         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2102         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2103         __le32 *rxd = (__le32 *)entry->skb->data;
2104         __le32 *rxwi;
2105         u32 rxd0;
2106         u32 rxwi0;
2107         u32 rxwi1;
2108         u32 rxwi2;
2109         u32 rxwi3;
2110
2111         /*
2112          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2113          * moving of frame data in rt2x00usb.
2114          */
2115         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2116         rxd = (__le32 *)skbdesc->desc;
2117         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2118
2119         /*
2120          * It is now safe to read the descriptor on all architectures.
2121          */
2122         rt2x00_desc_read(rxd, 0, &rxd0);
2123         rt2x00_desc_read(rxwi, 0, &rxwi0);
2124         rt2x00_desc_read(rxwi, 1, &rxwi1);
2125         rt2x00_desc_read(rxwi, 2, &rxwi2);
2126         rt2x00_desc_read(rxwi, 3, &rxwi3);
2127
2128         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2129                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2130
2131         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2132                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2133                 rxdesc->cipher_status =
2134                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2135         }
2136
2137         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2138                 /*
2139                  * Hardware has stripped IV/EIV data from 802.11 frame during
2140                  * decryption. Unfortunately the descriptor doesn't contain
2141                  * any fields with the EIV/IV data either, so they can't
2142                  * be restored by rt2x00lib.
2143                  */
2144                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2145
2146                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2147                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2148                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2149                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2150         }
2151
2152         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2153                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2154
2155         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2156                 rxdesc->dev_flags |= RXDONE_L2PAD;
2157                 skbdesc->flags |= SKBDESC_L2_PADDED;
2158         }
2159
2160         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2161                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2162
2163         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2164                 rxdesc->flags |= RX_FLAG_40MHZ;
2165
2166         /*
2167          * Detect RX rate, always use MCS as signal type.
2168          */
2169         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2170         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2171         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2172
2173         /*
2174          * Mask of 0x8 bit to remove the short preamble flag.
2175          */
2176         if (rxdesc->rate_mode == RATE_MODE_CCK)
2177                 rxdesc->signal &= ~0x8;
2178
2179         rxdesc->rssi =
2180             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2181              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2182
2183         rxdesc->noise =
2184             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2185              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2186
2187         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2188
2189         /*
2190          * Remove RXWI descriptor from start of buffer.
2191          */
2192         skb_pull(entry->skb, skbdesc->desc_len);
2193         skb_trim(entry->skb, rxdesc->size);
2194 }
2195
2196 /*
2197  * Device probe functions.
2198  */
2199 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2200 {
2201         u16 word;
2202         u8 *mac;
2203         u8 default_lna_gain;
2204
2205         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2206
2207         /*
2208          * Start validation of the data that has been read.
2209          */
2210         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2211         if (!is_valid_ether_addr(mac)) {
2212                 random_ether_addr(mac);
2213                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2214         }
2215
2216         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2217         if (word == 0xffff) {
2218                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2219                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2220                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2221                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2222                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2223         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2224                 /*
2225                  * There is a max of 2 RX streams for RT2870 series
2226                  */
2227                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2228                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2229                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2230         }
2231
2232         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2233         if (word == 0xffff) {
2234                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2235                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2236                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2237                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2238                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2239                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2240                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2241                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2242                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2243                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2244                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2245                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2246         }
2247
2248         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2249         if ((word & 0x00ff) == 0x00ff) {
2250                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2251                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2252                                    LED_MODE_TXRX_ACTIVITY);
2253                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2254                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2255                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2256                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2257                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2258                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2259         }
2260
2261         /*
2262          * During the LNA validation we are going to use
2263          * lna0 as correct value. Note that EEPROM_LNA
2264          * is never validated.
2265          */
2266         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2267         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2268
2269         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2270         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2271                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2272         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2273                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2274         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2275
2276         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2277         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2278                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2279         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2280             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2281                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2282                                    default_lna_gain);
2283         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2284
2285         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2286         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2287                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2288         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2289                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2290         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2291
2292         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2293         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2294                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2295         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2296             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2297                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2298                                    default_lna_gain);
2299         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2300
2301         return 0;
2302 }
2303
2304 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2305 {
2306         u32 reg;
2307         u16 value;
2308         u16 eeprom;
2309
2310         /*
2311          * Read EEPROM word for configuration.
2312          */
2313         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2314
2315         /*
2316          * Identify RF chipset.
2317          */
2318         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2319         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2320         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2321
2322         /*
2323          * The check for rt2860 is not a typo, some rt2870 hardware
2324          * identifies itself as rt2860 in the CSR register.
2325          */
2326         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2327             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2328             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2329             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2330                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2331                 return -ENODEV;
2332         }
2333
2334         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2335             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2336             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2337             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2338             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2339             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2340                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2341                 return -ENODEV;
2342         }
2343
2344         /*
2345          * Identify default antenna configuration.
2346          */
2347         rt2x00dev->default_ant.tx =
2348             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2349         rt2x00dev->default_ant.rx =
2350             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2351
2352         /*
2353          * Read frequency offset and RF programming sequence.
2354          */
2355         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2356         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2357
2358         /*
2359          * Read external LNA informations.
2360          */
2361         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2362
2363         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2364                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2365         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2366                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2367
2368         /*
2369          * Detect if this device has an hardware controlled radio.
2370          */
2371         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2372                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2373
2374         /*
2375          * Store led settings, for correct led behaviour.
2376          */
2377 #ifdef CONFIG_RT2X00_LIB_LEDS
2378         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2379         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2380         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2381
2382         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2383                            &rt2x00dev->led_mcu_reg);
2384 #endif /* CONFIG_RT2X00_LIB_LEDS */
2385
2386         return 0;
2387 }
2388
2389 /*
2390  * RF value list for rt2870
2391  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2392  */
2393 static const struct rf_channel rf_vals[] = {
2394         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2395         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2396         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2397         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2398         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2399         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2400         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2401         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2402         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2403         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2404         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2405         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2406         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2407         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2408
2409         /* 802.11 UNI / HyperLan 2 */
2410         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2411         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2412         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2413         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2414         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2415         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2416         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2417         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2418         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2419         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2420         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2421         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2422
2423         /* 802.11 HyperLan 2 */
2424         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2425         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2426         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2427         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2428         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2429         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2430         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2431         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2432         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2433         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2434         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2435         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2436         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2437         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2438         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2439         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2440
2441         /* 802.11 UNII */
2442         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2443         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2444         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2445         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2446         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2447         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2448         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2449         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2450         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2451         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2452         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2453
2454         /* 802.11 Japan */
2455         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2456         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2457         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2458         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2459         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2460         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2461         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2462 };
2463
2464 /*
2465  * RF value list for rt3070
2466  * Supports: 2.4 GHz
2467  */
2468 static const struct rf_channel rf_vals_3070[] = {
2469         {1,  241, 2, 2 },
2470         {2,  241, 2, 7 },
2471         {3,  242, 2, 2 },
2472         {4,  242, 2, 7 },
2473         {5,  243, 2, 2 },
2474         {6,  243, 2, 7 },
2475         {7,  244, 2, 2 },
2476         {8,  244, 2, 7 },
2477         {9,  245, 2, 2 },
2478         {10, 245, 2, 7 },
2479         {11, 246, 2, 2 },
2480         {12, 246, 2, 7 },
2481         {13, 247, 2, 2 },
2482         {14, 248, 2, 4 },
2483 };
2484
2485 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2486 {
2487         struct hw_mode_spec *spec = &rt2x00dev->spec;
2488         struct channel_info *info;
2489         char *tx_power1;
2490         char *tx_power2;
2491         unsigned int i;
2492         u16 eeprom;
2493
2494         /*
2495          * Initialize all hw fields.
2496          */
2497         rt2x00dev->hw->flags =
2498             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2499             IEEE80211_HW_SIGNAL_DBM |
2500             IEEE80211_HW_SUPPORTS_PS |
2501             IEEE80211_HW_PS_NULLFUNC_STACK;
2502         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2503
2504         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2505         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2506                                 rt2x00_eeprom_addr(rt2x00dev,
2507                                                    EEPROM_MAC_ADDR_0));
2508
2509         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2510
2511         /*
2512          * Initialize HT information.
2513          */
2514         spec->ht.ht_supported = true;
2515         spec->ht.cap =
2516             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2517             IEEE80211_HT_CAP_GRN_FLD |
2518             IEEE80211_HT_CAP_SGI_20 |
2519             IEEE80211_HT_CAP_SGI_40 |
2520             IEEE80211_HT_CAP_TX_STBC |
2521             IEEE80211_HT_CAP_RX_STBC |
2522             IEEE80211_HT_CAP_PSMP_SUPPORT;
2523         spec->ht.ampdu_factor = 3;
2524         spec->ht.ampdu_density = 4;
2525         spec->ht.mcs.tx_params =
2526             IEEE80211_HT_MCS_TX_DEFINED |
2527             IEEE80211_HT_MCS_TX_RX_DIFF |
2528             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2529                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2530
2531         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2532         case 3:
2533                 spec->ht.mcs.rx_mask[2] = 0xff;
2534         case 2:
2535                 spec->ht.mcs.rx_mask[1] = 0xff;
2536         case 1:
2537                 spec->ht.mcs.rx_mask[0] = 0xff;
2538                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2539                 break;
2540         }
2541
2542         /*
2543          * Initialize hw_mode information.
2544          */
2545         spec->supported_bands = SUPPORT_BAND_2GHZ;
2546         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2547
2548         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2549             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2550                 spec->num_channels = 14;
2551                 spec->channels = rf_vals;
2552         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2553                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2554                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2555                 spec->num_channels = ARRAY_SIZE(rf_vals);
2556                 spec->channels = rf_vals;
2557         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2558                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2559                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2560                 spec->channels = rf_vals_3070;
2561         }
2562
2563         /*
2564          * Create channel information array
2565          */
2566         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2567         if (!info)
2568                 return -ENOMEM;
2569
2570         spec->channels_info = info;
2571
2572         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2573         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2574
2575         for (i = 0; i < 14; i++) {
2576                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2577                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2578         }
2579
2580         if (spec->num_channels > 14) {
2581                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2582                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2583
2584                 for (i = 14; i < spec->num_channels; i++) {
2585                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2586                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2587                 }
2588         }
2589
2590         return 0;
2591 }
2592
2593 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2594 {
2595         int retval;
2596
2597         /*
2598          * Allocate eeprom data.
2599          */
2600         retval = rt2800usb_validate_eeprom(rt2x00dev);
2601         if (retval)
2602                 return retval;
2603
2604         retval = rt2800usb_init_eeprom(rt2x00dev);
2605         if (retval)
2606                 return retval;
2607
2608         /*
2609          * Initialize hw specifications.
2610          */
2611         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2612         if (retval)
2613                 return retval;
2614
2615         /*
2616          * This device has multiple filters for control frames
2617          * and has a separate filter for PS Poll frames.
2618          */
2619         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2620         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2621
2622         /*
2623          * This device requires firmware.
2624          */
2625         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2626         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2627         if (!modparam_nohwcrypt)
2628                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2629
2630         /*
2631          * Set the rssi offset.
2632          */
2633         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2634
2635         return 0;
2636 }
2637
2638 /*
2639  * IEEE80211 stack callback functions.
2640  */
2641 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2642                                    u32 *iv32, u16 *iv16)
2643 {
2644         struct rt2x00_dev *rt2x00dev = hw->priv;
2645         struct mac_iveiv_entry iveiv_entry;
2646         u32 offset;
2647
2648         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2649         rt2800_register_multiread(rt2x00dev, offset,
2650                                       &iveiv_entry, sizeof(iveiv_entry));
2651
2652         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2653         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2654 }
2655
2656 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2657 {
2658         struct rt2x00_dev *rt2x00dev = hw->priv;
2659         u32 reg;
2660         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2661
2662         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2663         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2664         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2665
2666         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2667         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2668         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2669
2670         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2671         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2672         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2673
2674         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2675         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2676         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2677
2678         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2679         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2680         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2681
2682         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2683         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2684         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2685
2686         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2687         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2688         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2689
2690         return 0;
2691 }
2692
2693 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2694                              const struct ieee80211_tx_queue_params *params)
2695 {
2696         struct rt2x00_dev *rt2x00dev = hw->priv;
2697         struct data_queue *queue;
2698         struct rt2x00_field32 field;
2699         int retval;
2700         u32 reg;
2701         u32 offset;
2702
2703         /*
2704          * First pass the configuration through rt2x00lib, that will
2705          * update the queue settings and validate the input. After that
2706          * we are free to update the registers based on the value
2707          * in the queue parameter.
2708          */
2709         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2710         if (retval)
2711                 return retval;
2712
2713         /*
2714          * We only need to perform additional register initialization
2715          * for WMM queues/
2716          */
2717         if (queue_idx >= 4)
2718                 return 0;
2719
2720         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2721
2722         /* Update WMM TXOP register */
2723         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2724         field.bit_offset = (queue_idx & 1) * 16;
2725         field.bit_mask = 0xffff << field.bit_offset;
2726
2727         rt2800_register_read(rt2x00dev, offset, &reg);
2728         rt2x00_set_field32(&reg, field, queue->txop);
2729         rt2800_register_write(rt2x00dev, offset, reg);
2730
2731         /* Update WMM registers */
2732         field.bit_offset = queue_idx * 4;
2733         field.bit_mask = 0xf << field.bit_offset;
2734
2735         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2736         rt2x00_set_field32(&reg, field, queue->aifs);
2737         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2738
2739         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2740         rt2x00_set_field32(&reg, field, queue->cw_min);
2741         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2742
2743         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2744         rt2x00_set_field32(&reg, field, queue->cw_max);
2745         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2746
2747         /* Update EDCA registers */
2748         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2749
2750         rt2800_register_read(rt2x00dev, offset, &reg);
2751         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2752         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2753         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2754         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2755         rt2800_register_write(rt2x00dev, offset, reg);
2756
2757         return 0;
2758 }
2759
2760 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2761 {
2762         struct rt2x00_dev *rt2x00dev = hw->priv;
2763         u64 tsf;
2764         u32 reg;
2765
2766         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2767         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2768         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2769         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2770
2771         return tsf;
2772 }
2773
2774 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2775         .tx                     = rt2x00mac_tx,
2776         .start                  = rt2x00mac_start,
2777         .stop                   = rt2x00mac_stop,
2778         .add_interface          = rt2x00mac_add_interface,
2779         .remove_interface       = rt2x00mac_remove_interface,
2780         .config                 = rt2x00mac_config,
2781         .configure_filter       = rt2x00mac_configure_filter,
2782         .set_tim                = rt2x00mac_set_tim,
2783         .set_key                = rt2x00mac_set_key,
2784         .get_stats              = rt2x00mac_get_stats,
2785         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2786         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2787         .bss_info_changed       = rt2x00mac_bss_info_changed,
2788         .conf_tx                = rt2800usb_conf_tx,
2789         .get_tx_stats           = rt2x00mac_get_tx_stats,
2790         .get_tsf                = rt2800usb_get_tsf,
2791         .rfkill_poll            = rt2x00mac_rfkill_poll,
2792 };
2793
2794 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2795         .probe_hw               = rt2800usb_probe_hw,
2796         .get_firmware_name      = rt2800usb_get_firmware_name,
2797         .check_firmware         = rt2800usb_check_firmware,
2798         .load_firmware          = rt2800usb_load_firmware,
2799         .initialize             = rt2x00usb_initialize,
2800         .uninitialize           = rt2x00usb_uninitialize,
2801         .clear_entry            = rt2x00usb_clear_entry,
2802         .set_device_state       = rt2800usb_set_device_state,
2803         .rfkill_poll            = rt2800usb_rfkill_poll,
2804         .link_stats             = rt2800usb_link_stats,
2805         .reset_tuner            = rt2800usb_reset_tuner,
2806         .link_tuner             = rt2800usb_link_tuner,
2807         .write_tx_desc          = rt2800usb_write_tx_desc,
2808         .write_tx_data          = rt2x00usb_write_tx_data,
2809         .write_beacon           = rt2800usb_write_beacon,
2810         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2811         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2812         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2813         .fill_rxdone            = rt2800usb_fill_rxdone,
2814         .config_shared_key      = rt2800usb_config_shared_key,
2815         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2816         .config_filter          = rt2800usb_config_filter,
2817         .config_intf            = rt2800usb_config_intf,
2818         .config_erp             = rt2800usb_config_erp,
2819         .config_ant             = rt2800usb_config_ant,
2820         .config                 = rt2800usb_config,
2821 };
2822
2823 static const struct data_queue_desc rt2800usb_queue_rx = {
2824         .entry_num              = RX_ENTRIES,
2825         .data_size              = AGGREGATION_SIZE,
2826         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2827         .priv_size              = sizeof(struct queue_entry_priv_usb),
2828 };
2829
2830 static const struct data_queue_desc rt2800usb_queue_tx = {
2831         .entry_num              = TX_ENTRIES,
2832         .data_size              = AGGREGATION_SIZE,
2833         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2834         .priv_size              = sizeof(struct queue_entry_priv_usb),
2835 };
2836
2837 static const struct data_queue_desc rt2800usb_queue_bcn = {
2838         .entry_num              = 8 * BEACON_ENTRIES,
2839         .data_size              = MGMT_FRAME_SIZE,
2840         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2841         .priv_size              = sizeof(struct queue_entry_priv_usb),
2842 };
2843
2844 static const struct rt2x00_ops rt2800usb_ops = {
2845         .name           = KBUILD_MODNAME,
2846         .max_sta_intf   = 1,
2847         .max_ap_intf    = 8,
2848         .eeprom_size    = EEPROM_SIZE,
2849         .rf_size        = RF_SIZE,
2850         .tx_queues      = NUM_TX_QUEUES,
2851         .rx             = &rt2800usb_queue_rx,
2852         .tx             = &rt2800usb_queue_tx,
2853         .bcn            = &rt2800usb_queue_bcn,
2854         .lib            = &rt2800usb_rt2x00_ops,
2855         .hw             = &rt2800usb_mac80211_ops,
2856 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2857         .debugfs        = &rt2800usb_rt2x00debug,
2858 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2859 };
2860
2861 /*
2862  * rt2800usb module information.
2863  */
2864 static struct usb_device_id rt2800usb_device_table[] = {
2865         /* Abocom */
2866         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2867         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2868         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2869         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2870         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2871         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2872         /* AirTies */
2873         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2874         /* Amigo */
2875         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2876         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2877         /* Amit */
2878         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2879         /* ASUS */
2880         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2881         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2882         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2883         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2884         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2885         /* AzureWave */
2886         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2887         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2888         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2889         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2890         /* Belkin */
2891         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2892         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2893         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2894         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2895         /* Buffalo */
2896         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2897         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2898         /* Conceptronic */
2899         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2900         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2901         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2902         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2903         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2904         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2906         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2908         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2909         /* Corega */
2910         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2911         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2912         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2915         /* D-Link */
2916         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2917         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2920         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2922         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2923         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         /* Edimax */
2925         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2926         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2928         /* Encore */
2929         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         /* EnGenius */
2931         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2935         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2937         /* Gemtek */
2938         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         /* Gigabyte */
2940         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2941         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2943         /* Hawking */
2944         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2947         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         /* I-O DATA */
2949         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2950         /* LevelOne */
2951         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2952         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2953         /* Linksys */
2954         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2956         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         /* Logitec */
2958         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2959         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2961         /* Motorola */
2962         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2963         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2964         /* Ovislink */
2965         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2966         /* Pegatron */
2967         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2968         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2970         /* Philips */
2971         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         /* Planex */
2973         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2974         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2975         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         /* Qcom */
2977         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2978         /* Quanta */
2979         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2980         /* Ralink */
2981         { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
2982         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2983         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2985         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2986         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2987         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2988         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2989         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         /* Samsung */
2991         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         /* Siemens */
2993         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2994         /* Sitecom */
2995         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2997         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2999         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3000         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3001         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3002         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3003         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3004         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3005         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3006         { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3007         /* SMC */
3008         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3009         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3010         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3011         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3013         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3014         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3015         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3016         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3017         /* Sparklan */
3018         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3019         /* Sweex */
3020         { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3021         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3022         { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3023         /* U-Media*/
3024         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3025         /* ZCOM */
3026         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3027         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3028         /* Zinwell */
3029         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3030         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3031         { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3032         { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3033         /* Zyxel */
3034         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3035         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3036         { 0, }
3037 };
3038
3039 MODULE_AUTHOR(DRV_PROJECT);
3040 MODULE_VERSION(DRV_VERSION);
3041 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3042 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3043 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3044 MODULE_FIRMWARE(FIRMWARE_RT2870);
3045 MODULE_LICENSE("GPL");
3046
3047 static struct usb_driver rt2800usb_driver = {
3048         .name           = KBUILD_MODNAME,
3049         .id_table       = rt2800usb_device_table,
3050         .probe          = rt2x00usb_probe,
3051         .disconnect     = rt2x00usb_disconnect,
3052         .suspend        = rt2x00usb_suspend,
3053         .resume         = rt2x00usb_resume,
3054 };
3055
3056 static int __init rt2800usb_init(void)
3057 {
3058         return usb_register(&rt2800usb_driver);
3059 }
3060
3061 static void __exit rt2800usb_exit(void)
3062 {
3063         usb_deregister(&rt2800usb_driver);
3064 }
3065
3066 module_init(rt2800usb_init);
3067 module_exit(rt2800usb_exit);