2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
41 * Allow hardware encryption to be disabled.
43 static int modparam_nohwcrypt = 0;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
58 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
63 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
64 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
65 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
67 udelay(REGISTER_BUSY_DELAY);
73 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
74 const unsigned int word, const u8 value)
78 mutex_lock(&rt2x00dev->csr_mutex);
81 * Wait until the BBP becomes ready.
83 reg = rt61pci_bbp_check(rt2x00dev);
84 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
88 * Write the data into the BBP.
91 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
92 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
93 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
94 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
96 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
97 mutex_unlock(&rt2x00dev->csr_mutex);
102 mutex_unlock(&rt2x00dev->csr_mutex);
104 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
107 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
108 const unsigned int word, u8 *value)
112 mutex_lock(&rt2x00dev->csr_mutex);
115 * Wait until the BBP becomes ready.
117 reg = rt61pci_bbp_check(rt2x00dev);
118 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
122 * Write the request into the BBP.
125 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
126 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
127 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
129 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
132 * Wait until the BBP becomes ready.
134 reg = rt61pci_bbp_check(rt2x00dev);
135 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
138 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
139 mutex_unlock(&rt2x00dev->csr_mutex);
144 mutex_unlock(&rt2x00dev->csr_mutex);
146 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
150 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
151 const unsigned int word, const u32 value)
159 mutex_lock(&rt2x00dev->csr_mutex);
161 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
162 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
163 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
165 udelay(REGISTER_BUSY_DELAY);
168 mutex_unlock(&rt2x00dev->csr_mutex);
169 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
174 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
175 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
176 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
177 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
179 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
180 rt2x00_rf_write(rt2x00dev, word, value);
182 mutex_unlock(&rt2x00dev->csr_mutex);
185 #ifdef CONFIG_RT2X00_LIB_LEDS
187 * This function is only called from rt61pci_led_brightness()
188 * make gcc happy by placing this function inside the
189 * same ifdef statement as the caller.
191 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
192 const u8 command, const u8 token,
193 const u8 arg0, const u8 arg1)
197 mutex_lock(&rt2x00dev->csr_mutex);
199 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
201 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER))
204 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
205 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
206 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
207 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
208 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
210 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
211 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
212 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
213 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
215 mutex_unlock(&rt2x00dev->csr_mutex);
220 mutex_unlock(&rt2x00dev->csr_mutex);
223 "mcu request error. Request 0x%02x failed for token 0x%02x.\n",
226 #endif /* CONFIG_RT2X00_LIB_LEDS */
228 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
230 struct rt2x00_dev *rt2x00dev = eeprom->data;
233 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
235 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
236 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
237 eeprom->reg_data_clock =
238 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
239 eeprom->reg_chip_select =
240 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
243 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
245 struct rt2x00_dev *rt2x00dev = eeprom->data;
248 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
249 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
250 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
251 !!eeprom->reg_data_clock);
252 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
253 !!eeprom->reg_chip_select);
255 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
258 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
259 static const struct rt2x00debug rt61pci_rt2x00debug = {
260 .owner = THIS_MODULE,
262 .read = rt2x00pci_register_read,
263 .write = rt2x00pci_register_write,
264 .flags = RT2X00DEBUGFS_OFFSET,
265 .word_base = CSR_REG_BASE,
266 .word_size = sizeof(u32),
267 .word_count = CSR_REG_SIZE / sizeof(u32),
270 .read = rt2x00_eeprom_read,
271 .write = rt2x00_eeprom_write,
272 .word_base = EEPROM_BASE,
273 .word_size = sizeof(u16),
274 .word_count = EEPROM_SIZE / sizeof(u16),
277 .read = rt61pci_bbp_read,
278 .write = rt61pci_bbp_write,
279 .word_base = BBP_BASE,
280 .word_size = sizeof(u8),
281 .word_count = BBP_SIZE / sizeof(u8),
284 .read = rt2x00_rf_read,
285 .write = rt61pci_rf_write,
286 .word_base = RF_BASE,
287 .word_size = sizeof(u32),
288 .word_count = RF_SIZE / sizeof(u32),
291 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
293 #ifdef CONFIG_RT2X00_LIB_RFKILL
294 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
298 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
299 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
302 #define rt61pci_rfkill_poll NULL
303 #endif /* CONFIG_RT2X00_LIB_RFKILL */
305 #ifdef CONFIG_RT2X00_LIB_LEDS
306 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
307 enum led_brightness brightness)
309 struct rt2x00_led *led =
310 container_of(led_cdev, struct rt2x00_led, led_dev);
311 unsigned int enabled = brightness != LED_OFF;
312 unsigned int a_mode =
313 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
314 unsigned int bg_mode =
315 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
317 if (led->type == LED_TYPE_RADIO) {
318 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
319 MCU_LEDCS_RADIO_STATUS, enabled);
321 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
322 (led->rt2x00dev->led_mcu_reg & 0xff),
323 ((led->rt2x00dev->led_mcu_reg >> 8)));
324 } else if (led->type == LED_TYPE_ASSOC) {
325 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
326 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
327 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
328 MCU_LEDCS_LINK_A_STATUS, a_mode);
330 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
331 (led->rt2x00dev->led_mcu_reg & 0xff),
332 ((led->rt2x00dev->led_mcu_reg >> 8)));
333 } else if (led->type == LED_TYPE_QUALITY) {
335 * The brightness is divided into 6 levels (0 - 5),
336 * this means we need to convert the brightness
337 * argument into the matching level within that range.
339 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
340 brightness / (LED_FULL / 6), 0);
344 static int rt61pci_blink_set(struct led_classdev *led_cdev,
345 unsigned long *delay_on,
346 unsigned long *delay_off)
348 struct rt2x00_led *led =
349 container_of(led_cdev, struct rt2x00_led, led_dev);
352 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
353 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
354 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
355 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
360 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
361 struct rt2x00_led *led,
364 led->rt2x00dev = rt2x00dev;
366 led->led_dev.brightness_set = rt61pci_brightness_set;
367 led->led_dev.blink_set = rt61pci_blink_set;
368 led->flags = LED_INITIALIZED;
370 #endif /* CONFIG_RT2X00_LIB_LEDS */
373 * Configuration handlers.
375 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
376 struct rt2x00lib_crypto *crypto,
377 struct ieee80211_key_conf *key)
379 struct hw_key_entry key_entry;
380 struct rt2x00_field32 field;
384 if (crypto->cmd == SET_KEY) {
386 * rt2x00lib can't determine the correct free
387 * key_idx for shared keys. We have 1 register
388 * with key valid bits. The goal is simple, read
389 * the register, if that is full we have no slots
391 * Note that each BSS is allowed to have up to 4
392 * shared keys, so put a mask over the allowed
395 mask = (0xf << crypto->bssidx);
397 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
400 if (reg && reg == mask)
403 key->hw_key_idx += reg ? ffz(reg) : 0;
406 * Upload key to hardware
408 memcpy(key_entry.key, crypto->key,
409 sizeof(key_entry.key));
410 memcpy(key_entry.tx_mic, crypto->tx_mic,
411 sizeof(key_entry.tx_mic));
412 memcpy(key_entry.rx_mic, crypto->rx_mic,
413 sizeof(key_entry.rx_mic));
415 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
416 rt2x00pci_register_multiwrite(rt2x00dev, reg,
417 &key_entry, sizeof(key_entry));
420 * The cipher types are stored over 2 registers.
421 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
422 * bssidx 1 and 2 keys are stored in SEC_CSR5.
423 * Using the correct defines correctly will cause overhead,
424 * so just calculate the correct offset.
426 if (key->hw_key_idx < 8) {
427 field.bit_offset = (3 * key->hw_key_idx);
428 field.bit_mask = 0x7 << field.bit_offset;
430 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
431 rt2x00_set_field32(®, field, crypto->cipher);
432 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
434 field.bit_offset = (3 * (key->hw_key_idx - 8));
435 field.bit_mask = 0x7 << field.bit_offset;
437 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
438 rt2x00_set_field32(®, field, crypto->cipher);
439 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
443 * The driver does not support the IV/EIV generation
444 * in hardware. However it doesn't support the IV/EIV
445 * inside the ieee80211 frame either, but requires it
446 * to be provided seperately for the descriptor.
447 * rt2x00lib will cut the IV/EIV data out of all frames
448 * given to us by mac80211, but we must tell mac80211
449 * to generate the IV/EIV data.
451 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
455 * SEC_CSR0 contains only single-bit fields to indicate
456 * a particular key is valid. Because using the FIELD32()
457 * defines directly will cause a lot of overhead we use
458 * a calculation to determine the correct bit directly.
460 mask = 1 << key->hw_key_idx;
462 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
463 if (crypto->cmd == SET_KEY)
465 else if (crypto->cmd == DISABLE_KEY)
467 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
472 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
473 struct rt2x00lib_crypto *crypto,
474 struct ieee80211_key_conf *key)
476 struct hw_pairwise_ta_entry addr_entry;
477 struct hw_key_entry key_entry;
481 if (crypto->cmd == SET_KEY) {
483 * rt2x00lib can't determine the correct free
484 * key_idx for pairwise keys. We have 2 registers
485 * with key valid bits. The goal is simple, read
486 * the first register, if that is full move to
488 * When both registers are full, we drop the key,
489 * otherwise we use the first invalid entry.
491 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
492 if (reg && reg == ~0) {
493 key->hw_key_idx = 32;
494 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
495 if (reg && reg == ~0)
499 key->hw_key_idx += reg ? ffz(reg) : 0;
502 * Upload key to hardware
504 memcpy(key_entry.key, crypto->key,
505 sizeof(key_entry.key));
506 memcpy(key_entry.tx_mic, crypto->tx_mic,
507 sizeof(key_entry.tx_mic));
508 memcpy(key_entry.rx_mic, crypto->rx_mic,
509 sizeof(key_entry.rx_mic));
511 memset(&addr_entry, 0, sizeof(addr_entry));
512 memcpy(&addr_entry, crypto->address, ETH_ALEN);
513 addr_entry.cipher = crypto->cipher;
515 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
516 rt2x00pci_register_multiwrite(rt2x00dev, reg,
517 &key_entry, sizeof(key_entry));
519 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
520 rt2x00pci_register_multiwrite(rt2x00dev, reg,
521 &addr_entry, sizeof(addr_entry));
524 * Enable pairwise lookup table for given BSS idx,
525 * without this received frames will not be decrypted
528 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
529 reg |= (1 << crypto->bssidx);
530 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
533 * The driver does not support the IV/EIV generation
534 * in hardware. However it doesn't support the IV/EIV
535 * inside the ieee80211 frame either, but requires it
536 * to be provided seperately for the descriptor.
537 * rt2x00lib will cut the IV/EIV data out of all frames
538 * given to us by mac80211, but we must tell mac80211
539 * to generate the IV/EIV data.
541 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
545 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
546 * a particular key is valid. Because using the FIELD32()
547 * defines directly will cause a lot of overhead we use
548 * a calculation to determine the correct bit directly.
550 if (key->hw_key_idx < 32) {
551 mask = 1 << key->hw_key_idx;
553 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
554 if (crypto->cmd == SET_KEY)
556 else if (crypto->cmd == DISABLE_KEY)
558 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
560 mask = 1 << (key->hw_key_idx - 32);
562 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
563 if (crypto->cmd == SET_KEY)
565 else if (crypto->cmd == DISABLE_KEY)
567 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
573 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
574 const unsigned int filter_flags)
579 * Start configuration steps.
580 * Note that the version error will always be dropped
581 * and broadcast frames will always be accepted since
582 * there is no filter for it at this time.
584 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
585 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
586 !(filter_flags & FIF_FCSFAIL));
587 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
588 !(filter_flags & FIF_PLCPFAIL));
589 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
590 !(filter_flags & FIF_CONTROL));
591 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
592 !(filter_flags & FIF_PROMISC_IN_BSS));
593 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
594 !(filter_flags & FIF_PROMISC_IN_BSS) &&
595 !rt2x00dev->intf_ap_count);
596 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
597 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
598 !(filter_flags & FIF_ALLMULTI));
599 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
600 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
601 !(filter_flags & FIF_CONTROL));
602 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
605 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
606 struct rt2x00_intf *intf,
607 struct rt2x00intf_conf *conf,
608 const unsigned int flags)
610 unsigned int beacon_base;
613 if (flags & CONFIG_UPDATE_TYPE) {
615 * Clear current synchronisation setup.
616 * For the Beacon base registers we only need to clear
617 * the first byte since that byte contains the VALID and OWNER
618 * bits which (when set to 0) will invalidate the entire beacon.
620 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
621 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
624 * Enable synchronisation.
626 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
627 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
628 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
629 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
630 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
633 if (flags & CONFIG_UPDATE_MAC) {
634 reg = le32_to_cpu(conf->mac[1]);
635 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
636 conf->mac[1] = cpu_to_le32(reg);
638 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
639 conf->mac, sizeof(conf->mac));
642 if (flags & CONFIG_UPDATE_BSSID) {
643 reg = le32_to_cpu(conf->bssid[1]);
644 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
645 conf->bssid[1] = cpu_to_le32(reg);
647 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
648 conf->bssid, sizeof(conf->bssid));
652 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
653 struct rt2x00lib_erp *erp)
657 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
658 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
659 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
661 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
662 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
663 !!erp->short_preamble);
664 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
666 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
668 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
669 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
670 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
672 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
673 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
674 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
675 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
676 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
679 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
680 struct antenna_setup *ant)
686 rt61pci_bbp_read(rt2x00dev, 3, &r3);
687 rt61pci_bbp_read(rt2x00dev, 4, &r4);
688 rt61pci_bbp_read(rt2x00dev, 77, &r77);
690 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
691 rt2x00_rf(&rt2x00dev->chip, RF5325));
694 * Configure the RX antenna.
697 case ANTENNA_HW_DIVERSITY:
698 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
699 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
700 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
703 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
704 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
705 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
706 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
708 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
712 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
713 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
714 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
715 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
717 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
721 rt61pci_bbp_write(rt2x00dev, 77, r77);
722 rt61pci_bbp_write(rt2x00dev, 3, r3);
723 rt61pci_bbp_write(rt2x00dev, 4, r4);
726 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
727 struct antenna_setup *ant)
733 rt61pci_bbp_read(rt2x00dev, 3, &r3);
734 rt61pci_bbp_read(rt2x00dev, 4, &r4);
735 rt61pci_bbp_read(rt2x00dev, 77, &r77);
737 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
738 rt2x00_rf(&rt2x00dev->chip, RF2529));
739 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
740 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
743 * Configure the RX antenna.
746 case ANTENNA_HW_DIVERSITY:
747 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
750 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
751 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
755 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
756 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
760 rt61pci_bbp_write(rt2x00dev, 77, r77);
761 rt61pci_bbp_write(rt2x00dev, 3, r3);
762 rt61pci_bbp_write(rt2x00dev, 4, r4);
765 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
766 const int p1, const int p2)
770 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
772 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
773 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
775 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
776 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
778 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
781 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
782 struct antenna_setup *ant)
788 rt61pci_bbp_read(rt2x00dev, 3, &r3);
789 rt61pci_bbp_read(rt2x00dev, 4, &r4);
790 rt61pci_bbp_read(rt2x00dev, 77, &r77);
793 * Configure the RX antenna.
797 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
798 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
799 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
801 case ANTENNA_HW_DIVERSITY:
803 * FIXME: Antenna selection for the rf 2529 is very confusing
804 * in the legacy driver. Just default to antenna B until the
805 * legacy code can be properly translated into rt2x00 code.
809 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
810 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
811 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
815 rt61pci_bbp_write(rt2x00dev, 77, r77);
816 rt61pci_bbp_write(rt2x00dev, 3, r3);
817 rt61pci_bbp_write(rt2x00dev, 4, r4);
823 * value[0] -> non-LNA
829 static const struct antenna_sel antenna_sel_a[] = {
830 { 96, { 0x58, 0x78 } },
831 { 104, { 0x38, 0x48 } },
832 { 75, { 0xfe, 0x80 } },
833 { 86, { 0xfe, 0x80 } },
834 { 88, { 0xfe, 0x80 } },
835 { 35, { 0x60, 0x60 } },
836 { 97, { 0x58, 0x58 } },
837 { 98, { 0x58, 0x58 } },
840 static const struct antenna_sel antenna_sel_bg[] = {
841 { 96, { 0x48, 0x68 } },
842 { 104, { 0x2c, 0x3c } },
843 { 75, { 0xfe, 0x80 } },
844 { 86, { 0xfe, 0x80 } },
845 { 88, { 0xfe, 0x80 } },
846 { 35, { 0x50, 0x50 } },
847 { 97, { 0x48, 0x48 } },
848 { 98, { 0x48, 0x48 } },
851 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
852 struct antenna_setup *ant)
854 const struct antenna_sel *sel;
860 * We should never come here because rt2x00lib is supposed
861 * to catch this and send us the correct antenna explicitely.
863 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
864 ant->tx == ANTENNA_SW_DIVERSITY);
866 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
868 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
870 sel = antenna_sel_bg;
871 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
874 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
875 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
877 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
879 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
880 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
881 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
882 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
884 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
886 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
887 rt2x00_rf(&rt2x00dev->chip, RF5325))
888 rt61pci_config_antenna_5x(rt2x00dev, ant);
889 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
890 rt61pci_config_antenna_2x(rt2x00dev, ant);
891 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
892 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
893 rt61pci_config_antenna_2x(rt2x00dev, ant);
895 rt61pci_config_antenna_2529(rt2x00dev, ant);
899 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
900 struct rt2x00lib_conf *libconf)
905 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
906 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
909 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
910 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
912 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
915 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
916 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
919 rt2x00dev->lna_gain = lna_gain;
922 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
923 struct rf_channel *rf, const int txpower)
929 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
930 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
932 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
933 rt2x00_rf(&rt2x00dev->chip, RF2527));
935 rt61pci_bbp_read(rt2x00dev, 3, &r3);
936 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
937 rt61pci_bbp_write(rt2x00dev, 3, r3);
940 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
941 r94 += txpower - MAX_TXPOWER;
942 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
944 rt61pci_bbp_write(rt2x00dev, 94, r94);
946 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
947 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
948 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
949 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
953 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
954 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
955 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
956 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
960 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
961 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
962 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
963 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
968 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
971 struct rf_channel rf;
973 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
974 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
975 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
976 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
978 rt61pci_config_channel(rt2x00dev, &rf, txpower);
981 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
982 struct rt2x00lib_conf *libconf)
986 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
987 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
988 libconf->conf->long_frame_max_tx_count);
989 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
990 libconf->conf->short_frame_max_tx_count);
991 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
994 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
995 struct rt2x00lib_conf *libconf)
999 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1000 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
1001 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1003 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
1004 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
1005 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
1007 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1008 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
1009 libconf->conf->beacon_int * 16);
1010 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1013 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
1014 struct rt2x00lib_conf *libconf,
1015 const unsigned int flags)
1017 /* Always recalculate LNA gain before changing configuration */
1018 rt61pci_config_lna_gain(rt2x00dev, libconf);
1020 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1021 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1022 libconf->conf->power_level);
1023 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1024 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1025 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1026 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1027 rt61pci_config_retry_limit(rt2x00dev, libconf);
1028 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1029 rt61pci_config_duration(rt2x00dev, libconf);
1035 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1036 struct link_qual *qual)
1041 * Update FCS error count from register.
1043 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1044 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1047 * Update False CCA count from register.
1049 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1050 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1053 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1055 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1056 rt2x00dev->link.vgc_level = 0x20;
1059 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1061 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1066 rt61pci_bbp_read(rt2x00dev, 17, &r17);
1069 * Determine r17 bounds.
1071 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1074 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1081 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1088 * If we are not associated, we should go straight to the
1089 * dynamic CCA tuning.
1091 if (!rt2x00dev->intf_associated)
1092 goto dynamic_cca_tune;
1095 * Special big-R17 for very short distance
1099 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1104 * Special big-R17 for short distance
1107 if (r17 != up_bound)
1108 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1113 * Special big-R17 for middle-short distance
1117 if (r17 != low_bound)
1118 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1123 * Special mid-R17 for middle distance
1127 if (r17 != low_bound)
1128 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1133 * Special case: Change up_bound based on the rssi.
1134 * Lower up_bound when rssi is weaker then -74 dBm.
1136 up_bound -= 2 * (-74 - rssi);
1137 if (low_bound > up_bound)
1138 up_bound = low_bound;
1140 if (r17 > up_bound) {
1141 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1148 * r17 does not yet exceed upper limit, continue and base
1149 * the r17 tuning on the false CCA count.
1151 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1152 if (++r17 > up_bound)
1154 rt61pci_bbp_write(rt2x00dev, 17, r17);
1155 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1156 if (--r17 < low_bound)
1158 rt61pci_bbp_write(rt2x00dev, 17, r17);
1163 * Firmware functions
1165 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1169 switch (rt2x00dev->chip.rt) {
1171 fw_name = FIRMWARE_RT2561;
1174 fw_name = FIRMWARE_RT2561s;
1177 fw_name = FIRMWARE_RT2661;
1187 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1192 * Use the crc itu-t algorithm.
1193 * The last 2 bytes in the firmware array are the crc checksum itself,
1194 * this means that we should never pass those 2 bytes to the crc
1197 crc = crc_itu_t(0, data, len - 2);
1198 crc = crc_itu_t_byte(crc, 0);
1199 crc = crc_itu_t_byte(crc, 0);
1204 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1211 * Wait for stable hardware.
1213 for (i = 0; i < 100; i++) {
1214 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1221 ERROR(rt2x00dev, "Unstable hardware.\n");
1226 * Prepare MCU and mailbox for firmware loading.
1229 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1230 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1231 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1232 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1233 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1236 * Write firmware to device.
1239 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1240 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1241 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1243 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1246 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1247 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1249 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1250 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1252 for (i = 0; i < 100; i++) {
1253 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1254 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1260 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1265 * Hardware needs another millisecond before it is ready.
1270 * Reset MAC and BBP registers.
1273 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1274 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1275 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1277 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1278 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1279 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1280 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1282 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1283 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1284 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1290 * Initialization functions.
1292 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1294 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1297 if (entry->queue->qid == QID_RX) {
1298 rt2x00_desc_read(entry_priv->desc, 0, &word);
1300 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1302 rt2x00_desc_read(entry_priv->desc, 0, &word);
1304 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1305 rt2x00_get_field32(word, TXD_W0_VALID));
1309 static void rt61pci_clear_entry(struct queue_entry *entry)
1311 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1312 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1315 if (entry->queue->qid == QID_RX) {
1316 rt2x00_desc_read(entry_priv->desc, 5, &word);
1317 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1319 rt2x00_desc_write(entry_priv->desc, 5, word);
1321 rt2x00_desc_read(entry_priv->desc, 0, &word);
1322 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1323 rt2x00_desc_write(entry_priv->desc, 0, word);
1325 rt2x00_desc_read(entry_priv->desc, 0, &word);
1326 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1327 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1328 rt2x00_desc_write(entry_priv->desc, 0, word);
1332 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1334 struct queue_entry_priv_pci *entry_priv;
1338 * Initialize registers.
1340 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1341 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1342 rt2x00dev->tx[0].limit);
1343 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1344 rt2x00dev->tx[1].limit);
1345 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1346 rt2x00dev->tx[2].limit);
1347 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1348 rt2x00dev->tx[3].limit);
1349 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1351 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1352 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1353 rt2x00dev->tx[0].desc_size / 4);
1354 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1356 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1357 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1358 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1359 entry_priv->desc_dma);
1360 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1362 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1363 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1364 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1365 entry_priv->desc_dma);
1366 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1368 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1369 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1370 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1371 entry_priv->desc_dma);
1372 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1374 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1375 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1376 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1377 entry_priv->desc_dma);
1378 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1380 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1381 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1382 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1383 rt2x00dev->rx->desc_size / 4);
1384 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1385 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1387 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1388 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1389 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1390 entry_priv->desc_dma);
1391 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1393 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1394 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1395 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1396 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1397 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1398 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1400 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1401 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1402 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1403 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1404 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1405 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1407 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1408 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1409 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1414 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1418 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1419 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1420 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1421 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1422 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1424 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1425 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1426 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1427 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1428 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1429 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1430 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1431 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1432 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1433 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1436 * CCK TXD BBP registers
1438 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1439 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1440 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1441 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1442 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1443 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1444 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1445 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1446 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1447 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1450 * OFDM TXD BBP registers
1452 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1453 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1454 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1455 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1456 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1457 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1458 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1459 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1461 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1462 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1463 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1464 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1465 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1466 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1468 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1469 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1470 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1471 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1472 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1473 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1475 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1476 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
1477 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1478 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
1479 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1480 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1481 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1482 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1484 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1486 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1488 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1489 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1490 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1492 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1494 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1497 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1500 * Invalidate all Shared Keys (SEC_CSR0),
1501 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1503 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1504 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1505 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1507 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1508 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1509 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1510 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1512 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1514 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1516 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1520 * For the Beacon base registers we only need to clear
1521 * the first byte since that byte contains the VALID and OWNER
1522 * bits which (when set to 0) will invalidate the entire beacon.
1524 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1525 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1526 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1527 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1530 * We must clear the error counters.
1531 * These registers are cleared on read,
1532 * so we may pass a useless variable to store the value.
1534 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1535 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1536 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1539 * Reset MAC and BBP registers.
1541 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1542 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1543 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1544 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1546 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1547 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1548 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1549 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1551 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1552 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1553 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1558 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1563 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1564 rt61pci_bbp_read(rt2x00dev, 0, &value);
1565 if ((value != 0xff) && (value != 0x00))
1567 udelay(REGISTER_BUSY_DELAY);
1570 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1574 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1581 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1584 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1585 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1586 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1587 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1588 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1589 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1590 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1591 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1592 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1593 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1594 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1595 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1596 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1597 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1598 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1599 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1600 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1601 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1602 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1603 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1604 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1605 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1606 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1607 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1609 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1610 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1612 if (eeprom != 0xffff && eeprom != 0x0000) {
1613 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1614 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1615 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1623 * Device state switch handlers.
1625 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1626 enum dev_state state)
1630 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1631 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1632 (state == STATE_RADIO_RX_OFF) ||
1633 (state == STATE_RADIO_RX_OFF_LINK));
1634 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1637 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1638 enum dev_state state)
1640 int mask = (state == STATE_RADIO_IRQ_OFF);
1644 * When interrupts are being enabled, the interrupt registers
1645 * should clear the register to assure a clean state.
1647 if (state == STATE_RADIO_IRQ_ON) {
1648 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1649 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1651 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1652 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1656 * Only toggle the interrupts bits we are going to use.
1657 * Non-checked interrupt bits are disabled by default.
1659 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1660 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1661 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1662 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1663 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1664 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1666 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1667 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1668 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1669 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1670 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1671 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1672 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1673 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1674 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1675 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1678 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1683 * Initialize all registers.
1685 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1686 rt61pci_init_registers(rt2x00dev) ||
1687 rt61pci_init_bbp(rt2x00dev)))
1693 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1694 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1695 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1700 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1704 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1707 * Disable synchronisation.
1709 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1714 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1715 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1716 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1717 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1718 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1719 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1722 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1728 put_to_sleep = (state != STATE_AWAKE);
1730 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1731 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1732 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1733 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1736 * Device is not guaranteed to be in the requested state yet.
1737 * We must wait until the register indicates that the
1738 * device has entered the correct state.
1740 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1741 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1742 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1743 if (state == !put_to_sleep)
1751 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1752 enum dev_state state)
1757 case STATE_RADIO_ON:
1758 retval = rt61pci_enable_radio(rt2x00dev);
1760 case STATE_RADIO_OFF:
1761 rt61pci_disable_radio(rt2x00dev);
1763 case STATE_RADIO_RX_ON:
1764 case STATE_RADIO_RX_ON_LINK:
1765 case STATE_RADIO_RX_OFF:
1766 case STATE_RADIO_RX_OFF_LINK:
1767 rt61pci_toggle_rx(rt2x00dev, state);
1769 case STATE_RADIO_IRQ_ON:
1770 case STATE_RADIO_IRQ_OFF:
1771 rt61pci_toggle_irq(rt2x00dev, state);
1773 case STATE_DEEP_SLEEP:
1777 retval = rt61pci_set_state(rt2x00dev, state);
1784 if (unlikely(retval))
1785 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1792 * TX descriptor initialization
1794 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1795 struct sk_buff *skb,
1796 struct txentry_desc *txdesc)
1798 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1799 __le32 *txd = skbdesc->desc;
1803 * Start writing the descriptor words.
1805 rt2x00_desc_read(txd, 1, &word);
1806 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1807 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1808 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1809 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1810 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1811 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1812 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1813 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1814 rt2x00_desc_write(txd, 1, word);
1816 rt2x00_desc_read(txd, 2, &word);
1817 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1818 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1819 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1820 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1821 rt2x00_desc_write(txd, 2, word);
1823 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1824 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1825 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1828 rt2x00_desc_read(txd, 5, &word);
1829 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1830 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1831 skbdesc->entry->entry_idx);
1832 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1833 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1834 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1835 rt2x00_desc_write(txd, 5, word);
1837 rt2x00_desc_read(txd, 6, &word);
1838 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1840 rt2x00_desc_write(txd, 6, word);
1842 if (skbdesc->desc_len > TXINFO_SIZE) {
1843 rt2x00_desc_read(txd, 11, &word);
1844 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1845 rt2x00_desc_write(txd, 11, word);
1848 rt2x00_desc_read(txd, 0, &word);
1849 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1850 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1851 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1852 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1853 rt2x00_set_field32(&word, TXD_W0_ACK,
1854 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1855 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1856 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1857 rt2x00_set_field32(&word, TXD_W0_OFDM,
1858 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1859 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1860 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1861 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1862 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1863 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1864 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1865 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1866 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1867 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1868 rt2x00_set_field32(&word, TXD_W0_BURST,
1869 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1870 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1871 rt2x00_desc_write(txd, 0, word);
1875 * TX data initialization
1877 static void rt61pci_write_beacon(struct queue_entry *entry)
1879 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1880 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1881 unsigned int beacon_base;
1885 * Disable beaconing while we are reloading the beacon data,
1886 * otherwise we might be sending out invalid data.
1888 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1889 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1890 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1891 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1892 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1895 * Write entire beacon with descriptor to register.
1897 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1898 rt2x00pci_register_multiwrite(rt2x00dev,
1900 skbdesc->desc, skbdesc->desc_len);
1901 rt2x00pci_register_multiwrite(rt2x00dev,
1902 beacon_base + skbdesc->desc_len,
1903 entry->skb->data, entry->skb->len);
1906 * Clean up beacon skb.
1908 dev_kfree_skb_any(entry->skb);
1912 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1913 const enum data_queue_qid queue)
1917 if (queue == QID_BEACON) {
1919 * For Wi-Fi faily generated beacons between participating
1920 * stations. Set TBTT phase adaptive adjustment step to 8us.
1922 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1924 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1925 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1926 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1927 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1928 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1929 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1934 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1935 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1936 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1937 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1938 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1939 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1943 * RX control handlers
1945 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1947 u8 offset = rt2x00dev->lna_gain;
1950 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1965 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1966 if (lna == 3 || lna == 2)
1970 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1973 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1974 struct rxdone_entry_desc *rxdesc)
1976 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1977 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1981 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1982 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1984 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1985 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1987 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1989 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1990 rxdesc->cipher_status =
1991 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1994 if (rxdesc->cipher != CIPHER_NONE) {
1995 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1996 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1997 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2000 * Hardware has stripped IV/EIV data from 802.11 frame during
2001 * decryption. It has provided the data seperately but rt2x00lib
2002 * should decide if it should be reinserted.
2004 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2007 * FIXME: Legacy driver indicates that the frame does
2008 * contain the Michael Mic. Unfortunately, in rt2x00
2009 * the MIC seems to be missing completely...
2011 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2013 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2014 rxdesc->flags |= RX_FLAG_DECRYPTED;
2015 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2016 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2020 * Obtain the status about this packet.
2021 * When frame was received with an OFDM bitrate,
2022 * the signal is the PLCP value. If it was received with
2023 * a CCK bitrate the signal is the rate in 100kbit/s.
2025 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2026 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2027 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2029 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2030 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2032 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2033 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2034 rxdesc->dev_flags |= RXDONE_MY_BSS;
2038 * Interrupt functions.
2040 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2042 struct data_queue *queue;
2043 struct queue_entry *entry;
2044 struct queue_entry *entry_done;
2045 struct queue_entry_priv_pci *entry_priv;
2046 struct txdone_entry_desc txdesc;
2054 * During each loop we will compare the freshly read
2055 * STA_CSR4 register value with the value read from
2056 * the previous loop. If the 2 values are equal then
2057 * we should stop processing because the chance it
2058 * quite big that the device has been unplugged and
2059 * we risk going into an endless loop.
2064 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
2065 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2073 * Skip this entry when it contains an invalid
2074 * queue identication number.
2076 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2077 queue = rt2x00queue_get_queue(rt2x00dev, type);
2078 if (unlikely(!queue))
2082 * Skip this entry when it contains an invalid
2085 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2086 if (unlikely(index >= queue->limit))
2089 entry = &queue->entries[index];
2090 entry_priv = entry->priv_data;
2091 rt2x00_desc_read(entry_priv->desc, 0, &word);
2093 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2094 !rt2x00_get_field32(word, TXD_W0_VALID))
2097 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2098 while (entry != entry_done) {
2100 * Just report any entries we missed as failed.
2103 "TX status report missed for entry %d\n",
2104 entry_done->entry_idx);
2107 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2110 rt2x00lib_txdone(entry_done, &txdesc);
2111 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2115 * Obtain the status about this packet.
2118 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2119 case 0: /* Success, maybe with retry */
2120 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2122 case 6: /* Failure, excessive retries */
2123 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2124 /* Don't break, this is a failed frame! */
2125 default: /* Failure */
2126 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2128 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2130 rt2x00lib_txdone(entry, &txdesc);
2134 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2136 struct rt2x00_dev *rt2x00dev = dev_instance;
2141 * Get the interrupt sources & saved to local variable.
2142 * Write register value back to clear pending interrupts.
2144 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
2145 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2147 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
2148 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2150 if (!reg && !reg_mcu)
2153 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2157 * Handle interrupts, walk through all bits
2158 * and run the tasks, the bits are checked in order of
2163 * 1 - Rx ring done interrupt.
2165 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2166 rt2x00pci_rxdone(rt2x00dev);
2169 * 2 - Tx ring done interrupt.
2171 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2172 rt61pci_txdone(rt2x00dev);
2175 * 3 - Handle MCU command done.
2178 rt2x00pci_register_write(rt2x00dev,
2179 M2H_CMD_DONE_CSR, 0xffffffff);
2185 * Device probe functions.
2187 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2189 struct eeprom_93cx6 eeprom;
2195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
2197 eeprom.data = rt2x00dev;
2198 eeprom.register_read = rt61pci_eepromregister_read;
2199 eeprom.register_write = rt61pci_eepromregister_write;
2200 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2201 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2202 eeprom.reg_data_in = 0;
2203 eeprom.reg_data_out = 0;
2204 eeprom.reg_data_clock = 0;
2205 eeprom.reg_chip_select = 0;
2207 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2208 EEPROM_SIZE / sizeof(u16));
2211 * Start validation of the data that has been read.
2213 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2214 if (!is_valid_ether_addr(mac)) {
2215 random_ether_addr(mac);
2216 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2219 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2220 if (word == 0xffff) {
2221 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2222 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2224 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2226 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2227 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2228 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2229 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2230 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2231 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2234 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2235 if (word == 0xffff) {
2236 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2237 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2238 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2239 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2240 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2241 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2242 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2243 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2246 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2247 if (word == 0xffff) {
2248 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2250 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2251 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2254 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2255 if (word == 0xffff) {
2256 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2257 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2258 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2259 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2262 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2263 if (word == 0xffff) {
2264 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2265 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2266 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2267 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2269 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2270 if (value < -10 || value > 10)
2271 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2272 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2273 if (value < -10 || value > 10)
2274 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2275 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2278 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2279 if (word == 0xffff) {
2280 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2281 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2282 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2283 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2285 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2286 if (value < -10 || value > 10)
2287 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2288 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2289 if (value < -10 || value > 10)
2290 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2291 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2297 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2305 * Read EEPROM word for configuration.
2307 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2310 * Identify RF chipset.
2311 * To determine the RT chip we have to read the
2312 * PCI header of the device.
2314 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2315 PCI_CONFIG_HEADER_DEVICE, &device);
2316 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2317 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2318 rt2x00_set_chip(rt2x00dev, device, value, reg);
2320 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2321 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2322 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2323 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2324 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2329 * Determine number of antenna's.
2331 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2332 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2335 * Identify default antenna configuration.
2337 rt2x00dev->default_ant.tx =
2338 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2339 rt2x00dev->default_ant.rx =
2340 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2343 * Read the Frame type.
2345 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2346 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2349 * Detect if this device has an hardware controlled radio.
2351 #ifdef CONFIG_RT2X00_LIB_RFKILL
2352 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2353 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2354 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2357 * Read frequency offset and RF programming sequence.
2359 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2360 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2361 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2363 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2366 * Read external LNA informations.
2368 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2370 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2371 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2372 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2373 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2376 * When working with a RF2529 chip without double antenna
2377 * the antenna settings should be gathered from the NIC
2380 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2381 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2382 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2384 rt2x00dev->default_ant.tx = ANTENNA_B;
2385 rt2x00dev->default_ant.rx = ANTENNA_A;
2388 rt2x00dev->default_ant.tx = ANTENNA_B;
2389 rt2x00dev->default_ant.rx = ANTENNA_B;
2392 rt2x00dev->default_ant.tx = ANTENNA_A;
2393 rt2x00dev->default_ant.rx = ANTENNA_A;
2396 rt2x00dev->default_ant.tx = ANTENNA_A;
2397 rt2x00dev->default_ant.rx = ANTENNA_B;
2401 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2402 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2403 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2404 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2408 * Store led settings, for correct led behaviour.
2409 * If the eeprom value is invalid,
2410 * switch to default led mode.
2412 #ifdef CONFIG_RT2X00_LIB_LEDS
2413 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2414 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2416 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2417 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2418 if (value == LED_MODE_SIGNAL_STRENGTH)
2419 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2422 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2423 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2424 rt2x00_get_field16(eeprom,
2425 EEPROM_LED_POLARITY_GPIO_0));
2426 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2427 rt2x00_get_field16(eeprom,
2428 EEPROM_LED_POLARITY_GPIO_1));
2429 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2430 rt2x00_get_field16(eeprom,
2431 EEPROM_LED_POLARITY_GPIO_2));
2432 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2433 rt2x00_get_field16(eeprom,
2434 EEPROM_LED_POLARITY_GPIO_3));
2435 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2436 rt2x00_get_field16(eeprom,
2437 EEPROM_LED_POLARITY_GPIO_4));
2438 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2439 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2440 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2441 rt2x00_get_field16(eeprom,
2442 EEPROM_LED_POLARITY_RDY_G));
2443 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2444 rt2x00_get_field16(eeprom,
2445 EEPROM_LED_POLARITY_RDY_A));
2446 #endif /* CONFIG_RT2X00_LIB_LEDS */
2452 * RF value list for RF5225 & RF5325
2453 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2455 static const struct rf_channel rf_vals_noseq[] = {
2456 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2457 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2458 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2459 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2460 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2461 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2462 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2463 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2464 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2465 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2466 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2467 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2468 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2469 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2471 /* 802.11 UNI / HyperLan 2 */
2472 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2473 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2474 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2475 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2476 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2477 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2478 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2479 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2481 /* 802.11 HyperLan 2 */
2482 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2483 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2484 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2485 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2486 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2487 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2488 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2489 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2490 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2491 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2494 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2495 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2496 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2497 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2498 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2499 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2501 /* MMAC(Japan)J52 ch 34,38,42,46 */
2502 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2503 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2504 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2505 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2509 * RF value list for RF5225 & RF5325
2510 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2512 static const struct rf_channel rf_vals_seq[] = {
2513 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2514 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2515 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2516 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2517 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2518 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2519 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2520 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2521 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2522 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2523 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2524 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2525 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2526 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2528 /* 802.11 UNI / HyperLan 2 */
2529 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2530 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2531 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2532 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2533 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2534 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2535 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2536 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2538 /* 802.11 HyperLan 2 */
2539 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2540 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2541 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2542 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2543 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2544 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2545 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2546 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2547 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2548 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2551 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2552 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2553 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2554 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2555 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2556 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2558 /* MMAC(Japan)J52 ch 34,38,42,46 */
2559 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2560 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2561 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2562 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2565 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2567 struct hw_mode_spec *spec = &rt2x00dev->spec;
2568 struct channel_info *info;
2573 * Initialize all hw fields.
2575 rt2x00dev->hw->flags =
2576 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2577 IEEE80211_HW_SIGNAL_DBM;
2578 rt2x00dev->hw->extra_tx_headroom = 0;
2580 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2581 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2582 rt2x00_eeprom_addr(rt2x00dev,
2583 EEPROM_MAC_ADDR_0));
2586 * Initialize hw_mode information.
2588 spec->supported_bands = SUPPORT_BAND_2GHZ;
2589 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2591 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2592 spec->num_channels = 14;
2593 spec->channels = rf_vals_noseq;
2595 spec->num_channels = 14;
2596 spec->channels = rf_vals_seq;
2599 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2600 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2601 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2602 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2606 * Create channel information array
2608 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2612 spec->channels_info = info;
2614 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2615 for (i = 0; i < 14; i++)
2616 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2618 if (spec->num_channels > 14) {
2619 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2620 for (i = 14; i < spec->num_channels; i++)
2621 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2627 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2632 * Allocate eeprom data.
2634 retval = rt61pci_validate_eeprom(rt2x00dev);
2638 retval = rt61pci_init_eeprom(rt2x00dev);
2643 * Initialize hw specifications.
2645 retval = rt61pci_probe_hw_mode(rt2x00dev);
2650 * This device requires firmware and DMA mapped skbs.
2652 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2653 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2654 if (!modparam_nohwcrypt)
2655 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2658 * Set the rssi offset.
2660 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2666 * IEEE80211 stack callback functions.
2668 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2669 const struct ieee80211_tx_queue_params *params)
2671 struct rt2x00_dev *rt2x00dev = hw->priv;
2672 struct data_queue *queue;
2673 struct rt2x00_field32 field;
2678 * First pass the configuration through rt2x00lib, that will
2679 * update the queue settings and validate the input. After that
2680 * we are free to update the registers based on the value
2681 * in the queue parameter.
2683 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2687 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2689 /* Update WMM TXOP register */
2690 if (queue_idx < 2) {
2691 field.bit_offset = queue_idx * 16;
2692 field.bit_mask = 0xffff << field.bit_offset;
2694 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
2695 rt2x00_set_field32(®, field, queue->txop);
2696 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2697 } else if (queue_idx < 4) {
2698 field.bit_offset = (queue_idx - 2) * 16;
2699 field.bit_mask = 0xffff << field.bit_offset;
2701 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
2702 rt2x00_set_field32(®, field, queue->txop);
2703 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2706 /* Update WMM registers */
2707 field.bit_offset = queue_idx * 4;
2708 field.bit_mask = 0xf << field.bit_offset;
2710 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®);
2711 rt2x00_set_field32(®, field, queue->aifs);
2712 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2714 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®);
2715 rt2x00_set_field32(®, field, queue->cw_min);
2716 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2718 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®);
2719 rt2x00_set_field32(®, field, queue->cw_max);
2720 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2725 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2727 struct rt2x00_dev *rt2x00dev = hw->priv;
2731 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2732 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2733 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2734 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2739 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2741 .start = rt2x00mac_start,
2742 .stop = rt2x00mac_stop,
2743 .add_interface = rt2x00mac_add_interface,
2744 .remove_interface = rt2x00mac_remove_interface,
2745 .config = rt2x00mac_config,
2746 .config_interface = rt2x00mac_config_interface,
2747 .configure_filter = rt2x00mac_configure_filter,
2748 .set_key = rt2x00mac_set_key,
2749 .get_stats = rt2x00mac_get_stats,
2750 .bss_info_changed = rt2x00mac_bss_info_changed,
2751 .conf_tx = rt61pci_conf_tx,
2752 .get_tx_stats = rt2x00mac_get_tx_stats,
2753 .get_tsf = rt61pci_get_tsf,
2756 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2757 .irq_handler = rt61pci_interrupt,
2758 .probe_hw = rt61pci_probe_hw,
2759 .get_firmware_name = rt61pci_get_firmware_name,
2760 .get_firmware_crc = rt61pci_get_firmware_crc,
2761 .load_firmware = rt61pci_load_firmware,
2762 .initialize = rt2x00pci_initialize,
2763 .uninitialize = rt2x00pci_uninitialize,
2764 .get_entry_state = rt61pci_get_entry_state,
2765 .clear_entry = rt61pci_clear_entry,
2766 .set_device_state = rt61pci_set_device_state,
2767 .rfkill_poll = rt61pci_rfkill_poll,
2768 .link_stats = rt61pci_link_stats,
2769 .reset_tuner = rt61pci_reset_tuner,
2770 .link_tuner = rt61pci_link_tuner,
2771 .write_tx_desc = rt61pci_write_tx_desc,
2772 .write_tx_data = rt2x00pci_write_tx_data,
2773 .write_beacon = rt61pci_write_beacon,
2774 .kick_tx_queue = rt61pci_kick_tx_queue,
2775 .fill_rxdone = rt61pci_fill_rxdone,
2776 .config_shared_key = rt61pci_config_shared_key,
2777 .config_pairwise_key = rt61pci_config_pairwise_key,
2778 .config_filter = rt61pci_config_filter,
2779 .config_intf = rt61pci_config_intf,
2780 .config_erp = rt61pci_config_erp,
2781 .config_ant = rt61pci_config_ant,
2782 .config = rt61pci_config,
2785 static const struct data_queue_desc rt61pci_queue_rx = {
2786 .entry_num = RX_ENTRIES,
2787 .data_size = DATA_FRAME_SIZE,
2788 .desc_size = RXD_DESC_SIZE,
2789 .priv_size = sizeof(struct queue_entry_priv_pci),
2792 static const struct data_queue_desc rt61pci_queue_tx = {
2793 .entry_num = TX_ENTRIES,
2794 .data_size = DATA_FRAME_SIZE,
2795 .desc_size = TXD_DESC_SIZE,
2796 .priv_size = sizeof(struct queue_entry_priv_pci),
2799 static const struct data_queue_desc rt61pci_queue_bcn = {
2800 .entry_num = 4 * BEACON_ENTRIES,
2801 .data_size = 0, /* No DMA required for beacons */
2802 .desc_size = TXINFO_SIZE,
2803 .priv_size = sizeof(struct queue_entry_priv_pci),
2806 static const struct rt2x00_ops rt61pci_ops = {
2807 .name = KBUILD_MODNAME,
2810 .eeprom_size = EEPROM_SIZE,
2812 .tx_queues = NUM_TX_QUEUES,
2813 .rx = &rt61pci_queue_rx,
2814 .tx = &rt61pci_queue_tx,
2815 .bcn = &rt61pci_queue_bcn,
2816 .lib = &rt61pci_rt2x00_ops,
2817 .hw = &rt61pci_mac80211_ops,
2818 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2819 .debugfs = &rt61pci_rt2x00debug,
2820 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2824 * RT61pci module information.
2826 static struct pci_device_id rt61pci_device_table[] = {
2828 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2830 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2832 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2836 MODULE_AUTHOR(DRV_PROJECT);
2837 MODULE_VERSION(DRV_VERSION);
2838 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2839 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2840 "PCI & PCMCIA chipset based cards");
2841 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2842 MODULE_FIRMWARE(FIRMWARE_RT2561);
2843 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2844 MODULE_FIRMWARE(FIRMWARE_RT2661);
2845 MODULE_LICENSE("GPL");
2847 static struct pci_driver rt61pci_driver = {
2848 .name = KBUILD_MODNAME,
2849 .id_table = rt61pci_device_table,
2850 .probe = rt2x00pci_probe,
2851 .remove = __devexit_p(rt2x00pci_remove),
2852 .suspend = rt2x00pci_suspend,
2853 .resume = rt2x00pci_resume,
2856 static int __init rt61pci_init(void)
2858 return pci_register_driver(&rt61pci_driver);
2861 static void __exit rt61pci_exit(void)
2863 pci_unregister_driver(&rt61pci_driver);
2866 module_init(rt61pci_init);
2867 module_exit(rt61pci_exit);