drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/pci.h>
  35 #include <linux/eeprom_93cx6.h>
  36
  37 #include "rt2x00.h"
  38 #include "rt2x00pci.h"
  39 #include "rt61pci.h"
  40
  41 /*
  42  * Allow hardware encryption to be disabled.
  43  */
  44 static int modparam_nohwcrypt = 0;
  45 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  47
  48 /*
  49  * Register access.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attempt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  */
  59 #define WAIT_FOR_BBP(__dev, __reg) \
  60         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  61 #define WAIT_FOR_RF(__dev, __reg) \
  62         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  63 #define WAIT_FOR_MCU(__dev, __reg) \
  64         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  65                                H2M_MAILBOX_CSR_OWNER, (__reg))
  66
  67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                               const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         mutex_lock(&rt2x00dev->csr_mutex);
  73
  74         /*
  75          * Wait until the BBP becomes available, afterwards we
  76          * can safely write the new data into the register.
  77          */
  78         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  79                 reg = 0;
  80                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  83                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  84
  85                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  86         }
  87
  88         mutex_unlock(&rt2x00dev->csr_mutex);
  89 }
  90
  91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  92                              const unsigned int word, u8 *value)
  93 {
  94         u32 reg;
  95
  96         mutex_lock(&rt2x00dev->csr_mutex);
  97
  98         /*
  99          * Wait until the BBP becomes available, afterwards we
 100          * can safely write the read request into the register.
 101          * After the data has been written, we wait until hardware
 102          * returns the correct value, if at any time the register
 103          * doesn't become available in time, reg will be 0xffffffff
 104          * which means we return 0xff to the caller.
 105          */
 106         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 107                 reg = 0;
 108                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 110                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 111
 112                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 113
 114                 WAIT_FOR_BBP(rt2x00dev, &reg);
 115         }
 116
 117         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 118
 119         mutex_unlock(&rt2x00dev->csr_mutex);
 120 }
 121
 122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 123                              const unsigned int word, const u32 value)
 124 {
 125         u32 reg;
 126
 127         mutex_lock(&rt2x00dev->csr_mutex);
 128
 129         /*
 130          * Wait until the RF becomes available, afterwards we
 131          * can safely write the new data into the register.
 132          */
 133         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 134                 reg = 0;
 135                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 136                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 137                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 138                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 139
 140                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 141                 rt2x00_rf_write(rt2x00dev, word, value);
 142         }
 143
 144         mutex_unlock(&rt2x00dev->csr_mutex);
 145 }
 146
 147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 148                                 const u8 command, const u8 token,
 149                                 const u8 arg0, const u8 arg1)
 150 {
 151         u32 reg;
 152
 153         mutex_lock(&rt2x00dev->csr_mutex);
 154
 155         /*
 156          * Wait until the MCU becomes available, afterwards we
 157          * can safely write the new data into the register.
 158          */
 159         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 160                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 161                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 164                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 165
 166                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 167                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 168                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 169                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 170         }
 171
 172         mutex_unlock(&rt2x00dev->csr_mutex);
 173
 174 }
 175
 176 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 177 {
 178         struct rt2x00_dev *rt2x00dev = eeprom->data;
 179         u32 reg;
 180
 181         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 182
 183         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 184         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 185         eeprom->reg_data_clock =
 186             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 187         eeprom->reg_chip_select =
 188             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 189 }
 190
 191 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 192 {
 193         struct rt2x00_dev *rt2x00dev = eeprom->data;
 194         u32 reg = 0;
 195
 196         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 197         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 199                            !!eeprom->reg_data_clock);
 200         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 201                            !!eeprom->reg_chip_select);
 202
 203         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 204 }
 205
 206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 207 static const struct rt2x00debug rt61pci_rt2x00debug = {
 208         .owner  = THIS_MODULE,
 209         .csr    = {
 210                 .read           = rt2x00pci_register_read,
 211                 .write          = rt2x00pci_register_write,
 212                 .flags          = RT2X00DEBUGFS_OFFSET,
 213                 .word_base      = CSR_REG_BASE,
 214                 .word_size      = sizeof(u32),
 215                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 216         },
 217         .eeprom = {
 218                 .read           = rt2x00_eeprom_read,
 219                 .write          = rt2x00_eeprom_write,
 220                 .word_base      = EEPROM_BASE,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt61pci_bbp_read,
 226                 .write          = rt61pci_bbp_write,
 227                 .word_base      = BBP_BASE,
 228                 .word_size      = sizeof(u8),
 229                 .word_count     = BBP_SIZE / sizeof(u8),
 230         },
 231         .rf     = {
 232                 .read           = rt2x00_rf_read,
 233                 .write          = rt61pci_rf_write,
 234                 .word_base      = RF_BASE,
 235                 .word_size      = sizeof(u32),
 236                 .word_count     = RF_SIZE / sizeof(u32),
 237         },
 238 };
 239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 240
 241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 242 {
 243         u32 reg;
 244
 245         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 246         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 247 }
 248
 249 #ifdef CONFIG_RT2X00_LIB_LEDS
 250 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 251                                    enum led_brightness brightness)
 252 {
 253         struct rt2x00_led *led =
 254             container_of(led_cdev, struct rt2x00_led, led_dev);
 255         unsigned int enabled = brightness != LED_OFF;
 256         unsigned int a_mode =
 257             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 258         unsigned int bg_mode =
 259             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 260
 261         if (led->type == LED_TYPE_RADIO) {
 262                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 263                                    MCU_LEDCS_RADIO_STATUS, enabled);
 264
 265                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 266                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 267                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 268         } else if (led->type == LED_TYPE_ASSOC) {
 269                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 270                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 271                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 272                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 273
 274                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 275                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 276                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 277         } else if (led->type == LED_TYPE_QUALITY) {
 278                 /*
 279                  * The brightness is divided into 6 levels (0 - 5),
 280                  * this means we need to convert the brightness
 281                  * argument into the matching level within that range.
 282                  */
 283                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 284                                     brightness / (LED_FULL / 6), 0);
 285         }
 286 }
 287
 288 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 289                              unsigned long *delay_on,
 290                              unsigned long *delay_off)
 291 {
 292         struct rt2x00_led *led =
 293             container_of(led_cdev, struct rt2x00_led, led_dev);
 294         u32 reg;
 295
 296         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 297         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 298         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 299         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 300
 301         return 0;
 302 }
 303
 304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 305                              struct rt2x00_led *led,
 306                              enum led_type type)
 307 {
 308         led->rt2x00dev = rt2x00dev;
 309         led->type = type;
 310         led->led_dev.brightness_set = rt61pci_brightness_set;
 311         led->led_dev.blink_set = rt61pci_blink_set;
 312         led->flags = LED_INITIALIZED;
 313 }
 314 #endif /* CONFIG_RT2X00_LIB_LEDS */
 315
 316 /*
 317  * Configuration handlers.
 318  */
 319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 320                                      struct rt2x00lib_crypto *crypto,
 321                                      struct ieee80211_key_conf *key)
 322 {
 323         struct hw_key_entry key_entry;
 324         struct rt2x00_field32 field;
 325         u32 mask;
 326         u32 reg;
 327
 328         if (crypto->cmd == SET_KEY) {
 329                 /*
 330                  * rt2x00lib can't determine the correct free
 331                  * key_idx for shared keys. We have 1 register
 332                  * with key valid bits. The goal is simple, read
 333                  * the register, if that is full we have no slots
 334                  * left.
 335                  * Note that each BSS is allowed to have up to 4
 336                  * shared keys, so put a mask over the allowed
 337                  * entries.
 338                  */
 339                 mask = (0xf << crypto->bssidx);
 340
 341                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 342                 reg &= mask;
 343
 344                 if (reg && reg == mask)
 345                         return -ENOSPC;
 346
 347                 key->hw_key_idx += reg ? ffz(reg) : 0;
 348
 349                 /*
 350                  * Upload key to hardware
 351                  */
 352                 memcpy(key_entry.key, crypto->key,
 353                        sizeof(key_entry.key));
 354                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 355                        sizeof(key_entry.tx_mic));
 356                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 357                        sizeof(key_entry.rx_mic));
 358
 359                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 360                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 361                                               &key_entry, sizeof(key_entry));
 362
 363                 /*
 364                  * The cipher types are stored over 2 registers.
 365                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 366                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 367                  * Using the correct defines correctly will cause overhead,
 368                  * so just calculate the correct offset.
 369                  */
 370                 if (key->hw_key_idx < 8) {
 371                         field.bit_offset = (3 * key->hw_key_idx);
 372                         field.bit_mask = 0x7 << field.bit_offset;
 373
 374                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 375                         rt2x00_set_field32(&reg, field, crypto->cipher);
 376                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 377                 } else {
 378                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 379                         field.bit_mask = 0x7 << field.bit_offset;
 380
 381                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 382                         rt2x00_set_field32(&reg, field, crypto->cipher);
 383                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 384                 }
 385
 386                 /*
 387                  * The driver does not support the IV/EIV generation
 388                  * in hardware. However it doesn't support the IV/EIV
 389                  * inside the ieee80211 frame either, but requires it
 390                  * to be provided separately for the descriptor.
 391                  * rt2x00lib will cut the IV/EIV data out of all frames
 392                  * given to us by mac80211, but we must tell mac80211
 393                  * to generate the IV/EIV data.
 394                  */
 395                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 396         }
 397
 398         /*
 399          * SEC_CSR0 contains only single-bit fields to indicate
 400          * a particular key is valid. Because using the FIELD32()
 401          * defines directly will cause a lot of overhead, we use
 402          * a calculation to determine the correct bit directly.
 403          */
 404         mask = 1 << key->hw_key_idx;
 405
 406         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 407         if (crypto->cmd == SET_KEY)
 408                 reg |= mask;
 409         else if (crypto->cmd == DISABLE_KEY)
 410                 reg &= ~mask;
 411         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 412
 413         return 0;
 414 }
 415
 416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 417                                        struct rt2x00lib_crypto *crypto,
 418                                        struct ieee80211_key_conf *key)
 419 {
 420         struct hw_pairwise_ta_entry addr_entry;
 421         struct hw_key_entry key_entry;
 422         u32 mask;
 423         u32 reg;
 424
 425         if (crypto->cmd == SET_KEY) {
 426                 /*
 427                  * rt2x00lib can't determine the correct free
 428                  * key_idx for pairwise keys. We have 2 registers
 429                  * with key valid bits. The goal is simple: read
 430                  * the first register. If that is full, move to
 431                  * the next register.
 432                  * When both registers are full, we drop the key.
 433                  * Otherwise, we use the first invalid entry.
 434                  */
 435                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 436                 if (reg && reg == ~0) {
 437                         key->hw_key_idx = 32;
 438                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 439                         if (reg && reg == ~0)
 440                                 return -ENOSPC;
 441                 }
 442
 443                 key->hw_key_idx += reg ? ffz(reg) : 0;
 444
 445                 /*
 446                  * Upload key to hardware
 447                  */
 448                 memcpy(key_entry.key, crypto->key,
 449                        sizeof(key_entry.key));
 450                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 451                        sizeof(key_entry.tx_mic));
 452                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 453                        sizeof(key_entry.rx_mic));
 454
 455                 memset(&addr_entry, 0, sizeof(addr_entry));
 456                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 457                 addr_entry.cipher = crypto->cipher;
 458
 459                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 460                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 461                                               &key_entry, sizeof(key_entry));
 462
 463                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 464                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 465                                               &addr_entry, sizeof(addr_entry));
 466
 467                 /*
 468                  * Enable pairwise lookup table for given BSS idx.
 469                  * Without this, received frames will not be decrypted
 470                  * by the hardware.
 471                  */
 472                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 473                 reg |= (1 << crypto->bssidx);
 474                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 475
 476                 /*
 477                  * The driver does not support the IV/EIV generation
 478                  * in hardware. However it doesn't support the IV/EIV
 479                  * inside the ieee80211 frame either, but requires it
 480                  * to be provided separately for the descriptor.
 481                  * rt2x00lib will cut the IV/EIV data out of all frames
 482                  * given to us by mac80211, but we must tell mac80211
 483                  * to generate the IV/EIV data.
 484                  */
 485                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 486         }
 487
 488         /*
 489          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 490          * a particular key is valid. Because using the FIELD32()
 491          * defines directly will cause a lot of overhead, we use
 492          * a calculation to determine the correct bit directly.
 493          */
 494         if (key->hw_key_idx < 32) {
 495                 mask = 1 << key->hw_key_idx;
 496
 497                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 498                 if (crypto->cmd == SET_KEY)
 499                         reg |= mask;
 500                 else if (crypto->cmd == DISABLE_KEY)
 501                         reg &= ~mask;
 502                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 503         } else {
 504                 mask = 1 << (key->hw_key_idx - 32);
 505
 506                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 507                 if (crypto->cmd == SET_KEY)
 508                         reg |= mask;
 509                 else if (crypto->cmd == DISABLE_KEY)
 510                         reg &= ~mask;
 511                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 512         }
 513
 514         return 0;
 515 }
 516
 517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 518                                   const unsigned int filter_flags)
 519 {
 520         u32 reg;
 521
 522         /*
 523          * Start configuration steps.
 524          * Note that the version error will always be dropped
 525          * and broadcast frames will always be accepted since
 526          * there is no filter for it at this time.
 527          */
 528         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 529         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 530                            !(filter_flags & FIF_FCSFAIL));
 531         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 532                            !(filter_flags & FIF_PLCPFAIL));
 533         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 534                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 536                            !(filter_flags & FIF_PROMISC_IN_BSS));
 537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 538                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 539                            !rt2x00dev->intf_ap_count);
 540         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 542                            !(filter_flags & FIF_ALLMULTI));
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 544         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 547 }
 548
 549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 550                                 struct rt2x00_intf *intf,
 551                                 struct rt2x00intf_conf *conf,
 552                                 const unsigned int flags)
 553 {
 554         unsigned int beacon_base;
 555         u32 reg;
 556
 557         if (flags & CONFIG_UPDATE_TYPE) {
 558                 /*
 559                  * Clear current synchronisation setup.
 560                  * For the Beacon base registers, we only need to clear
 561                  * the first byte since that byte contains the VALID and OWNER
 562                  * bits which (when set to 0) will invalidate the entire beacon.
 563                  */
 564                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 565                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 566
 567                 /*
 568                  * Enable synchronisation.
 569                  */
 570                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 571                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 572                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 573                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 574                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 575         }
 576
 577         if (flags & CONFIG_UPDATE_MAC) {
 578                 reg = le32_to_cpu(conf->mac[1]);
 579                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 580                 conf->mac[1] = cpu_to_le32(reg);
 581
 582                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 583                                               conf->mac, sizeof(conf->mac));
 584         }
 585
 586         if (flags & CONFIG_UPDATE_BSSID) {
 587                 reg = le32_to_cpu(conf->bssid[1]);
 588                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 589                 conf->bssid[1] = cpu_to_le32(reg);
 590
 591                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 592                                               conf->bssid, sizeof(conf->bssid));
 593         }
 594 }
 595
 596 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 597                                struct rt2x00lib_erp *erp,
 598                                u32 changed)
 599 {
 600         u32 reg;
 601
 602         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 603         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 604         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 605         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 606
 607         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 608                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 609                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 610                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 611                                    !!erp->short_preamble);
 612                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 613         }
 614
 615         if (changed & BSS_CHANGED_BASIC_RATES)
 616                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
 617                                          erp->basic_rates);
 618
 619         if (changed & BSS_CHANGED_BEACON_INT) {
 620                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 621                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 622                                    erp->beacon_int * 16);
 623                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 624         }
 625
 626         if (changed & BSS_CHANGED_ERP_SLOT) {
 627                 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 628                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 629                 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 630
 631                 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 632                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 633                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 634                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 635                 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 636         }
 637 }
 638
 639 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 640                                       struct antenna_setup *ant)
 641 {
 642         u8 r3;
 643         u8 r4;
 644         u8 r77;
 645
 646         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 647         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 648         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 649
 650         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
 651
 652         /*
 653          * Configure the RX antenna.
 654          */
 655         switch (ant->rx) {
 656         case ANTENNA_HW_DIVERSITY:
 657                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 658                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 659                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 660                 break;
 661         case ANTENNA_A:
 662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 663                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 664                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 665                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 666                 else
 667                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 668                 break;
 669         case ANTENNA_B:
 670         default:
 671                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 672                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 673                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 674                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 675                 else
 676                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 677                 break;
 678         }
 679
 680         rt61pci_bbp_write(rt2x00dev, 77, r77);
 681         rt61pci_bbp_write(rt2x00dev, 3, r3);
 682         rt61pci_bbp_write(rt2x00dev, 4, r4);
 683 }
 684
 685 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 686                                       struct antenna_setup *ant)
 687 {
 688         u8 r3;
 689         u8 r4;
 690         u8 r77;
 691
 692         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 693         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 694         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 695
 696         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
 697         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 698                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 699
 700         /*
 701          * Configure the RX antenna.
 702          */
 703         switch (ant->rx) {
 704         case ANTENNA_HW_DIVERSITY:
 705                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 706                 break;
 707         case ANTENNA_A:
 708                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 709                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 710                 break;
 711         case ANTENNA_B:
 712         default:
 713                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 714                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 715                 break;
 716         }
 717
 718         rt61pci_bbp_write(rt2x00dev, 77, r77);
 719         rt61pci_bbp_write(rt2x00dev, 3, r3);
 720         rt61pci_bbp_write(rt2x00dev, 4, r4);
 721 }
 722
 723 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 724                                            const int p1, const int p2)
 725 {
 726         u32 reg;
 727
 728         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 729
 730         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 731         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 732
 733         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 734         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 735
 736         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 737 }
 738
 739 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 740                                         struct antenna_setup *ant)
 741 {
 742         u8 r3;
 743         u8 r4;
 744         u8 r77;
 745
 746         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 747         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 748         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 749
 750         /*
 751          * Configure the RX antenna.
 752          */
 753         switch (ant->rx) {
 754         case ANTENNA_A:
 755                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 756                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 757                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 758                 break;
 759         case ANTENNA_HW_DIVERSITY:
 760                 /*
 761                  * FIXME: Antenna selection for the rf 2529 is very confusing
 762                  * in the legacy driver. Just default to antenna B until the
 763                  * legacy code can be properly translated into rt2x00 code.
 764                  */
 765         case ANTENNA_B:
 766         default:
 767                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 768                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 769                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 770                 break;
 771         }
 772
 773         rt61pci_bbp_write(rt2x00dev, 77, r77);
 774         rt61pci_bbp_write(rt2x00dev, 3, r3);
 775         rt61pci_bbp_write(rt2x00dev, 4, r4);
 776 }
 777
 778 struct antenna_sel {
 779         u8 word;
 780         /*
 781          * value[0] -> non-LNA
 782          * value[1] -> LNA
 783          */
 784         u8 value[2];
 785 };
 786
 787 static const struct antenna_sel antenna_sel_a[] = {
 788         { 96,  { 0x58, 0x78 } },
 789         { 104, { 0x38, 0x48 } },
 790         { 75,  { 0xfe, 0x80 } },
 791         { 86,  { 0xfe, 0x80 } },
 792         { 88,  { 0xfe, 0x80 } },
 793         { 35,  { 0x60, 0x60 } },
 794         { 97,  { 0x58, 0x58 } },
 795         { 98,  { 0x58, 0x58 } },
 796 };
 797
 798 static const struct antenna_sel antenna_sel_bg[] = {
 799         { 96,  { 0x48, 0x68 } },
 800         { 104, { 0x2c, 0x3c } },
 801         { 75,  { 0xfe, 0x80 } },
 802         { 86,  { 0xfe, 0x80 } },
 803         { 88,  { 0xfe, 0x80 } },
 804         { 35,  { 0x50, 0x50 } },
 805         { 97,  { 0x48, 0x48 } },
 806         { 98,  { 0x48, 0x48 } },
 807 };
 808
 809 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 810                                struct antenna_setup *ant)
 811 {
 812         const struct antenna_sel *sel;
 813         unsigned int lna;
 814         unsigned int i;
 815         u32 reg;
 816
 817         /*
 818          * We should never come here because rt2x00lib is supposed
 819          * to catch this and send us the correct antenna explicitely.
 820          */
 821         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 822                ant->tx == ANTENNA_SW_DIVERSITY);
 823
 824         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 825                 sel = antenna_sel_a;
 826                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 827         } else {
 828                 sel = antenna_sel_bg;
 829                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 830         }
 831
 832         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 833                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 834
 835         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 836
 837         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 838                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 839         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 840                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 841
 842         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 843
 844         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
 845                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 846         else if (rt2x00_rf(rt2x00dev, RF2527))
 847                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 848         else if (rt2x00_rf(rt2x00dev, RF2529)) {
 849                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 850                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 851                 else
 852                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 853         }
 854 }
 855
 856 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 857                                     struct rt2x00lib_conf *libconf)
 858 {
 859         u16 eeprom;
 860         short lna_gain = 0;
 861
 862         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 863                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 864                         lna_gain += 14;
 865
 866                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 867                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 868         } else {
 869                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 870                         lna_gain += 14;
 871
 872                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 873                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 874         }
 875
 876         rt2x00dev->lna_gain = lna_gain;
 877 }
 878
 879 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 880                                    struct rf_channel *rf, const int txpower)
 881 {
 882         u8 r3;
 883         u8 r94;
 884         u8 smart;
 885
 886         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 887         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 888
 889         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 890
 891         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 892         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 893         rt61pci_bbp_write(rt2x00dev, 3, r3);
 894
 895         r94 = 6;
 896         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 897                 r94 += txpower - MAX_TXPOWER;
 898         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 899                 r94 += txpower;
 900         rt61pci_bbp_write(rt2x00dev, 94, r94);
 901
 902         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 903         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 904         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 905         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 906
 907         udelay(200);
 908
 909         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 910         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 911         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 912         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 913
 914         udelay(200);
 915
 916         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 917         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 918         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 919         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 920
 921         msleep(1);
 922 }
 923
 924 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 925                                    const int txpower)
 926 {
 927         struct rf_channel rf;
 928
 929         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 930         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 931         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 932         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 933
 934         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 935 }
 936
 937 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 938                                     struct rt2x00lib_conf *libconf)
 939 {
 940         u32 reg;
 941
 942         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 943         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
 944         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
 945         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
 946         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 947                            libconf->conf->long_frame_max_tx_count);
 948         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 949                            libconf->conf->short_frame_max_tx_count);
 950         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 951 }
 952
 953 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 954                                 struct rt2x00lib_conf *libconf)
 955 {
 956         enum dev_state state =
 957             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 958                 STATE_SLEEP : STATE_AWAKE;
 959         u32 reg;
 960
 961         if (state == STATE_SLEEP) {
 962                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 963                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 964                                    rt2x00dev->beacon_int - 10);
 965                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 966                                    libconf->conf->listen_interval - 1);
 967                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 968
 969                 /* We must first disable autowake before it can be enabled */
 970                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 971                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 972
 973                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 974                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 975
 976                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
 977                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 978                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 979
 980                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 981         } else {
 982                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 983                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 984                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 985                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 986                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 987                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 988
 989                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
 990                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
 991                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
 992
 993                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
 994         }
 995 }
 996
 997 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 998                            struct rt2x00lib_conf *libconf,
 999                            const unsigned int flags)
1000 {
1001         /* Always recalculate LNA gain before changing configuration */
1002         rt61pci_config_lna_gain(rt2x00dev, libconf);
1003
1004         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1005                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1006                                        libconf->conf->power_level);
1007         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1008             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1009                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1010         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1011                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1012         if (flags & IEEE80211_CONF_CHANGE_PS)
1013                 rt61pci_config_ps(rt2x00dev, libconf);
1014 }
1015
1016 /*
1017  * Link tuning
1018  */
1019 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1020                                struct link_qual *qual)
1021 {
1022         u32 reg;
1023
1024         /*
1025          * Update FCS error count from register.
1026          */
1027         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1028         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1029
1030         /*
1031          * Update False CCA count from register.
1032          */
1033         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1034         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1035 }
1036
1037 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1038                                    struct link_qual *qual, u8 vgc_level)
1039 {
1040         if (qual->vgc_level != vgc_level) {
1041                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1042                 qual->vgc_level = vgc_level;
1043                 qual->vgc_level_reg = vgc_level;
1044         }
1045 }
1046
1047 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1048                                 struct link_qual *qual)
1049 {
1050         rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1051 }
1052
1053 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1054                                struct link_qual *qual, const u32 count)
1055 {
1056         u8 up_bound;
1057         u8 low_bound;
1058
1059         /*
1060          * Determine r17 bounds.
1061          */
1062         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1063                 low_bound = 0x28;
1064                 up_bound = 0x48;
1065                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1066                         low_bound += 0x10;
1067                         up_bound += 0x10;
1068                 }
1069         } else {
1070                 low_bound = 0x20;
1071                 up_bound = 0x40;
1072                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1073                         low_bound += 0x10;
1074                         up_bound += 0x10;
1075                 }
1076         }
1077
1078         /*
1079          * If we are not associated, we should go straight to the
1080          * dynamic CCA tuning.
1081          */
1082         if (!rt2x00dev->intf_associated)
1083                 goto dynamic_cca_tune;
1084
1085         /*
1086          * Special big-R17 for very short distance
1087          */
1088         if (qual->rssi >= -35) {
1089                 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1090                 return;
1091         }
1092
1093         /*
1094          * Special big-R17 for short distance
1095          */
1096         if (qual->rssi >= -58) {
1097                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1098                 return;
1099         }
1100
1101         /*
1102          * Special big-R17 for middle-short distance
1103          */
1104         if (qual->rssi >= -66) {
1105                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1106                 return;
1107         }
1108
1109         /*
1110          * Special mid-R17 for middle distance
1111          */
1112         if (qual->rssi >= -74) {
1113                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1114                 return;
1115         }
1116
1117         /*
1118          * Special case: Change up_bound based on the rssi.
1119          * Lower up_bound when rssi is weaker then -74 dBm.
1120          */
1121         up_bound -= 2 * (-74 - qual->rssi);
1122         if (low_bound > up_bound)
1123                 up_bound = low_bound;
1124
1125         if (qual->vgc_level > up_bound) {
1126                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1127                 return;
1128         }
1129
1130 dynamic_cca_tune:
1131
1132         /*
1133          * r17 does not yet exceed upper limit, continue and base
1134          * the r17 tuning on the false CCA count.
1135          */
1136         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1137                 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1138         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1139                 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1140 }
1141
1142 /*
1143  * Firmware functions
1144  */
1145 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1146 {
1147         u16 chip;
1148         char *fw_name;
1149
1150         pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1151         switch (chip) {
1152         case RT2561_PCI_ID:
1153                 fw_name = FIRMWARE_RT2561;
1154                 break;
1155         case RT2561s_PCI_ID:
1156                 fw_name = FIRMWARE_RT2561s;
1157                 break;
1158         case RT2661_PCI_ID:
1159                 fw_name = FIRMWARE_RT2661;
1160                 break;
1161         default:
1162                 fw_name = NULL;
1163                 break;
1164         }
1165
1166         return fw_name;
1167 }
1168
1169 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1170                                   const u8 *data, const size_t len)
1171 {
1172         u16 fw_crc;
1173         u16 crc;
1174
1175         /*
1176          * Only support 8kb firmware files.
1177          */
1178         if (len != 8192)
1179                 return FW_BAD_LENGTH;
1180
1181         /*
1182          * The last 2 bytes in the firmware array are the crc checksum itself.
1183          * This means that we should never pass those 2 bytes to the crc
1184          * algorithm.
1185          */
1186         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1187
1188         /*
1189          * Use the crc itu-t algorithm.
1190          */
1191         crc = crc_itu_t(0, data, len - 2);
1192         crc = crc_itu_t_byte(crc, 0);
1193         crc = crc_itu_t_byte(crc, 0);
1194
1195         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1196 }
1197
1198 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1199                                  const u8 *data, const size_t len)
1200 {
1201         int i;
1202         u32 reg;
1203
1204         /*
1205          * Wait for stable hardware.
1206          */
1207         for (i = 0; i < 100; i++) {
1208                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1209                 if (reg)
1210                         break;
1211                 msleep(1);
1212         }
1213
1214         if (!reg) {
1215                 ERROR(rt2x00dev, "Unstable hardware.\n");
1216                 return -EBUSY;
1217         }
1218
1219         /*
1220          * Prepare MCU and mailbox for firmware loading.
1221          */
1222         reg = 0;
1223         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1224         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1225         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1226         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1227         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1228
1229         /*
1230          * Write firmware to device.
1231          */
1232         reg = 0;
1233         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1234         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1235         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1236
1237         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1238                                       data, len);
1239
1240         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1241         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1242
1243         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1244         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1245
1246         for (i = 0; i < 100; i++) {
1247                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1248                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1249                         break;
1250                 msleep(1);
1251         }
1252
1253         if (i == 100) {
1254                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1255                 return -EBUSY;
1256         }
1257
1258         /*
1259          * Hardware needs another millisecond before it is ready.
1260          */
1261         msleep(1);
1262
1263         /*
1264          * Reset MAC and BBP registers.
1265          */
1266         reg = 0;
1267         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1268         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1269         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1270
1271         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1272         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1273         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1274         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1275
1276         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1277         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1278         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1279
1280         return 0;
1281 }
1282
1283 /*
1284  * Initialization functions.
1285  */
1286 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1287 {
1288         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1289         u32 word;
1290
1291         if (entry->queue->qid == QID_RX) {
1292                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1293
1294                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1295         } else {
1296                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1297
1298                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1299                         rt2x00_get_field32(word, TXD_W0_VALID));
1300         }
1301 }
1302
1303 static void rt61pci_clear_entry(struct queue_entry *entry)
1304 {
1305         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1306         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1307         u32 word;
1308
1309         if (entry->queue->qid == QID_RX) {
1310                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1311                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1312                                    skbdesc->skb_dma);
1313                 rt2x00_desc_write(entry_priv->desc, 5, word);
1314
1315                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1316                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1317                 rt2x00_desc_write(entry_priv->desc, 0, word);
1318         } else {
1319                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1320                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1321                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1322                 rt2x00_desc_write(entry_priv->desc, 0, word);
1323         }
1324 }
1325
1326 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1327 {
1328         struct queue_entry_priv_pci *entry_priv;
1329         u32 reg;
1330
1331         /*
1332          * Initialize registers.
1333          */
1334         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1335         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1336                            rt2x00dev->tx[0].limit);
1337         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1338                            rt2x00dev->tx[1].limit);
1339         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1340                            rt2x00dev->tx[2].limit);
1341         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1342                            rt2x00dev->tx[3].limit);
1343         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1344
1345         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1346         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1347                            rt2x00dev->tx[0].desc_size / 4);
1348         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1349
1350         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1351         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1352         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1353                            entry_priv->desc_dma);
1354         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1355
1356         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1357         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1358         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1359                            entry_priv->desc_dma);
1360         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1361
1362         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1363         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1364         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1365                            entry_priv->desc_dma);
1366         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1367
1368         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1369         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1370         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1371                            entry_priv->desc_dma);
1372         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1373
1374         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1375         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1376         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1377                            rt2x00dev->rx->desc_size / 4);
1378         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1379         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1380
1381         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1382         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1383         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1384                            entry_priv->desc_dma);
1385         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1386
1387         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1388         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1389         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1390         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1391         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1392         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1393
1394         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1395         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1396         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1397         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1398         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1399         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1400
1401         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1402         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1403         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1404
1405         return 0;
1406 }
1407
1408 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1409 {
1410         u32 reg;
1411
1412         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1413         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1414         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1415         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1416         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1417
1418         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1419         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1420         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1421         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1422         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1423         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1424         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1425         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1426         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1427         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1428
1429         /*
1430          * CCK TXD BBP registers
1431          */
1432         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1433         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1434         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1435         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1436         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1437         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1438         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1439         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1440         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1441         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1442
1443         /*
1444          * OFDM TXD BBP registers
1445          */
1446         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1447         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1448         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1449         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1450         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1451         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1452         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1453         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1454
1455         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1456         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1457         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1458         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1459         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1460         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1461
1462         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1463         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1464         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1465         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1466         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1467         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1468
1469         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1470         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1471         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1472         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1473         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1474         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1475         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1476         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1477
1478         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1479
1480         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1481
1482         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1483         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1484         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1485
1486         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1487
1488         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1489                 return -EBUSY;
1490
1491         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1492
1493         /*
1494          * Invalidate all Shared Keys (SEC_CSR0),
1495          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1496          */
1497         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1498         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1499         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1500
1501         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1502         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1503         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1504         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1505
1506         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1507
1508         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1509
1510         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1511
1512         /*
1513          * Clear all beacons
1514          * For the Beacon base registers we only need to clear
1515          * the first byte since that byte contains the VALID and OWNER
1516          * bits which (when set to 0) will invalidate the entire beacon.
1517          */
1518         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1519         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1520         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1521         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1522
1523         /*
1524          * We must clear the error counters.
1525          * These registers are cleared on read,
1526          * so we may pass a useless variable to store the value.
1527          */
1528         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1529         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1530         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1531
1532         /*
1533          * Reset MAC and BBP registers.
1534          */
1535         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1536         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1537         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1538         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1539
1540         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1541         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1542         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1543         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1544
1545         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1546         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1547         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1548
1549         return 0;
1550 }
1551
1552 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1553 {
1554         unsigned int i;
1555         u8 value;
1556
1557         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1558                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1559                 if ((value != 0xff) && (value != 0x00))
1560                         return 0;
1561                 udelay(REGISTER_BUSY_DELAY);
1562         }
1563
1564         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1565         return -EACCES;
1566 }
1567
1568 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1569 {
1570         unsigned int i;
1571         u16 eeprom;
1572         u8 reg_id;
1573         u8 value;
1574
1575         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1576                 return -EACCES;
1577
1578         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1579         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1580         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1581         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1582         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1583         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1584         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1585         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1586         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1587         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1588         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1589         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1590         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1591         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1592         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1593         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1594         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1595         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1596         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1597         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1598         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1599         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1600         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1601         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1602
1603         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1604                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1605
1606                 if (eeprom != 0xffff && eeprom != 0x0000) {
1607                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1608                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1609                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1610                 }
1611         }
1612
1613         return 0;
1614 }
1615
1616 /*
1617  * Device state switch handlers.
1618  */
1619 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1620                               enum dev_state state)
1621 {
1622         u32 reg;
1623
1624         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1625         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1626                            (state == STATE_RADIO_RX_OFF) ||
1627                            (state == STATE_RADIO_RX_OFF_LINK));
1628         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1629 }
1630
1631 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1632                                enum dev_state state)
1633 {
1634         int mask = (state == STATE_RADIO_IRQ_OFF) ||
1635                    (state == STATE_RADIO_IRQ_OFF_ISR);
1636         u32 reg;
1637
1638         /*
1639          * When interrupts are being enabled, the interrupt registers
1640          * should clear the register to assure a clean state.
1641          */
1642         if (state == STATE_RADIO_IRQ_ON) {
1643                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1644                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1645
1646                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1647                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1648         }
1649
1650         /*
1651          * Only toggle the interrupts bits we are going to use.
1652          * Non-checked interrupt bits are disabled by default.
1653          */
1654         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1655         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1656         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1657         rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1658         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1659         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1660         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1661
1662         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1663         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1664         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1665         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1666         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1667         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1668         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1669         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1670         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1671         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1672         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1673 }
1674
1675 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1676 {
1677         u32 reg;
1678
1679         /*
1680          * Initialize all registers.
1681          */
1682         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1683                      rt61pci_init_registers(rt2x00dev) ||
1684                      rt61pci_init_bbp(rt2x00dev)))
1685                 return -EIO;
1686
1687         /*
1688          * Enable RX.
1689          */
1690         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1691         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1692         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1693
1694         return 0;
1695 }
1696
1697 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1698 {
1699         /*
1700          * Disable power
1701          */
1702         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1703 }
1704
1705 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1706 {
1707         u32 reg, reg2;
1708         unsigned int i;
1709         char put_to_sleep;
1710
1711         put_to_sleep = (state != STATE_AWAKE);
1712
1713         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1714         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1715         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1716         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1717
1718         /*
1719          * Device is not guaranteed to be in the requested state yet.
1720          * We must wait until the register indicates that the
1721          * device has entered the correct state.
1722          */
1723         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1724                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1725                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1726                 if (state == !put_to_sleep)
1727                         return 0;
1728                 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1729                 msleep(10);
1730         }
1731
1732         return -EBUSY;
1733 }
1734
1735 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1736                                     enum dev_state state)
1737 {
1738         int retval = 0;
1739
1740         switch (state) {
1741         case STATE_RADIO_ON:
1742                 retval = rt61pci_enable_radio(rt2x00dev);
1743                 break;
1744         case STATE_RADIO_OFF:
1745                 rt61pci_disable_radio(rt2x00dev);
1746                 break;
1747         case STATE_RADIO_RX_ON:
1748         case STATE_RADIO_RX_ON_LINK:
1749         case STATE_RADIO_RX_OFF:
1750         case STATE_RADIO_RX_OFF_LINK:
1751                 rt61pci_toggle_rx(rt2x00dev, state);
1752                 break;
1753         case STATE_RADIO_IRQ_ON:
1754         case STATE_RADIO_IRQ_ON_ISR:
1755         case STATE_RADIO_IRQ_OFF:
1756         case STATE_RADIO_IRQ_OFF_ISR:
1757                 rt61pci_toggle_irq(rt2x00dev, state);
1758                 break;
1759         case STATE_DEEP_SLEEP:
1760         case STATE_SLEEP:
1761         case STATE_STANDBY:
1762         case STATE_AWAKE:
1763                 retval = rt61pci_set_state(rt2x00dev, state);
1764                 break;
1765         default:
1766                 retval = -ENOTSUPP;
1767                 break;
1768         }
1769
1770         if (unlikely(retval))
1771                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1772                       state, retval);
1773
1774         return retval;
1775 }
1776
1777 /*
1778  * TX descriptor initialization
1779  */
1780 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1781                                   struct txentry_desc *txdesc)
1782 {
1783         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1784         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1785         __le32 *txd = entry_priv->desc;
1786         u32 word;
1787
1788         /*
1789          * Start writing the descriptor words.
1790          */
1791         rt2x00_desc_read(txd, 1, &word);
1792         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid);
1793         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1794         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1795         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1796         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1797         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1798                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1799         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1800         rt2x00_desc_write(txd, 1, word);
1801
1802         rt2x00_desc_read(txd, 2, &word);
1803         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1804         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1805         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1806         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1807         rt2x00_desc_write(txd, 2, word);
1808
1809         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1810                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1811                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1812         }
1813
1814         rt2x00_desc_read(txd, 5, &word);
1815         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1816         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1817                            skbdesc->entry->entry_idx);
1818         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1819                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1820         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1821         rt2x00_desc_write(txd, 5, word);
1822
1823         if (txdesc->qid != QID_BEACON) {
1824                 rt2x00_desc_read(txd, 6, &word);
1825                 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1826                                    skbdesc->skb_dma);
1827                 rt2x00_desc_write(txd, 6, word);
1828
1829                 rt2x00_desc_read(txd, 11, &word);
1830                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1831                                    txdesc->length);
1832                 rt2x00_desc_write(txd, 11, word);
1833         }
1834
1835         /*
1836          * Writing TXD word 0 must the last to prevent a race condition with
1837          * the device, whereby the device may take hold of the TXD before we
1838          * finished updating it.
1839          */
1840         rt2x00_desc_read(txd, 0, &word);
1841         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1842         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1843         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1844                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1845         rt2x00_set_field32(&word, TXD_W0_ACK,
1846                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1847         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1848                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1849         rt2x00_set_field32(&word, TXD_W0_OFDM,
1850                            (txdesc->rate_mode == RATE_MODE_OFDM));
1851         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1852         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1853                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1854         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1855                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1856         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1857                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1858         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1859         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1860         rt2x00_set_field32(&word, TXD_W0_BURST,
1861                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1862         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1863         rt2x00_desc_write(txd, 0, word);
1864
1865         /*
1866          * Register descriptor details in skb frame descriptor.
1867          */
1868         skbdesc->desc = txd;
1869         skbdesc->desc_len =
1870                 (txdesc->qid == QID_BEACON) ?  TXINFO_SIZE : TXD_DESC_SIZE;
1871 }
1872
1873 /*
1874  * TX data initialization
1875  */
1876 static void rt61pci_write_beacon(struct queue_entry *entry,
1877                                  struct txentry_desc *txdesc)
1878 {
1879         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1880         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1881         unsigned int beacon_base;
1882         u32 reg;
1883
1884         /*
1885          * Disable beaconing while we are reloading the beacon data,
1886          * otherwise we might be sending out invalid data.
1887          */
1888         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1889         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1890         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1891
1892         /*
1893          * Write the TX descriptor for the beacon.
1894          */
1895         rt61pci_write_tx_desc(entry, txdesc);
1896
1897         /*
1898          * Dump beacon to userspace through debugfs.
1899          */
1900         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1901
1902         /*
1903          * Write entire beacon with descriptor to register.
1904          */
1905         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1906         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1907                                       entry_priv->desc, TXINFO_SIZE);
1908         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1909                                       entry->skb->data, entry->skb->len);
1910
1911         /*
1912          * Enable beaconing again.
1913          *
1914          * For Wi-Fi faily generated beacons between participating
1915          * stations. Set TBTT phase adaptive adjustment step to 8us.
1916          */
1917         rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1918
1919         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1920         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1921         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1922         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1923
1924         /*
1925          * Clean up beacon skb.
1926          */
1927         dev_kfree_skb_any(entry->skb);
1928         entry->skb = NULL;
1929 }
1930
1931 static void rt61pci_kick_tx_queue(struct data_queue *queue)
1932 {
1933         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1934         u32 reg;
1935
1936         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1937         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE));
1938         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK));
1939         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI));
1940         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO));
1941         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1942 }
1943
1944 static void rt61pci_kill_tx_queue(struct data_queue *queue)
1945 {
1946         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1947         u32 reg;
1948
1949         if (queue->qid == QID_BEACON) {
1950                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1951                 return;
1952         }
1953
1954         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1955         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE));
1956         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK));
1957         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI));
1958         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO));
1959         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1960 }
1961
1962 /*
1963  * RX control handlers
1964  */
1965 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1966 {
1967         u8 offset = rt2x00dev->lna_gain;
1968         u8 lna;
1969
1970         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1971         switch (lna) {
1972         case 3:
1973                 offset += 90;
1974                 break;
1975         case 2:
1976                 offset += 74;
1977                 break;
1978         case 1:
1979                 offset += 64;
1980                 break;
1981         default:
1982                 return 0;
1983         }
1984
1985         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1986                 if (lna == 3 || lna == 2)
1987                         offset += 10;
1988         }
1989
1990         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1991 }
1992
1993 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1994                                 struct rxdone_entry_desc *rxdesc)
1995 {
1996         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1997         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1998         u32 word0;
1999         u32 word1;
2000
2001         rt2x00_desc_read(entry_priv->desc, 0, &word0);
2002         rt2x00_desc_read(entry_priv->desc, 1, &word1);
2003
2004         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
2005                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2006
2007         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2008         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2009
2010         if (rxdesc->cipher != CIPHER_NONE) {
2011                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2012                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2013                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2014
2015                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2016                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2017
2018                 /*
2019                  * Hardware has stripped IV/EIV data from 802.11 frame during
2020                  * decryption. It has provided the data separately but rt2x00lib
2021                  * should decide if it should be reinserted.
2022                  */
2023                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2024
2025                 /*
2026                  * FIXME: Legacy driver indicates that the frame does
2027                  * contain the Michael Mic. Unfortunately, in rt2x00
2028                  * the MIC seems to be missing completely...
2029                  */
2030                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2031
2032                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2033                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2034                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2035                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2036         }
2037
2038         /*
2039          * Obtain the status about this packet.
2040          * When frame was received with an OFDM bitrate,
2041          * the signal is the PLCP value. If it was received with
2042          * a CCK bitrate the signal is the rate in 100kbit/s.
2043          */
2044         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2045         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2046         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2047
2048         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2049                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2050         else
2051                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2052         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2053                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2054 }
2055
2056 /*
2057  * Interrupt functions.
2058  */
2059 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2060 {
2061         struct data_queue *queue;
2062         struct queue_entry *entry;
2063         struct queue_entry *entry_done;
2064         struct queue_entry_priv_pci *entry_priv;
2065         struct txdone_entry_desc txdesc;
2066         u32 word;
2067         u32 reg;
2068         int type;
2069         int index;
2070         int i;
2071
2072         /*
2073          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2074          * at most X times and also stop processing once the TX_STA_FIFO_VALID
2075          * flag is not set anymore.
2076          *
2077          * The legacy drivers use X=TX_RING_SIZE but state in a comment
2078          * that the TX_STA_FIFO stack has a size of 16. We stick to our
2079          * tx ring size for now.
2080          */
2081         for (i = 0; i < TX_ENTRIES; i++) {
2082                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2083                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2084                         break;
2085
2086                 /*
2087                  * Skip this entry when it contains an invalid
2088                  * queue identication number.
2089                  */
2090                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2091                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2092                 if (unlikely(!queue))
2093                         continue;
2094
2095                 /*
2096                  * Skip this entry when it contains an invalid
2097                  * index number.
2098                  */
2099                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2100                 if (unlikely(index >= queue->limit))
2101                         continue;
2102
2103                 entry = &queue->entries[index];
2104                 entry_priv = entry->priv_data;
2105                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2106
2107                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2108                     !rt2x00_get_field32(word, TXD_W0_VALID))
2109                         return;
2110
2111                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2112                 while (entry != entry_done) {
2113                         /* Catch up.
2114                          * Just report any entries we missed as failed.
2115                          */
2116                         WARNING(rt2x00dev,
2117                                 "TX status report missed for entry %d\n",
2118                                 entry_done->entry_idx);
2119
2120                         rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2121                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2122                 }
2123
2124                 /*
2125                  * Obtain the status about this packet.
2126                  */
2127                 txdesc.flags = 0;
2128                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2129                 case 0: /* Success, maybe with retry */
2130                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2131                         break;
2132                 case 6: /* Failure, excessive retries */
2133                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2134                         /* Don't break, this is a failed frame! */
2135                 default: /* Failure */
2136                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2137                 }
2138                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2139
2140                 /*
2141                  * the frame was retried at least once
2142                  * -> hw used fallback rates
2143                  */
2144                 if (txdesc.retry)
2145                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2146
2147                 rt2x00lib_txdone(entry, &txdesc);
2148         }
2149 }
2150
2151 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2152 {
2153         struct ieee80211_conf conf = { .flags = 0 };
2154         struct rt2x00lib_conf libconf = { .conf = &conf };
2155
2156         rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2157 }
2158
2159 static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance)
2160 {
2161         struct rt2x00_dev *rt2x00dev = dev_instance;
2162         u32 reg = rt2x00dev->irqvalue[0];
2163         u32 reg_mcu = rt2x00dev->irqvalue[1];
2164
2165         /*
2166          * Handle interrupts, walk through all bits
2167          * and run the tasks, the bits are checked in order of
2168          * priority.
2169          */
2170
2171         /*
2172          * 1 - Rx ring done interrupt.
2173          */
2174         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2175                 rt2x00pci_rxdone(rt2x00dev);
2176
2177         /*
2178          * 2 - Tx ring done interrupt.
2179          */
2180         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2181                 rt61pci_txdone(rt2x00dev);
2182
2183         /*
2184          * 3 - Handle MCU command done.
2185          */
2186         if (reg_mcu)
2187                 rt2x00pci_register_write(rt2x00dev,
2188                                          M2H_CMD_DONE_CSR, 0xffffffff);
2189
2190         /*
2191          * 4 - MCU Autowakeup interrupt.
2192          */
2193         if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2194                 rt61pci_wakeup(rt2x00dev);
2195
2196         /*
2197          * 5 - Beacon done interrupt.
2198          */
2199         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2200                 rt2x00lib_beacondone(rt2x00dev);
2201
2202         /* Enable interrupts again. */
2203         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2204                                               STATE_RADIO_IRQ_ON_ISR);
2205         return IRQ_HANDLED;
2206 }
2207
2208
2209 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2210 {
2211         struct rt2x00_dev *rt2x00dev = dev_instance;
2212         u32 reg_mcu;
2213         u32 reg;
2214
2215         /*
2216          * Get the interrupt sources & saved to local variable.
2217          * Write register value back to clear pending interrupts.
2218          */
2219         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2220         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2221
2222         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2223         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2224
2225         if (!reg && !reg_mcu)
2226                 return IRQ_NONE;
2227
2228         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2229                 return IRQ_HANDLED;
2230
2231         /* Store irqvalues for use in the interrupt thread. */
2232         rt2x00dev->irqvalue[0] = reg;
2233         rt2x00dev->irqvalue[1] = reg_mcu;
2234
2235         /* Disable interrupts, will be enabled again in the interrupt thread. */
2236         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2237                                               STATE_RADIO_IRQ_OFF_ISR);
2238         return IRQ_WAKE_THREAD;
2239 }
2240
2241 /*
2242  * Device probe functions.
2243  */
2244 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2245 {
2246         struct eeprom_93cx6 eeprom;
2247         u32 reg;
2248         u16 word;
2249         u8 *mac;
2250         s8 value;
2251
2252         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2253
2254         eeprom.data = rt2x00dev;
2255         eeprom.register_read = rt61pci_eepromregister_read;
2256         eeprom.register_write = rt61pci_eepromregister_write;
2257         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2258             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2259         eeprom.reg_data_in = 0;
2260         eeprom.reg_data_out = 0;
2261         eeprom.reg_data_clock = 0;
2262         eeprom.reg_chip_select = 0;
2263
2264         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2265                                EEPROM_SIZE / sizeof(u16));
2266
2267         /*
2268          * Start validation of the data that has been read.
2269          */
2270         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2271         if (!is_valid_ether_addr(mac)) {
2272                 random_ether_addr(mac);
2273                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2274         }
2275
2276         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2277         if (word == 0xffff) {
2278                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2279                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2280                                    ANTENNA_B);
2281                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2282                                    ANTENNA_B);
2283                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2284                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2285                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2286                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2287                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2288                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2289         }
2290
2291         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2292         if (word == 0xffff) {
2293                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2294                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2295                 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2296                 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2297                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2298                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2299                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2300                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2301                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2302         }
2303
2304         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2305         if (word == 0xffff) {
2306                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2307                                    LED_MODE_DEFAULT);
2308                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2309                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2310         }
2311
2312         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2313         if (word == 0xffff) {
2314                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2315                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2316                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2317                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2318         }
2319
2320         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2321         if (word == 0xffff) {
2322                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2323                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2324                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2325                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2326         } else {
2327                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2328                 if (value < -10 || value > 10)
2329                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2330                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2331                 if (value < -10 || value > 10)
2332                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2333                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2334         }
2335
2336         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2337         if (word == 0xffff) {
2338                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2339                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2340                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2341                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2342         } else {
2343                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2344                 if (value < -10 || value > 10)
2345                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2346                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2347                 if (value < -10 || value > 10)
2348                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2349                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2350         }
2351
2352         return 0;
2353 }
2354
2355 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2356 {
2357         u32 reg;
2358         u16 value;
2359         u16 eeprom;
2360
2361         /*
2362          * Read EEPROM word for configuration.
2363          */
2364         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2365
2366         /*
2367          * Identify RF chipset.
2368          */
2369         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2370         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2371         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2372                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2373
2374         if (!rt2x00_rf(rt2x00dev, RF5225) &&
2375             !rt2x00_rf(rt2x00dev, RF5325) &&
2376             !rt2x00_rf(rt2x00dev, RF2527) &&
2377             !rt2x00_rf(rt2x00dev, RF2529)) {
2378                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2379                 return -ENODEV;
2380         }
2381
2382         /*
2383          * Determine number of antennas.
2384          */
2385         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2386                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2387
2388         /*
2389          * Identify default antenna configuration.
2390          */
2391         rt2x00dev->default_ant.tx =
2392             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2393         rt2x00dev->default_ant.rx =
2394             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2395
2396         /*
2397          * Read the Frame type.
2398          */
2399         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2400                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2401
2402         /*
2403          * Detect if this device has a hardware controlled radio.
2404          */
2405         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2406                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2407
2408         /*
2409          * Read frequency offset and RF programming sequence.
2410          */
2411         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2412         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2413                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2414
2415         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2416
2417         /*
2418          * Read external LNA informations.
2419          */
2420         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2421
2422         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2423                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2424         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2425                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2426
2427         /*
2428          * When working with a RF2529 chip without double antenna,
2429          * the antenna settings should be gathered from the NIC
2430          * eeprom word.
2431          */
2432         if (rt2x00_rf(rt2x00dev, RF2529) &&
2433             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2434                 rt2x00dev->default_ant.rx =
2435                     ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2436                 rt2x00dev->default_ant.tx =
2437                     ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2438
2439                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2440                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2441                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2442                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2443         }
2444
2445         /*
2446          * Store led settings, for correct led behaviour.
2447          * If the eeprom value is invalid,
2448          * switch to default led mode.
2449          */
2450 #ifdef CONFIG_RT2X00_LIB_LEDS
2451         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2452         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2453
2454         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2455         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2456         if (value == LED_MODE_SIGNAL_STRENGTH)
2457                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2458                                  LED_TYPE_QUALITY);
2459
2460         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2461         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2462                            rt2x00_get_field16(eeprom,
2463                                               EEPROM_LED_POLARITY_GPIO_0));
2464         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2465                            rt2x00_get_field16(eeprom,
2466                                               EEPROM_LED_POLARITY_GPIO_1));
2467         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2468                            rt2x00_get_field16(eeprom,
2469                                               EEPROM_LED_POLARITY_GPIO_2));
2470         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2471                            rt2x00_get_field16(eeprom,
2472                                               EEPROM_LED_POLARITY_GPIO_3));
2473         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2474                            rt2x00_get_field16(eeprom,
2475                                               EEPROM_LED_POLARITY_GPIO_4));
2476         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2477                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2478         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2479                            rt2x00_get_field16(eeprom,
2480                                               EEPROM_LED_POLARITY_RDY_G));
2481         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2482                            rt2x00_get_field16(eeprom,
2483                                               EEPROM_LED_POLARITY_RDY_A));
2484 #endif /* CONFIG_RT2X00_LIB_LEDS */
2485
2486         return 0;
2487 }
2488
2489 /*
2490  * RF value list for RF5225 & RF5325
2491  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2492  */
2493 static const struct rf_channel rf_vals_noseq[] = {
2494         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2495         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2496         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2497         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2498         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2499         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2500         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2501         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2502         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2503         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2504         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2505         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2506         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2507         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2508
2509         /* 802.11 UNI / HyperLan 2 */
2510         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2511         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2512         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2513         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2514         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2515         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2516         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2517         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2518
2519         /* 802.11 HyperLan 2 */
2520         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2521         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2522         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2523         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2524         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2525         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2526         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2527         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2528         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2529         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2530
2531         /* 802.11 UNII */
2532         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2533         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2534         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2535         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2536         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2537         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2538
2539         /* MMAC(Japan)J52 ch 34,38,42,46 */
2540         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2541         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2542         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2543         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2544 };
2545
2546 /*
2547  * RF value list for RF5225 & RF5325
2548  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2549  */
2550 static const struct rf_channel rf_vals_seq[] = {
2551         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2552         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2553         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2554         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2555         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2556         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2557         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2558         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2559         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2560         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2561         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2562         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2563         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2564         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2565
2566         /* 802.11 UNI / HyperLan 2 */
2567         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2568         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2569         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2570         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2571         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2572         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2573         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2574         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2575
2576         /* 802.11 HyperLan 2 */
2577         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2578         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2579         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2580         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2581         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2582         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2583         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2584         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2585         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2586         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2587
2588         /* 802.11 UNII */
2589         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2590         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2591         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2592         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2593         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2594         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2595
2596         /* MMAC(Japan)J52 ch 34,38,42,46 */
2597         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2598         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2599         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2600         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2601 };
2602
2603 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2604 {
2605         struct hw_mode_spec *spec = &rt2x00dev->spec;
2606         struct channel_info *info;
2607         char *tx_power;
2608         unsigned int i;
2609
2610         /*
2611          * Disable powersaving as default.
2612          */
2613         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2614
2615         /*
2616          * Initialize all hw fields.
2617          */
2618         rt2x00dev->hw->flags =
2619             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2620             IEEE80211_HW_SIGNAL_DBM |
2621             IEEE80211_HW_SUPPORTS_PS |
2622             IEEE80211_HW_PS_NULLFUNC_STACK;
2623
2624         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2625         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2626                                 rt2x00_eeprom_addr(rt2x00dev,
2627                                                    EEPROM_MAC_ADDR_0));
2628
2629         /*
2630          * As rt61 has a global fallback table we cannot specify
2631          * more then one tx rate per frame but since the hw will
2632          * try several rates (based on the fallback table) we should
2633          * initialize max_report_rates to the maximum number of rates
2634          * we are going to try. Otherwise mac80211 will truncate our
2635          * reported tx rates and the rc algortihm will end up with
2636          * incorrect data.
2637          */
2638         rt2x00dev->hw->max_rates = 1;
2639         rt2x00dev->hw->max_report_rates = 7;
2640         rt2x00dev->hw->max_rate_tries = 1;
2641
2642         /*
2643          * Initialize hw_mode information.
2644          */
2645         spec->supported_bands = SUPPORT_BAND_2GHZ;
2646         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2647
2648         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2649                 spec->num_channels = 14;
2650                 spec->channels = rf_vals_noseq;
2651         } else {
2652                 spec->num_channels = 14;
2653                 spec->channels = rf_vals_seq;
2654         }
2655
2656         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2657                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2658                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2659         }
2660
2661         /*
2662          * Create channel information array
2663          */
2664         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2665         if (!info)
2666                 return -ENOMEM;
2667
2668         spec->channels_info = info;
2669
2670         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2671         for (i = 0; i < 14; i++) {
2672                 info[i].max_power = MAX_TXPOWER;
2673                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2674         }
2675
2676         if (spec->num_channels > 14) {
2677                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2678                 for (i = 14; i < spec->num_channels; i++) {
2679                         info[i].max_power = MAX_TXPOWER;
2680                         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2681                 }
2682         }
2683
2684         return 0;
2685 }
2686
2687 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2688 {
2689         int retval;
2690
2691         /*
2692          * Disable power saving.
2693          */
2694         rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2695
2696         /*
2697          * Allocate eeprom data.
2698          */
2699         retval = rt61pci_validate_eeprom(rt2x00dev);
2700         if (retval)
2701                 return retval;
2702
2703         retval = rt61pci_init_eeprom(rt2x00dev);
2704         if (retval)
2705                 return retval;
2706
2707         /*
2708          * Initialize hw specifications.
2709          */
2710         retval = rt61pci_probe_hw_mode(rt2x00dev);
2711         if (retval)
2712                 return retval;
2713
2714         /*
2715          * This device has multiple filters for control frames,
2716          * but has no a separate filter for PS Poll frames.
2717          */
2718         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2719
2720         /*
2721          * This device requires firmware and DMA mapped skbs.
2722          */
2723         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2724         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2725         if (!modparam_nohwcrypt)
2726                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2727         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2728
2729         /*
2730          * Set the rssi offset.
2731          */
2732         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2733
2734         return 0;
2735 }
2736
2737 /*
2738  * IEEE80211 stack callback functions.
2739  */
2740 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2741                            const struct ieee80211_tx_queue_params *params)
2742 {
2743         struct rt2x00_dev *rt2x00dev = hw->priv;
2744         struct data_queue *queue;
2745         struct rt2x00_field32 field;
2746         int retval;
2747         u32 reg;
2748         u32 offset;
2749
2750         /*
2751          * First pass the configuration through rt2x00lib, that will
2752          * update the queue settings and validate the input. After that
2753          * we are free to update the registers based on the value
2754          * in the queue parameter.
2755          */
2756         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2757         if (retval)
2758                 return retval;
2759
2760         /*
2761          * We only need to perform additional register initialization
2762          * for WMM queues.
2763          */
2764         if (queue_idx >= 4)
2765                 return 0;
2766
2767         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2768
2769         /* Update WMM TXOP register */
2770         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2771         field.bit_offset = (queue_idx & 1) * 16;
2772         field.bit_mask = 0xffff << field.bit_offset;
2773
2774         rt2x00pci_register_read(rt2x00dev, offset, &reg);
2775         rt2x00_set_field32(&reg, field, queue->txop);
2776         rt2x00pci_register_write(rt2x00dev, offset, reg);
2777
2778         /* Update WMM registers */
2779         field.bit_offset = queue_idx * 4;
2780         field.bit_mask = 0xf << field.bit_offset;
2781
2782         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2783         rt2x00_set_field32(&reg, field, queue->aifs);
2784         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2785
2786         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2787         rt2x00_set_field32(&reg, field, queue->cw_min);
2788         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2789
2790         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2791         rt2x00_set_field32(&reg, field, queue->cw_max);
2792         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2793
2794         return 0;
2795 }
2796
2797 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2798 {
2799         struct rt2x00_dev *rt2x00dev = hw->priv;
2800         u64 tsf;
2801         u32 reg;
2802
2803         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2804         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2805         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2806         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2807
2808         return tsf;
2809 }
2810
2811 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2812         .tx                     = rt2x00mac_tx,
2813         .start                  = rt2x00mac_start,
2814         .stop                   = rt2x00mac_stop,
2815         .add_interface          = rt2x00mac_add_interface,
2816         .remove_interface       = rt2x00mac_remove_interface,
2817         .config                 = rt2x00mac_config,
2818         .configure_filter       = rt2x00mac_configure_filter,
2819         .set_key                = rt2x00mac_set_key,
2820         .sw_scan_start          = rt2x00mac_sw_scan_start,
2821         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2822         .get_stats              = rt2x00mac_get_stats,
2823         .bss_info_changed       = rt2x00mac_bss_info_changed,
2824         .conf_tx                = rt61pci_conf_tx,
2825         .get_tsf                = rt61pci_get_tsf,
2826         .rfkill_poll            = rt2x00mac_rfkill_poll,
2827 };
2828
2829 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2830         .irq_handler            = rt61pci_interrupt,
2831         .irq_handler_thread     = rt61pci_interrupt_thread,
2832         .probe_hw               = rt61pci_probe_hw,
2833         .get_firmware_name      = rt61pci_get_firmware_name,
2834         .check_firmware         = rt61pci_check_firmware,
2835         .load_firmware          = rt61pci_load_firmware,
2836         .initialize             = rt2x00pci_initialize,
2837         .uninitialize           = rt2x00pci_uninitialize,
2838         .get_entry_state        = rt61pci_get_entry_state,
2839         .clear_entry            = rt61pci_clear_entry,
2840         .set_device_state       = rt61pci_set_device_state,
2841         .rfkill_poll            = rt61pci_rfkill_poll,
2842         .link_stats             = rt61pci_link_stats,
2843         .reset_tuner            = rt61pci_reset_tuner,
2844         .link_tuner             = rt61pci_link_tuner,
2845         .write_tx_desc          = rt61pci_write_tx_desc,
2846         .write_beacon           = rt61pci_write_beacon,
2847         .kick_tx_queue          = rt61pci_kick_tx_queue,
2848         .kill_tx_queue          = rt61pci_kill_tx_queue,
2849         .fill_rxdone            = rt61pci_fill_rxdone,
2850         .config_shared_key      = rt61pci_config_shared_key,
2851         .config_pairwise_key    = rt61pci_config_pairwise_key,
2852         .config_filter          = rt61pci_config_filter,
2853         .config_intf            = rt61pci_config_intf,
2854         .config_erp             = rt61pci_config_erp,
2855         .config_ant             = rt61pci_config_ant,
2856         .config                 = rt61pci_config,
2857 };
2858
2859 static const struct data_queue_desc rt61pci_queue_rx = {
2860         .entry_num              = RX_ENTRIES,
2861         .data_size              = DATA_FRAME_SIZE,
2862         .desc_size              = RXD_DESC_SIZE,
2863         .priv_size              = sizeof(struct queue_entry_priv_pci),
2864 };
2865
2866 static const struct data_queue_desc rt61pci_queue_tx = {
2867         .entry_num              = TX_ENTRIES,
2868         .data_size              = DATA_FRAME_SIZE,
2869         .desc_size              = TXD_DESC_SIZE,
2870         .priv_size              = sizeof(struct queue_entry_priv_pci),
2871 };
2872
2873 static const struct data_queue_desc rt61pci_queue_bcn = {
2874         .entry_num              = 4 * BEACON_ENTRIES,
2875         .data_size              = 0, /* No DMA required for beacons */
2876         .desc_size              = TXINFO_SIZE,
2877         .priv_size              = sizeof(struct queue_entry_priv_pci),
2878 };
2879
2880 static const struct rt2x00_ops rt61pci_ops = {
2881         .name                   = KBUILD_MODNAME,
2882         .max_sta_intf           = 1,
2883         .max_ap_intf            = 4,
2884         .eeprom_size            = EEPROM_SIZE,
2885         .rf_size                = RF_SIZE,
2886         .tx_queues              = NUM_TX_QUEUES,
2887         .extra_tx_headroom      = 0,
2888         .rx                     = &rt61pci_queue_rx,
2889         .tx                     = &rt61pci_queue_tx,
2890         .bcn                    = &rt61pci_queue_bcn,
2891         .lib                    = &rt61pci_rt2x00_ops,
2892         .hw                     = &rt61pci_mac80211_ops,
2893 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2894         .debugfs                = &rt61pci_rt2x00debug,
2895 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2896 };
2897
2898 /*
2899  * RT61pci module information.
2900  */
2901 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2902         /* RT2561s */
2903         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2904         /* RT2561 v2 */
2905         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2906         /* RT2661 */
2907         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2908         { 0, }
2909 };
2910
2911 MODULE_AUTHOR(DRV_PROJECT);
2912 MODULE_VERSION(DRV_VERSION);
2913 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2914 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2915                         "PCI & PCMCIA chipset based cards");
2916 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2917 MODULE_FIRMWARE(FIRMWARE_RT2561);
2918 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2919 MODULE_FIRMWARE(FIRMWARE_RT2661);
2920 MODULE_LICENSE("GPL");
2921
2922 static struct pci_driver rt61pci_driver = {
2923         .name           = KBUILD_MODNAME,
2924         .id_table       = rt61pci_device_table,
2925         .probe          = rt2x00pci_probe,
2926         .remove         = __devexit_p(rt2x00pci_remove),
2927         .suspend        = rt2x00pci_suspend,
2928         .resume         = rt2x00pci_resume,
2929 };
2930
2931 static int __init rt61pci_init(void)
2932 {
2933         return pci_register_driver(&rt61pci_driver);
2934 }
2935
2936 static void __exit rt61pci_exit(void)
2937 {
2938         pci_unregister_driver(&rt61pci_driver);
2939 }
2940
2941 module_init(rt61pci_init);
2942 module_exit(rt61pci_exit);