2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
41 * Allow hardware encryption to be disabled.
43 static int modparam_nohwcrypt = 0;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 #define WAIT_FOR_RF(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62 #define WAIT_FOR_MCU(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 H2M_MAILBOX_CSR_OWNER, (__reg))
66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
67 const unsigned int word, const u8 value)
71 mutex_lock(&rt2x00dev->csr_mutex);
74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
77 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
79 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
84 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
87 mutex_unlock(&rt2x00dev->csr_mutex);
90 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
91 const unsigned int word, u8 *value)
95 mutex_lock(&rt2x00dev->csr_mutex);
98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
105 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
107 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
111 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
113 WAIT_FOR_BBP(rt2x00dev, ®);
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
118 mutex_unlock(&rt2x00dev->csr_mutex);
121 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
122 const unsigned int word, const u32 value)
129 mutex_lock(&rt2x00dev->csr_mutex);
132 * Wait until the RF becomes available, afterwards we
133 * can safely write the new data into the register.
135 if (WAIT_FOR_RF(rt2x00dev, ®)) {
137 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
138 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
139 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
140 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
142 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
143 rt2x00_rf_write(rt2x00dev, word, value);
146 mutex_unlock(&rt2x00dev->csr_mutex);
149 #ifdef CONFIG_RT2X00_LIB_LEDS
151 * This function is only called from rt61pci_led_brightness()
152 * make gcc happy by placing this function inside the
153 * same ifdef statement as the caller.
155 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
156 const u8 command, const u8 token,
157 const u8 arg0, const u8 arg1)
161 mutex_lock(&rt2x00dev->csr_mutex);
164 * Wait until the MCU becomes available, afterwards we
165 * can safely write the new data into the register.
167 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
168 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
169 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
170 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
171 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
172 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
174 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
175 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
176 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
177 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
180 mutex_unlock(&rt2x00dev->csr_mutex);
183 #endif /* CONFIG_RT2X00_LIB_LEDS */
185 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
187 struct rt2x00_dev *rt2x00dev = eeprom->data;
190 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
192 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
193 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
194 eeprom->reg_data_clock =
195 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
196 eeprom->reg_chip_select =
197 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
200 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
205 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
206 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
207 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
208 !!eeprom->reg_data_clock);
209 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
210 !!eeprom->reg_chip_select);
212 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
215 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
216 static const struct rt2x00debug rt61pci_rt2x00debug = {
217 .owner = THIS_MODULE,
219 .read = rt2x00pci_register_read,
220 .write = rt2x00pci_register_write,
221 .flags = RT2X00DEBUGFS_OFFSET,
222 .word_base = CSR_REG_BASE,
223 .word_size = sizeof(u32),
224 .word_count = CSR_REG_SIZE / sizeof(u32),
227 .read = rt2x00_eeprom_read,
228 .write = rt2x00_eeprom_write,
229 .word_base = EEPROM_BASE,
230 .word_size = sizeof(u16),
231 .word_count = EEPROM_SIZE / sizeof(u16),
234 .read = rt61pci_bbp_read,
235 .write = rt61pci_bbp_write,
236 .word_base = BBP_BASE,
237 .word_size = sizeof(u8),
238 .word_count = BBP_SIZE / sizeof(u8),
241 .read = rt2x00_rf_read,
242 .write = rt61pci_rf_write,
243 .word_base = RF_BASE,
244 .word_size = sizeof(u32),
245 .word_count = RF_SIZE / sizeof(u32),
248 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
250 #ifdef CONFIG_RT2X00_LIB_RFKILL
251 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
255 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
256 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
259 #define rt61pci_rfkill_poll NULL
260 #endif /* CONFIG_RT2X00_LIB_RFKILL */
262 #ifdef CONFIG_RT2X00_LIB_LEDS
263 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
264 enum led_brightness brightness)
266 struct rt2x00_led *led =
267 container_of(led_cdev, struct rt2x00_led, led_dev);
268 unsigned int enabled = brightness != LED_OFF;
269 unsigned int a_mode =
270 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
271 unsigned int bg_mode =
272 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
274 if (led->type == LED_TYPE_RADIO) {
275 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
276 MCU_LEDCS_RADIO_STATUS, enabled);
278 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
279 (led->rt2x00dev->led_mcu_reg & 0xff),
280 ((led->rt2x00dev->led_mcu_reg >> 8)));
281 } else if (led->type == LED_TYPE_ASSOC) {
282 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
283 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
284 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
285 MCU_LEDCS_LINK_A_STATUS, a_mode);
287 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
288 (led->rt2x00dev->led_mcu_reg & 0xff),
289 ((led->rt2x00dev->led_mcu_reg >> 8)));
290 } else if (led->type == LED_TYPE_QUALITY) {
292 * The brightness is divided into 6 levels (0 - 5),
293 * this means we need to convert the brightness
294 * argument into the matching level within that range.
296 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
297 brightness / (LED_FULL / 6), 0);
301 static int rt61pci_blink_set(struct led_classdev *led_cdev,
302 unsigned long *delay_on,
303 unsigned long *delay_off)
305 struct rt2x00_led *led =
306 container_of(led_cdev, struct rt2x00_led, led_dev);
309 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
310 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
311 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
312 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
317 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
318 struct rt2x00_led *led,
321 led->rt2x00dev = rt2x00dev;
323 led->led_dev.brightness_set = rt61pci_brightness_set;
324 led->led_dev.blink_set = rt61pci_blink_set;
325 led->flags = LED_INITIALIZED;
327 #endif /* CONFIG_RT2X00_LIB_LEDS */
330 * Configuration handlers.
332 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
333 struct rt2x00lib_crypto *crypto,
334 struct ieee80211_key_conf *key)
336 struct hw_key_entry key_entry;
337 struct rt2x00_field32 field;
341 if (crypto->cmd == SET_KEY) {
343 * rt2x00lib can't determine the correct free
344 * key_idx for shared keys. We have 1 register
345 * with key valid bits. The goal is simple, read
346 * the register, if that is full we have no slots
348 * Note that each BSS is allowed to have up to 4
349 * shared keys, so put a mask over the allowed
352 mask = (0xf << crypto->bssidx);
354 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
357 if (reg && reg == mask)
360 key->hw_key_idx += reg ? ffz(reg) : 0;
363 * Upload key to hardware
365 memcpy(key_entry.key, crypto->key,
366 sizeof(key_entry.key));
367 memcpy(key_entry.tx_mic, crypto->tx_mic,
368 sizeof(key_entry.tx_mic));
369 memcpy(key_entry.rx_mic, crypto->rx_mic,
370 sizeof(key_entry.rx_mic));
372 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
373 rt2x00pci_register_multiwrite(rt2x00dev, reg,
374 &key_entry, sizeof(key_entry));
377 * The cipher types are stored over 2 registers.
378 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
379 * bssidx 1 and 2 keys are stored in SEC_CSR5.
380 * Using the correct defines correctly will cause overhead,
381 * so just calculate the correct offset.
383 if (key->hw_key_idx < 8) {
384 field.bit_offset = (3 * key->hw_key_idx);
385 field.bit_mask = 0x7 << field.bit_offset;
387 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
388 rt2x00_set_field32(®, field, crypto->cipher);
389 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
391 field.bit_offset = (3 * (key->hw_key_idx - 8));
392 field.bit_mask = 0x7 << field.bit_offset;
394 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
395 rt2x00_set_field32(®, field, crypto->cipher);
396 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
400 * The driver does not support the IV/EIV generation
401 * in hardware. However it doesn't support the IV/EIV
402 * inside the ieee80211 frame either, but requires it
403 * to be provided seperately for the descriptor.
404 * rt2x00lib will cut the IV/EIV data out of all frames
405 * given to us by mac80211, but we must tell mac80211
406 * to generate the IV/EIV data.
408 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
412 * SEC_CSR0 contains only single-bit fields to indicate
413 * a particular key is valid. Because using the FIELD32()
414 * defines directly will cause a lot of overhead we use
415 * a calculation to determine the correct bit directly.
417 mask = 1 << key->hw_key_idx;
419 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
420 if (crypto->cmd == SET_KEY)
422 else if (crypto->cmd == DISABLE_KEY)
424 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
429 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
430 struct rt2x00lib_crypto *crypto,
431 struct ieee80211_key_conf *key)
433 struct hw_pairwise_ta_entry addr_entry;
434 struct hw_key_entry key_entry;
438 if (crypto->cmd == SET_KEY) {
440 * rt2x00lib can't determine the correct free
441 * key_idx for pairwise keys. We have 2 registers
442 * with key valid bits. The goal is simple, read
443 * the first register, if that is full move to
445 * When both registers are full, we drop the key,
446 * otherwise we use the first invalid entry.
448 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
449 if (reg && reg == ~0) {
450 key->hw_key_idx = 32;
451 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
452 if (reg && reg == ~0)
456 key->hw_key_idx += reg ? ffz(reg) : 0;
459 * Upload key to hardware
461 memcpy(key_entry.key, crypto->key,
462 sizeof(key_entry.key));
463 memcpy(key_entry.tx_mic, crypto->tx_mic,
464 sizeof(key_entry.tx_mic));
465 memcpy(key_entry.rx_mic, crypto->rx_mic,
466 sizeof(key_entry.rx_mic));
468 memset(&addr_entry, 0, sizeof(addr_entry));
469 memcpy(&addr_entry, crypto->address, ETH_ALEN);
470 addr_entry.cipher = crypto->cipher;
472 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
473 rt2x00pci_register_multiwrite(rt2x00dev, reg,
474 &key_entry, sizeof(key_entry));
476 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
477 rt2x00pci_register_multiwrite(rt2x00dev, reg,
478 &addr_entry, sizeof(addr_entry));
481 * Enable pairwise lookup table for given BSS idx,
482 * without this received frames will not be decrypted
485 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
486 reg |= (1 << crypto->bssidx);
487 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
490 * The driver does not support the IV/EIV generation
491 * in hardware. However it doesn't support the IV/EIV
492 * inside the ieee80211 frame either, but requires it
493 * to be provided seperately for the descriptor.
494 * rt2x00lib will cut the IV/EIV data out of all frames
495 * given to us by mac80211, but we must tell mac80211
496 * to generate the IV/EIV data.
498 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
502 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
503 * a particular key is valid. Because using the FIELD32()
504 * defines directly will cause a lot of overhead we use
505 * a calculation to determine the correct bit directly.
507 if (key->hw_key_idx < 32) {
508 mask = 1 << key->hw_key_idx;
510 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
511 if (crypto->cmd == SET_KEY)
513 else if (crypto->cmd == DISABLE_KEY)
515 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
517 mask = 1 << (key->hw_key_idx - 32);
519 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
520 if (crypto->cmd == SET_KEY)
522 else if (crypto->cmd == DISABLE_KEY)
524 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
530 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
531 const unsigned int filter_flags)
536 * Start configuration steps.
537 * Note that the version error will always be dropped
538 * and broadcast frames will always be accepted since
539 * there is no filter for it at this time.
541 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
542 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
543 !(filter_flags & FIF_FCSFAIL));
544 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
545 !(filter_flags & FIF_PLCPFAIL));
546 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
547 !(filter_flags & FIF_CONTROL));
548 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
549 !(filter_flags & FIF_PROMISC_IN_BSS));
550 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
551 !(filter_flags & FIF_PROMISC_IN_BSS) &&
552 !rt2x00dev->intf_ap_count);
553 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
554 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
555 !(filter_flags & FIF_ALLMULTI));
556 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
557 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
558 !(filter_flags & FIF_CONTROL));
559 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
562 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
563 struct rt2x00_intf *intf,
564 struct rt2x00intf_conf *conf,
565 const unsigned int flags)
567 unsigned int beacon_base;
570 if (flags & CONFIG_UPDATE_TYPE) {
572 * Clear current synchronisation setup.
573 * For the Beacon base registers we only need to clear
574 * the first byte since that byte contains the VALID and OWNER
575 * bits which (when set to 0) will invalidate the entire beacon.
577 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
578 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
581 * Enable synchronisation.
583 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
584 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
585 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
586 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
587 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
590 if (flags & CONFIG_UPDATE_MAC) {
591 reg = le32_to_cpu(conf->mac[1]);
592 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
593 conf->mac[1] = cpu_to_le32(reg);
595 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
596 conf->mac, sizeof(conf->mac));
599 if (flags & CONFIG_UPDATE_BSSID) {
600 reg = le32_to_cpu(conf->bssid[1]);
601 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
602 conf->bssid[1] = cpu_to_le32(reg);
604 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
605 conf->bssid, sizeof(conf->bssid));
609 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
610 struct rt2x00lib_erp *erp)
614 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
615 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
616 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
618 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
619 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
620 !!erp->short_preamble);
621 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
623 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
625 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
626 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
627 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
629 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
630 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
631 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
632 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
633 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
636 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
637 struct antenna_setup *ant)
643 rt61pci_bbp_read(rt2x00dev, 3, &r3);
644 rt61pci_bbp_read(rt2x00dev, 4, &r4);
645 rt61pci_bbp_read(rt2x00dev, 77, &r77);
647 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
648 rt2x00_rf(&rt2x00dev->chip, RF5325));
651 * Configure the RX antenna.
654 case ANTENNA_HW_DIVERSITY:
655 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
656 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
657 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
660 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
661 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
662 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
663 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
669 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
670 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
671 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
672 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
674 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
678 rt61pci_bbp_write(rt2x00dev, 77, r77);
679 rt61pci_bbp_write(rt2x00dev, 3, r3);
680 rt61pci_bbp_write(rt2x00dev, 4, r4);
683 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
684 struct antenna_setup *ant)
690 rt61pci_bbp_read(rt2x00dev, 3, &r3);
691 rt61pci_bbp_read(rt2x00dev, 4, &r4);
692 rt61pci_bbp_read(rt2x00dev, 77, &r77);
694 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
695 rt2x00_rf(&rt2x00dev->chip, RF2529));
696 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
697 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
700 * Configure the RX antenna.
703 case ANTENNA_HW_DIVERSITY:
704 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
707 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
708 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
712 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
713 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
717 rt61pci_bbp_write(rt2x00dev, 77, r77);
718 rt61pci_bbp_write(rt2x00dev, 3, r3);
719 rt61pci_bbp_write(rt2x00dev, 4, r4);
722 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
723 const int p1, const int p2)
727 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
729 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
730 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
732 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
733 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
735 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
738 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
739 struct antenna_setup *ant)
745 rt61pci_bbp_read(rt2x00dev, 3, &r3);
746 rt61pci_bbp_read(rt2x00dev, 4, &r4);
747 rt61pci_bbp_read(rt2x00dev, 77, &r77);
750 * Configure the RX antenna.
754 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
755 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
756 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
758 case ANTENNA_HW_DIVERSITY:
760 * FIXME: Antenna selection for the rf 2529 is very confusing
761 * in the legacy driver. Just default to antenna B until the
762 * legacy code can be properly translated into rt2x00 code.
766 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
767 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
768 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
772 rt61pci_bbp_write(rt2x00dev, 77, r77);
773 rt61pci_bbp_write(rt2x00dev, 3, r3);
774 rt61pci_bbp_write(rt2x00dev, 4, r4);
780 * value[0] -> non-LNA
786 static const struct antenna_sel antenna_sel_a[] = {
787 { 96, { 0x58, 0x78 } },
788 { 104, { 0x38, 0x48 } },
789 { 75, { 0xfe, 0x80 } },
790 { 86, { 0xfe, 0x80 } },
791 { 88, { 0xfe, 0x80 } },
792 { 35, { 0x60, 0x60 } },
793 { 97, { 0x58, 0x58 } },
794 { 98, { 0x58, 0x58 } },
797 static const struct antenna_sel antenna_sel_bg[] = {
798 { 96, { 0x48, 0x68 } },
799 { 104, { 0x2c, 0x3c } },
800 { 75, { 0xfe, 0x80 } },
801 { 86, { 0xfe, 0x80 } },
802 { 88, { 0xfe, 0x80 } },
803 { 35, { 0x50, 0x50 } },
804 { 97, { 0x48, 0x48 } },
805 { 98, { 0x48, 0x48 } },
808 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
809 struct antenna_setup *ant)
811 const struct antenna_sel *sel;
817 * We should never come here because rt2x00lib is supposed
818 * to catch this and send us the correct antenna explicitely.
820 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
821 ant->tx == ANTENNA_SW_DIVERSITY);
823 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
825 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
827 sel = antenna_sel_bg;
828 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
831 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
832 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
834 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
836 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
837 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
838 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
839 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
841 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
843 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
844 rt2x00_rf(&rt2x00dev->chip, RF5325))
845 rt61pci_config_antenna_5x(rt2x00dev, ant);
846 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
847 rt61pci_config_antenna_2x(rt2x00dev, ant);
848 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
849 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
850 rt61pci_config_antenna_2x(rt2x00dev, ant);
852 rt61pci_config_antenna_2529(rt2x00dev, ant);
856 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
857 struct rt2x00lib_conf *libconf)
862 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
863 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
866 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
867 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
869 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
872 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
873 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
876 rt2x00dev->lna_gain = lna_gain;
879 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
880 struct rf_channel *rf, const int txpower)
886 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
887 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
889 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
890 rt2x00_rf(&rt2x00dev->chip, RF2527));
892 rt61pci_bbp_read(rt2x00dev, 3, &r3);
893 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
894 rt61pci_bbp_write(rt2x00dev, 3, r3);
897 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
898 r94 += txpower - MAX_TXPOWER;
899 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
901 rt61pci_bbp_write(rt2x00dev, 94, r94);
903 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
904 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
905 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
906 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
910 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
911 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
912 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
913 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
917 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
918 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
919 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
920 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
925 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
928 struct rf_channel rf;
930 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
931 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
932 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
933 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
935 rt61pci_config_channel(rt2x00dev, &rf, txpower);
938 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
939 struct rt2x00lib_conf *libconf)
943 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
944 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
945 libconf->conf->long_frame_max_tx_count);
946 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
947 libconf->conf->short_frame_max_tx_count);
948 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
951 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
952 struct rt2x00lib_conf *libconf)
956 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
957 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
958 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
960 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
961 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
962 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
964 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
965 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
966 libconf->conf->beacon_int * 16);
967 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
970 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
971 struct rt2x00lib_conf *libconf,
972 const unsigned int flags)
974 /* Always recalculate LNA gain before changing configuration */
975 rt61pci_config_lna_gain(rt2x00dev, libconf);
977 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
978 rt61pci_config_channel(rt2x00dev, &libconf->rf,
979 libconf->conf->power_level);
980 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
981 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
982 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
983 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
984 rt61pci_config_retry_limit(rt2x00dev, libconf);
985 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
986 rt61pci_config_duration(rt2x00dev, libconf);
992 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
993 struct link_qual *qual)
998 * Update FCS error count from register.
1000 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1001 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1004 * Update False CCA count from register.
1006 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1007 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1010 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1012 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1013 rt2x00dev->link.vgc_level = 0x20;
1016 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1018 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1023 rt61pci_bbp_read(rt2x00dev, 17, &r17);
1026 * Determine r17 bounds.
1028 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1031 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1038 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1045 * If we are not associated, we should go straight to the
1046 * dynamic CCA tuning.
1048 if (!rt2x00dev->intf_associated)
1049 goto dynamic_cca_tune;
1052 * Special big-R17 for very short distance
1056 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1061 * Special big-R17 for short distance
1064 if (r17 != up_bound)
1065 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1070 * Special big-R17 for middle-short distance
1074 if (r17 != low_bound)
1075 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1080 * Special mid-R17 for middle distance
1084 if (r17 != low_bound)
1085 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1090 * Special case: Change up_bound based on the rssi.
1091 * Lower up_bound when rssi is weaker then -74 dBm.
1093 up_bound -= 2 * (-74 - rssi);
1094 if (low_bound > up_bound)
1095 up_bound = low_bound;
1097 if (r17 > up_bound) {
1098 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1105 * r17 does not yet exceed upper limit, continue and base
1106 * the r17 tuning on the false CCA count.
1108 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1109 if (++r17 > up_bound)
1111 rt61pci_bbp_write(rt2x00dev, 17, r17);
1112 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1113 if (--r17 < low_bound)
1115 rt61pci_bbp_write(rt2x00dev, 17, r17);
1120 * Firmware functions
1122 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1126 switch (rt2x00dev->chip.rt) {
1128 fw_name = FIRMWARE_RT2561;
1131 fw_name = FIRMWARE_RT2561s;
1134 fw_name = FIRMWARE_RT2661;
1144 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1149 * Use the crc itu-t algorithm.
1150 * The last 2 bytes in the firmware array are the crc checksum itself,
1151 * this means that we should never pass those 2 bytes to the crc
1154 crc = crc_itu_t(0, data, len - 2);
1155 crc = crc_itu_t_byte(crc, 0);
1156 crc = crc_itu_t_byte(crc, 0);
1161 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1168 * Wait for stable hardware.
1170 for (i = 0; i < 100; i++) {
1171 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1178 ERROR(rt2x00dev, "Unstable hardware.\n");
1183 * Prepare MCU and mailbox for firmware loading.
1186 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1187 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1188 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1189 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1190 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1193 * Write firmware to device.
1196 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1197 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1198 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1200 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1203 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1204 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1206 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1207 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1209 for (i = 0; i < 100; i++) {
1210 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1211 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1217 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1222 * Hardware needs another millisecond before it is ready.
1227 * Reset MAC and BBP registers.
1230 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1231 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1232 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1234 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1235 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1236 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1237 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1239 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1240 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1241 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1247 * Initialization functions.
1249 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1251 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1254 if (entry->queue->qid == QID_RX) {
1255 rt2x00_desc_read(entry_priv->desc, 0, &word);
1257 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1259 rt2x00_desc_read(entry_priv->desc, 0, &word);
1261 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1262 rt2x00_get_field32(word, TXD_W0_VALID));
1266 static void rt61pci_clear_entry(struct queue_entry *entry)
1268 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1269 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1272 if (entry->queue->qid == QID_RX) {
1273 rt2x00_desc_read(entry_priv->desc, 5, &word);
1274 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1276 rt2x00_desc_write(entry_priv->desc, 5, word);
1278 rt2x00_desc_read(entry_priv->desc, 0, &word);
1279 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1280 rt2x00_desc_write(entry_priv->desc, 0, word);
1282 rt2x00_desc_read(entry_priv->desc, 0, &word);
1283 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1284 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1285 rt2x00_desc_write(entry_priv->desc, 0, word);
1289 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1291 struct queue_entry_priv_pci *entry_priv;
1295 * Initialize registers.
1297 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1298 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1299 rt2x00dev->tx[0].limit);
1300 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1301 rt2x00dev->tx[1].limit);
1302 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1303 rt2x00dev->tx[2].limit);
1304 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1305 rt2x00dev->tx[3].limit);
1306 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1308 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1309 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1310 rt2x00dev->tx[0].desc_size / 4);
1311 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1313 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1314 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1315 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1316 entry_priv->desc_dma);
1317 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1319 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1320 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1321 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1322 entry_priv->desc_dma);
1323 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1325 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1326 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1327 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1328 entry_priv->desc_dma);
1329 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1331 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1332 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1333 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1334 entry_priv->desc_dma);
1335 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1337 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1338 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1339 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1340 rt2x00dev->rx->desc_size / 4);
1341 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1342 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1344 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1345 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1346 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1347 entry_priv->desc_dma);
1348 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1350 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1351 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1352 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1353 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1354 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1355 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1357 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1358 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1359 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1360 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1361 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1362 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1364 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1365 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1366 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1371 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1375 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1376 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1377 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1378 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1379 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1381 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1382 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1383 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1384 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1385 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1386 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1387 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1388 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1389 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1390 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1393 * CCK TXD BBP registers
1395 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1396 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1397 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1398 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1399 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1400 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1401 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1402 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1403 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1404 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1407 * OFDM TXD BBP registers
1409 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1410 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1411 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1412 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1413 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1414 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1415 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1416 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1418 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1419 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1420 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1421 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1422 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1423 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1425 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1426 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1427 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1428 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1429 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1430 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1432 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1433 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
1434 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1435 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
1436 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1437 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1438 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1439 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1441 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1443 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1445 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1446 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1447 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1449 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1451 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1454 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1457 * Invalidate all Shared Keys (SEC_CSR0),
1458 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1460 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1461 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1462 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1464 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1465 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1466 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1467 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1469 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1471 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1473 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1477 * For the Beacon base registers we only need to clear
1478 * the first byte since that byte contains the VALID and OWNER
1479 * bits which (when set to 0) will invalidate the entire beacon.
1481 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1482 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1483 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1484 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1487 * We must clear the error counters.
1488 * These registers are cleared on read,
1489 * so we may pass a useless variable to store the value.
1491 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1492 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1493 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1496 * Reset MAC and BBP registers.
1498 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1499 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1500 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1501 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1503 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1504 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1505 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1506 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1508 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1509 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1510 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1515 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1520 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1521 rt61pci_bbp_read(rt2x00dev, 0, &value);
1522 if ((value != 0xff) && (value != 0x00))
1524 udelay(REGISTER_BUSY_DELAY);
1527 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1531 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1538 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1541 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1542 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1543 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1544 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1545 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1546 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1547 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1548 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1549 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1550 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1551 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1552 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1553 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1554 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1555 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1556 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1557 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1558 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1559 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1560 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1561 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1562 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1563 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1564 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1566 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1567 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1569 if (eeprom != 0xffff && eeprom != 0x0000) {
1570 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1571 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1572 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1580 * Device state switch handlers.
1582 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1583 enum dev_state state)
1587 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1588 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1589 (state == STATE_RADIO_RX_OFF) ||
1590 (state == STATE_RADIO_RX_OFF_LINK));
1591 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1594 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1595 enum dev_state state)
1597 int mask = (state == STATE_RADIO_IRQ_OFF);
1601 * When interrupts are being enabled, the interrupt registers
1602 * should clear the register to assure a clean state.
1604 if (state == STATE_RADIO_IRQ_ON) {
1605 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1606 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1608 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1609 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1613 * Only toggle the interrupts bits we are going to use.
1614 * Non-checked interrupt bits are disabled by default.
1616 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1617 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1618 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1619 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1620 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1621 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1623 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1624 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1625 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1626 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1627 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1628 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1629 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1630 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1631 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1632 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1635 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1640 * Initialize all registers.
1642 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1643 rt61pci_init_registers(rt2x00dev) ||
1644 rt61pci_init_bbp(rt2x00dev)))
1650 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1651 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1652 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1657 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1661 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1664 * Disable synchronisation.
1666 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1671 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1672 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1673 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1674 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1675 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1676 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1679 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1685 put_to_sleep = (state != STATE_AWAKE);
1687 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1688 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1689 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1690 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1693 * Device is not guaranteed to be in the requested state yet.
1694 * We must wait until the register indicates that the
1695 * device has entered the correct state.
1697 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1698 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1699 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1700 if (state == !put_to_sleep)
1708 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1709 enum dev_state state)
1714 case STATE_RADIO_ON:
1715 retval = rt61pci_enable_radio(rt2x00dev);
1717 case STATE_RADIO_OFF:
1718 rt61pci_disable_radio(rt2x00dev);
1720 case STATE_RADIO_RX_ON:
1721 case STATE_RADIO_RX_ON_LINK:
1722 case STATE_RADIO_RX_OFF:
1723 case STATE_RADIO_RX_OFF_LINK:
1724 rt61pci_toggle_rx(rt2x00dev, state);
1726 case STATE_RADIO_IRQ_ON:
1727 case STATE_RADIO_IRQ_OFF:
1728 rt61pci_toggle_irq(rt2x00dev, state);
1730 case STATE_DEEP_SLEEP:
1734 retval = rt61pci_set_state(rt2x00dev, state);
1741 if (unlikely(retval))
1742 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1749 * TX descriptor initialization
1751 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1752 struct sk_buff *skb,
1753 struct txentry_desc *txdesc)
1755 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1756 __le32 *txd = skbdesc->desc;
1760 * Start writing the descriptor words.
1762 rt2x00_desc_read(txd, 1, &word);
1763 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1764 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1765 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1766 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1767 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1768 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1769 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1770 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1771 rt2x00_desc_write(txd, 1, word);
1773 rt2x00_desc_read(txd, 2, &word);
1774 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1775 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1776 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1777 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1778 rt2x00_desc_write(txd, 2, word);
1780 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1781 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1782 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1785 rt2x00_desc_read(txd, 5, &word);
1786 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1787 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1788 skbdesc->entry->entry_idx);
1789 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1790 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1791 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1792 rt2x00_desc_write(txd, 5, word);
1794 rt2x00_desc_read(txd, 6, &word);
1795 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1797 rt2x00_desc_write(txd, 6, word);
1799 if (skbdesc->desc_len > TXINFO_SIZE) {
1800 rt2x00_desc_read(txd, 11, &word);
1801 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1802 rt2x00_desc_write(txd, 11, word);
1805 rt2x00_desc_read(txd, 0, &word);
1806 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1807 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1808 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1809 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1810 rt2x00_set_field32(&word, TXD_W0_ACK,
1811 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1812 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1813 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1814 rt2x00_set_field32(&word, TXD_W0_OFDM,
1815 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1816 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1817 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1818 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1819 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1820 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1821 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1822 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1823 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1824 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1825 rt2x00_set_field32(&word, TXD_W0_BURST,
1826 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1827 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1828 rt2x00_desc_write(txd, 0, word);
1832 * TX data initialization
1834 static void rt61pci_write_beacon(struct queue_entry *entry)
1836 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1837 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1838 unsigned int beacon_base;
1842 * Disable beaconing while we are reloading the beacon data,
1843 * otherwise we might be sending out invalid data.
1845 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1846 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1847 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1848 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1849 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1852 * Write entire beacon with descriptor to register.
1854 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1855 rt2x00pci_register_multiwrite(rt2x00dev,
1857 skbdesc->desc, skbdesc->desc_len);
1858 rt2x00pci_register_multiwrite(rt2x00dev,
1859 beacon_base + skbdesc->desc_len,
1860 entry->skb->data, entry->skb->len);
1863 * Clean up beacon skb.
1865 dev_kfree_skb_any(entry->skb);
1869 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1870 const enum data_queue_qid queue)
1874 if (queue == QID_BEACON) {
1876 * For Wi-Fi faily generated beacons between participating
1877 * stations. Set TBTT phase adaptive adjustment step to 8us.
1879 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1881 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1882 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1883 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1884 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1885 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1886 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1891 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1892 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1893 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1894 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1895 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1896 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1900 * RX control handlers
1902 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1904 u8 offset = rt2x00dev->lna_gain;
1907 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1922 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1923 if (lna == 3 || lna == 2)
1927 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1930 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1931 struct rxdone_entry_desc *rxdesc)
1933 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1934 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1938 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1939 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1941 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1942 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1944 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1946 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1947 rxdesc->cipher_status =
1948 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1951 if (rxdesc->cipher != CIPHER_NONE) {
1952 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1953 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
1954 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1957 * Hardware has stripped IV/EIV data from 802.11 frame during
1958 * decryption. It has provided the data seperately but rt2x00lib
1959 * should decide if it should be reinserted.
1961 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1964 * FIXME: Legacy driver indicates that the frame does
1965 * contain the Michael Mic. Unfortunately, in rt2x00
1966 * the MIC seems to be missing completely...
1968 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1970 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1971 rxdesc->flags |= RX_FLAG_DECRYPTED;
1972 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1973 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1977 * Obtain the status about this packet.
1978 * When frame was received with an OFDM bitrate,
1979 * the signal is the PLCP value. If it was received with
1980 * a CCK bitrate the signal is the rate in 100kbit/s.
1982 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1983 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
1984 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1986 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1987 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1989 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1990 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1991 rxdesc->dev_flags |= RXDONE_MY_BSS;
1995 * Interrupt functions.
1997 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1999 struct data_queue *queue;
2000 struct queue_entry *entry;
2001 struct queue_entry *entry_done;
2002 struct queue_entry_priv_pci *entry_priv;
2003 struct txdone_entry_desc txdesc;
2011 * During each loop we will compare the freshly read
2012 * STA_CSR4 register value with the value read from
2013 * the previous loop. If the 2 values are equal then
2014 * we should stop processing because the chance it
2015 * quite big that the device has been unplugged and
2016 * we risk going into an endless loop.
2021 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
2022 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2030 * Skip this entry when it contains an invalid
2031 * queue identication number.
2033 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2034 queue = rt2x00queue_get_queue(rt2x00dev, type);
2035 if (unlikely(!queue))
2039 * Skip this entry when it contains an invalid
2042 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2043 if (unlikely(index >= queue->limit))
2046 entry = &queue->entries[index];
2047 entry_priv = entry->priv_data;
2048 rt2x00_desc_read(entry_priv->desc, 0, &word);
2050 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2051 !rt2x00_get_field32(word, TXD_W0_VALID))
2054 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2055 while (entry != entry_done) {
2057 * Just report any entries we missed as failed.
2060 "TX status report missed for entry %d\n",
2061 entry_done->entry_idx);
2064 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2067 rt2x00lib_txdone(entry_done, &txdesc);
2068 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2072 * Obtain the status about this packet.
2075 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2076 case 0: /* Success, maybe with retry */
2077 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2079 case 6: /* Failure, excessive retries */
2080 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2081 /* Don't break, this is a failed frame! */
2082 default: /* Failure */
2083 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2085 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2087 rt2x00lib_txdone(entry, &txdesc);
2091 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2093 struct rt2x00_dev *rt2x00dev = dev_instance;
2098 * Get the interrupt sources & saved to local variable.
2099 * Write register value back to clear pending interrupts.
2101 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
2102 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2104 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
2105 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2107 if (!reg && !reg_mcu)
2110 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2114 * Handle interrupts, walk through all bits
2115 * and run the tasks, the bits are checked in order of
2120 * 1 - Rx ring done interrupt.
2122 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2123 rt2x00pci_rxdone(rt2x00dev);
2126 * 2 - Tx ring done interrupt.
2128 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2129 rt61pci_txdone(rt2x00dev);
2132 * 3 - Handle MCU command done.
2135 rt2x00pci_register_write(rt2x00dev,
2136 M2H_CMD_DONE_CSR, 0xffffffff);
2142 * Device probe functions.
2144 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2146 struct eeprom_93cx6 eeprom;
2152 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
2154 eeprom.data = rt2x00dev;
2155 eeprom.register_read = rt61pci_eepromregister_read;
2156 eeprom.register_write = rt61pci_eepromregister_write;
2157 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2158 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2159 eeprom.reg_data_in = 0;
2160 eeprom.reg_data_out = 0;
2161 eeprom.reg_data_clock = 0;
2162 eeprom.reg_chip_select = 0;
2164 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2165 EEPROM_SIZE / sizeof(u16));
2168 * Start validation of the data that has been read.
2170 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2171 if (!is_valid_ether_addr(mac)) {
2172 random_ether_addr(mac);
2173 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2176 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2177 if (word == 0xffff) {
2178 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2179 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2181 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2183 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2184 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2185 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2186 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2187 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2188 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2191 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2192 if (word == 0xffff) {
2193 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2194 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2195 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2196 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2197 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2198 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2199 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2200 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2203 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2204 if (word == 0xffff) {
2205 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2207 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2208 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2211 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2212 if (word == 0xffff) {
2213 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2214 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2215 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2216 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2219 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2220 if (word == 0xffff) {
2221 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2222 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2223 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2224 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2226 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2227 if (value < -10 || value > 10)
2228 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2229 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2230 if (value < -10 || value > 10)
2231 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2232 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2235 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2236 if (word == 0xffff) {
2237 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2238 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2239 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2240 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2242 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2243 if (value < -10 || value > 10)
2244 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2245 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2246 if (value < -10 || value > 10)
2247 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2248 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2254 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2262 * Read EEPROM word for configuration.
2264 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2267 * Identify RF chipset.
2268 * To determine the RT chip we have to read the
2269 * PCI header of the device.
2271 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2272 PCI_CONFIG_HEADER_DEVICE, &device);
2273 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2274 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2275 rt2x00_set_chip(rt2x00dev, device, value, reg);
2277 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2278 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2279 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2280 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2281 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2286 * Determine number of antenna's.
2288 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2289 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2292 * Identify default antenna configuration.
2294 rt2x00dev->default_ant.tx =
2295 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2296 rt2x00dev->default_ant.rx =
2297 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2300 * Read the Frame type.
2302 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2303 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2306 * Detect if this device has an hardware controlled radio.
2308 #ifdef CONFIG_RT2X00_LIB_RFKILL
2309 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2310 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2311 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2314 * Read frequency offset and RF programming sequence.
2316 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2317 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2318 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2320 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2323 * Read external LNA informations.
2325 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2327 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2328 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2329 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2330 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2333 * When working with a RF2529 chip without double antenna
2334 * the antenna settings should be gathered from the NIC
2337 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2338 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2339 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2341 rt2x00dev->default_ant.tx = ANTENNA_B;
2342 rt2x00dev->default_ant.rx = ANTENNA_A;
2345 rt2x00dev->default_ant.tx = ANTENNA_B;
2346 rt2x00dev->default_ant.rx = ANTENNA_B;
2349 rt2x00dev->default_ant.tx = ANTENNA_A;
2350 rt2x00dev->default_ant.rx = ANTENNA_A;
2353 rt2x00dev->default_ant.tx = ANTENNA_A;
2354 rt2x00dev->default_ant.rx = ANTENNA_B;
2358 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2359 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2360 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2361 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2365 * Store led settings, for correct led behaviour.
2366 * If the eeprom value is invalid,
2367 * switch to default led mode.
2369 #ifdef CONFIG_RT2X00_LIB_LEDS
2370 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2371 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2373 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2374 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2375 if (value == LED_MODE_SIGNAL_STRENGTH)
2376 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2379 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2380 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2381 rt2x00_get_field16(eeprom,
2382 EEPROM_LED_POLARITY_GPIO_0));
2383 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2384 rt2x00_get_field16(eeprom,
2385 EEPROM_LED_POLARITY_GPIO_1));
2386 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2387 rt2x00_get_field16(eeprom,
2388 EEPROM_LED_POLARITY_GPIO_2));
2389 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2390 rt2x00_get_field16(eeprom,
2391 EEPROM_LED_POLARITY_GPIO_3));
2392 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2393 rt2x00_get_field16(eeprom,
2394 EEPROM_LED_POLARITY_GPIO_4));
2395 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2396 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2397 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2398 rt2x00_get_field16(eeprom,
2399 EEPROM_LED_POLARITY_RDY_G));
2400 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2401 rt2x00_get_field16(eeprom,
2402 EEPROM_LED_POLARITY_RDY_A));
2403 #endif /* CONFIG_RT2X00_LIB_LEDS */
2409 * RF value list for RF5225 & RF5325
2410 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2412 static const struct rf_channel rf_vals_noseq[] = {
2413 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2414 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2415 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2416 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2417 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2418 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2419 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2420 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2421 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2422 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2423 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2424 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2425 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2426 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2428 /* 802.11 UNI / HyperLan 2 */
2429 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2430 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2431 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2432 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2433 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2434 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2435 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2436 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2438 /* 802.11 HyperLan 2 */
2439 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2440 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2441 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2442 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2443 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2444 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2445 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2446 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2447 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2448 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2451 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2452 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2453 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2454 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2455 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2456 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2458 /* MMAC(Japan)J52 ch 34,38,42,46 */
2459 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2460 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2461 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2462 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2466 * RF value list for RF5225 & RF5325
2467 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2469 static const struct rf_channel rf_vals_seq[] = {
2470 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2471 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2472 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2473 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2474 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2475 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2476 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2477 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2478 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2479 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2480 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2481 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2482 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2483 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2485 /* 802.11 UNI / HyperLan 2 */
2486 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2487 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2488 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2489 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2490 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2491 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2492 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2493 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2495 /* 802.11 HyperLan 2 */
2496 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2497 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2498 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2499 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2500 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2501 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2502 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2503 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2504 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2505 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2508 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2509 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2510 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2511 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2512 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2513 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2515 /* MMAC(Japan)J52 ch 34,38,42,46 */
2516 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2517 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2518 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2519 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2522 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2524 struct hw_mode_spec *spec = &rt2x00dev->spec;
2525 struct channel_info *info;
2530 * Initialize all hw fields.
2532 rt2x00dev->hw->flags =
2533 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2534 IEEE80211_HW_SIGNAL_DBM;
2535 rt2x00dev->hw->extra_tx_headroom = 0;
2537 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2538 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2539 rt2x00_eeprom_addr(rt2x00dev,
2540 EEPROM_MAC_ADDR_0));
2543 * Initialize hw_mode information.
2545 spec->supported_bands = SUPPORT_BAND_2GHZ;
2546 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2548 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2549 spec->num_channels = 14;
2550 spec->channels = rf_vals_noseq;
2552 spec->num_channels = 14;
2553 spec->channels = rf_vals_seq;
2556 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2557 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2558 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2559 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2563 * Create channel information array
2565 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2569 spec->channels_info = info;
2571 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2572 for (i = 0; i < 14; i++)
2573 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2575 if (spec->num_channels > 14) {
2576 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2577 for (i = 14; i < spec->num_channels; i++)
2578 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2584 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2589 * Allocate eeprom data.
2591 retval = rt61pci_validate_eeprom(rt2x00dev);
2595 retval = rt61pci_init_eeprom(rt2x00dev);
2600 * Initialize hw specifications.
2602 retval = rt61pci_probe_hw_mode(rt2x00dev);
2607 * This device requires firmware and DMA mapped skbs.
2609 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2610 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2611 if (!modparam_nohwcrypt)
2612 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2615 * Set the rssi offset.
2617 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2623 * IEEE80211 stack callback functions.
2625 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2626 const struct ieee80211_tx_queue_params *params)
2628 struct rt2x00_dev *rt2x00dev = hw->priv;
2629 struct data_queue *queue;
2630 struct rt2x00_field32 field;
2635 * First pass the configuration through rt2x00lib, that will
2636 * update the queue settings and validate the input. After that
2637 * we are free to update the registers based on the value
2638 * in the queue parameter.
2640 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2644 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2646 /* Update WMM TXOP register */
2647 if (queue_idx < 2) {
2648 field.bit_offset = queue_idx * 16;
2649 field.bit_mask = 0xffff << field.bit_offset;
2651 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
2652 rt2x00_set_field32(®, field, queue->txop);
2653 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2654 } else if (queue_idx < 4) {
2655 field.bit_offset = (queue_idx - 2) * 16;
2656 field.bit_mask = 0xffff << field.bit_offset;
2658 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
2659 rt2x00_set_field32(®, field, queue->txop);
2660 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2663 /* Update WMM registers */
2664 field.bit_offset = queue_idx * 4;
2665 field.bit_mask = 0xf << field.bit_offset;
2667 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®);
2668 rt2x00_set_field32(®, field, queue->aifs);
2669 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2671 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®);
2672 rt2x00_set_field32(®, field, queue->cw_min);
2673 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2675 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®);
2676 rt2x00_set_field32(®, field, queue->cw_max);
2677 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2682 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2684 struct rt2x00_dev *rt2x00dev = hw->priv;
2688 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2689 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2690 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2691 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2696 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2698 .start = rt2x00mac_start,
2699 .stop = rt2x00mac_stop,
2700 .add_interface = rt2x00mac_add_interface,
2701 .remove_interface = rt2x00mac_remove_interface,
2702 .config = rt2x00mac_config,
2703 .config_interface = rt2x00mac_config_interface,
2704 .configure_filter = rt2x00mac_configure_filter,
2705 .set_key = rt2x00mac_set_key,
2706 .get_stats = rt2x00mac_get_stats,
2707 .bss_info_changed = rt2x00mac_bss_info_changed,
2708 .conf_tx = rt61pci_conf_tx,
2709 .get_tx_stats = rt2x00mac_get_tx_stats,
2710 .get_tsf = rt61pci_get_tsf,
2713 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2714 .irq_handler = rt61pci_interrupt,
2715 .probe_hw = rt61pci_probe_hw,
2716 .get_firmware_name = rt61pci_get_firmware_name,
2717 .get_firmware_crc = rt61pci_get_firmware_crc,
2718 .load_firmware = rt61pci_load_firmware,
2719 .initialize = rt2x00pci_initialize,
2720 .uninitialize = rt2x00pci_uninitialize,
2721 .get_entry_state = rt61pci_get_entry_state,
2722 .clear_entry = rt61pci_clear_entry,
2723 .set_device_state = rt61pci_set_device_state,
2724 .rfkill_poll = rt61pci_rfkill_poll,
2725 .link_stats = rt61pci_link_stats,
2726 .reset_tuner = rt61pci_reset_tuner,
2727 .link_tuner = rt61pci_link_tuner,
2728 .write_tx_desc = rt61pci_write_tx_desc,
2729 .write_tx_data = rt2x00pci_write_tx_data,
2730 .write_beacon = rt61pci_write_beacon,
2731 .kick_tx_queue = rt61pci_kick_tx_queue,
2732 .fill_rxdone = rt61pci_fill_rxdone,
2733 .config_shared_key = rt61pci_config_shared_key,
2734 .config_pairwise_key = rt61pci_config_pairwise_key,
2735 .config_filter = rt61pci_config_filter,
2736 .config_intf = rt61pci_config_intf,
2737 .config_erp = rt61pci_config_erp,
2738 .config_ant = rt61pci_config_ant,
2739 .config = rt61pci_config,
2742 static const struct data_queue_desc rt61pci_queue_rx = {
2743 .entry_num = RX_ENTRIES,
2744 .data_size = DATA_FRAME_SIZE,
2745 .desc_size = RXD_DESC_SIZE,
2746 .priv_size = sizeof(struct queue_entry_priv_pci),
2749 static const struct data_queue_desc rt61pci_queue_tx = {
2750 .entry_num = TX_ENTRIES,
2751 .data_size = DATA_FRAME_SIZE,
2752 .desc_size = TXD_DESC_SIZE,
2753 .priv_size = sizeof(struct queue_entry_priv_pci),
2756 static const struct data_queue_desc rt61pci_queue_bcn = {
2757 .entry_num = 4 * BEACON_ENTRIES,
2758 .data_size = 0, /* No DMA required for beacons */
2759 .desc_size = TXINFO_SIZE,
2760 .priv_size = sizeof(struct queue_entry_priv_pci),
2763 static const struct rt2x00_ops rt61pci_ops = {
2764 .name = KBUILD_MODNAME,
2767 .eeprom_size = EEPROM_SIZE,
2769 .tx_queues = NUM_TX_QUEUES,
2770 .rx = &rt61pci_queue_rx,
2771 .tx = &rt61pci_queue_tx,
2772 .bcn = &rt61pci_queue_bcn,
2773 .lib = &rt61pci_rt2x00_ops,
2774 .hw = &rt61pci_mac80211_ops,
2775 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2776 .debugfs = &rt61pci_rt2x00debug,
2777 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2781 * RT61pci module information.
2783 static struct pci_device_id rt61pci_device_table[] = {
2785 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2787 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2789 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2793 MODULE_AUTHOR(DRV_PROJECT);
2794 MODULE_VERSION(DRV_VERSION);
2795 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2796 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2797 "PCI & PCMCIA chipset based cards");
2798 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2799 MODULE_FIRMWARE(FIRMWARE_RT2561);
2800 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2801 MODULE_FIRMWARE(FIRMWARE_RT2661);
2802 MODULE_LICENSE("GPL");
2804 static struct pci_driver rt61pci_driver = {
2805 .name = KBUILD_MODNAME,
2806 .id_table = rt61pci_device_table,
2807 .probe = rt2x00pci_probe,
2808 .remove = __devexit_p(rt2x00pci_remove),
2809 .suspend = rt2x00pci_suspend,
2810 .resume = rt2x00pci_resume,
2813 static int __init rt61pci_init(void)
2815 return pci_register_driver(&rt61pci_driver);
2818 static void __exit rt61pci_exit(void)
2820 pci_unregister_driver(&rt61pci_driver);
2823 module_init(rt61pci_init);
2824 module_exit(rt61pci_exit);