2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
38 #include "rt2x00pci.h"
42 * Allow hardware encryption to be disabled.
44 static int modparam_nohwcrypt = 0;
45 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attempt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
59 #define WAIT_FOR_BBP(__dev, __reg) \
60 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65 H2M_MAILBOX_CSR_OWNER, (__reg))
67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
72 mutex_lock(&rt2x00dev->csr_mutex);
75 * Wait until the BBP becomes available, afterwards we
76 * can safely write the new data into the register.
78 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
80 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
81 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
82 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
83 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
85 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
88 mutex_unlock(&rt2x00dev->csr_mutex);
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
92 const unsigned int word, u8 *value)
96 mutex_lock(&rt2x00dev->csr_mutex);
99 * Wait until the BBP becomes available, afterwards we
100 * can safely write the read request into the register.
101 * After the data has been written, we wait until hardware
102 * returns the correct value, if at any time the register
103 * doesn't become available in time, reg will be 0xffffffff
104 * which means we return 0xff to the caller.
106 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
108 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
109 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
110 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
112 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
114 WAIT_FOR_BBP(rt2x00dev, ®);
117 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
119 mutex_unlock(&rt2x00dev->csr_mutex);
122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
123 const unsigned int word, const u32 value)
127 mutex_lock(&rt2x00dev->csr_mutex);
130 * Wait until the RF becomes available, afterwards we
131 * can safely write the new data into the register.
133 if (WAIT_FOR_RF(rt2x00dev, ®)) {
135 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
136 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
137 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
138 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
140 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141 rt2x00_rf_write(rt2x00dev, word, value);
144 mutex_unlock(&rt2x00dev->csr_mutex);
147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
148 const u8 command, const u8 token,
149 const u8 arg0, const u8 arg1)
153 mutex_lock(&rt2x00dev->csr_mutex);
156 * Wait until the MCU becomes available, afterwards we
157 * can safely write the new data into the register.
159 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
160 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
161 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
163 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
164 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
166 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
167 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
168 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
172 mutex_unlock(&rt2x00dev->csr_mutex);
176 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
178 struct rt2x00_dev *rt2x00dev = eeprom->data;
181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
183 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185 eeprom->reg_data_clock =
186 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187 eeprom->reg_chip_select =
188 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
191 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
193 struct rt2x00_dev *rt2x00dev = eeprom->data;
196 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
199 !!eeprom->reg_data_clock);
200 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
201 !!eeprom->reg_chip_select);
203 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug = {
208 .owner = THIS_MODULE,
210 .read = rt2x00pci_register_read,
211 .write = rt2x00pci_register_write,
212 .flags = RT2X00DEBUGFS_OFFSET,
213 .word_base = CSR_REG_BASE,
214 .word_size = sizeof(u32),
215 .word_count = CSR_REG_SIZE / sizeof(u32),
218 .read = rt2x00_eeprom_read,
219 .write = rt2x00_eeprom_write,
220 .word_base = EEPROM_BASE,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
225 .read = rt61pci_bbp_read,
226 .write = rt61pci_bbp_write,
227 .word_base = BBP_BASE,
228 .word_size = sizeof(u8),
229 .word_count = BBP_SIZE / sizeof(u8),
232 .read = rt2x00_rf_read,
233 .write = rt61pci_rf_write,
234 .word_base = RF_BASE,
235 .word_size = sizeof(u32),
236 .word_count = RF_SIZE / sizeof(u32),
239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
245 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
246 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
251 enum led_brightness brightness)
253 struct rt2x00_led *led =
254 container_of(led_cdev, struct rt2x00_led, led_dev);
255 unsigned int enabled = brightness != LED_OFF;
256 unsigned int a_mode =
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258 unsigned int bg_mode =
259 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
261 if (led->type == LED_TYPE_RADIO) {
262 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263 MCU_LEDCS_RADIO_STATUS, enabled);
265 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266 (led->rt2x00dev->led_mcu_reg & 0xff),
267 ((led->rt2x00dev->led_mcu_reg >> 8)));
268 } else if (led->type == LED_TYPE_ASSOC) {
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272 MCU_LEDCS_LINK_A_STATUS, a_mode);
274 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275 (led->rt2x00dev->led_mcu_reg & 0xff),
276 ((led->rt2x00dev->led_mcu_reg >> 8)));
277 } else if (led->type == LED_TYPE_QUALITY) {
279 * The brightness is divided into 6 levels (0 - 5),
280 * this means we need to convert the brightness
281 * argument into the matching level within that range.
283 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284 brightness / (LED_FULL / 6), 0);
288 static int rt61pci_blink_set(struct led_classdev *led_cdev,
289 unsigned long *delay_on,
290 unsigned long *delay_off)
292 struct rt2x00_led *led =
293 container_of(led_cdev, struct rt2x00_led, led_dev);
296 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
297 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
298 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
299 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305 struct rt2x00_led *led,
308 led->rt2x00dev = rt2x00dev;
310 led->led_dev.brightness_set = rt61pci_brightness_set;
311 led->led_dev.blink_set = rt61pci_blink_set;
312 led->flags = LED_INITIALIZED;
314 #endif /* CONFIG_RT2X00_LIB_LEDS */
317 * Configuration handlers.
319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320 struct rt2x00lib_crypto *crypto,
321 struct ieee80211_key_conf *key)
323 struct hw_key_entry key_entry;
324 struct rt2x00_field32 field;
328 if (crypto->cmd == SET_KEY) {
330 * rt2x00lib can't determine the correct free
331 * key_idx for shared keys. We have 1 register
332 * with key valid bits. The goal is simple, read
333 * the register, if that is full we have no slots
335 * Note that each BSS is allowed to have up to 4
336 * shared keys, so put a mask over the allowed
339 mask = (0xf << crypto->bssidx);
341 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
344 if (reg && reg == mask)
347 key->hw_key_idx += reg ? ffz(reg) : 0;
350 * Upload key to hardware
352 memcpy(key_entry.key, crypto->key,
353 sizeof(key_entry.key));
354 memcpy(key_entry.tx_mic, crypto->tx_mic,
355 sizeof(key_entry.tx_mic));
356 memcpy(key_entry.rx_mic, crypto->rx_mic,
357 sizeof(key_entry.rx_mic));
359 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361 &key_entry, sizeof(key_entry));
364 * The cipher types are stored over 2 registers.
365 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366 * bssidx 1 and 2 keys are stored in SEC_CSR5.
367 * Using the correct defines correctly will cause overhead,
368 * so just calculate the correct offset.
370 if (key->hw_key_idx < 8) {
371 field.bit_offset = (3 * key->hw_key_idx);
372 field.bit_mask = 0x7 << field.bit_offset;
374 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
375 rt2x00_set_field32(®, field, crypto->cipher);
376 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
378 field.bit_offset = (3 * (key->hw_key_idx - 8));
379 field.bit_mask = 0x7 << field.bit_offset;
381 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
382 rt2x00_set_field32(®, field, crypto->cipher);
383 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
387 * The driver does not support the IV/EIV generation
388 * in hardware. However it doesn't support the IV/EIV
389 * inside the ieee80211 frame either, but requires it
390 * to be provided separately for the descriptor.
391 * rt2x00lib will cut the IV/EIV data out of all frames
392 * given to us by mac80211, but we must tell mac80211
393 * to generate the IV/EIV data.
395 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
399 * SEC_CSR0 contains only single-bit fields to indicate
400 * a particular key is valid. Because using the FIELD32()
401 * defines directly will cause a lot of overhead, we use
402 * a calculation to determine the correct bit directly.
404 mask = 1 << key->hw_key_idx;
406 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
407 if (crypto->cmd == SET_KEY)
409 else if (crypto->cmd == DISABLE_KEY)
411 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417 struct rt2x00lib_crypto *crypto,
418 struct ieee80211_key_conf *key)
420 struct hw_pairwise_ta_entry addr_entry;
421 struct hw_key_entry key_entry;
425 if (crypto->cmd == SET_KEY) {
427 * rt2x00lib can't determine the correct free
428 * key_idx for pairwise keys. We have 2 registers
429 * with key valid bits. The goal is simple: read
430 * the first register. If that is full, move to
432 * When both registers are full, we drop the key.
433 * Otherwise, we use the first invalid entry.
435 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
436 if (reg && reg == ~0) {
437 key->hw_key_idx = 32;
438 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
439 if (reg && reg == ~0)
443 key->hw_key_idx += reg ? ffz(reg) : 0;
446 * Upload key to hardware
448 memcpy(key_entry.key, crypto->key,
449 sizeof(key_entry.key));
450 memcpy(key_entry.tx_mic, crypto->tx_mic,
451 sizeof(key_entry.tx_mic));
452 memcpy(key_entry.rx_mic, crypto->rx_mic,
453 sizeof(key_entry.rx_mic));
455 memset(&addr_entry, 0, sizeof(addr_entry));
456 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457 addr_entry.cipher = crypto->cipher;
459 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461 &key_entry, sizeof(key_entry));
463 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465 &addr_entry, sizeof(addr_entry));
468 * Enable pairwise lookup table for given BSS idx.
469 * Without this, received frames will not be decrypted
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
473 reg |= (1 << crypto->bssidx);
474 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
477 * The driver does not support the IV/EIV generation
478 * in hardware. However it doesn't support the IV/EIV
479 * inside the ieee80211 frame either, but requires it
480 * to be provided separately for the descriptor.
481 * rt2x00lib will cut the IV/EIV data out of all frames
482 * given to us by mac80211, but we must tell mac80211
483 * to generate the IV/EIV data.
485 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
489 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490 * a particular key is valid. Because using the FIELD32()
491 * defines directly will cause a lot of overhead, we use
492 * a calculation to determine the correct bit directly.
494 if (key->hw_key_idx < 32) {
495 mask = 1 << key->hw_key_idx;
497 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
498 if (crypto->cmd == SET_KEY)
500 else if (crypto->cmd == DISABLE_KEY)
502 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
504 mask = 1 << (key->hw_key_idx - 32);
506 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
507 if (crypto->cmd == SET_KEY)
509 else if (crypto->cmd == DISABLE_KEY)
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518 const unsigned int filter_flags)
523 * Start configuration steps.
524 * Note that the version error will always be dropped
525 * and broadcast frames will always be accepted since
526 * there is no filter for it at this time.
528 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
529 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
530 !(filter_flags & FIF_FCSFAIL));
531 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
532 !(filter_flags & FIF_PLCPFAIL));
533 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
534 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
535 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
536 !(filter_flags & FIF_PROMISC_IN_BSS));
537 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
538 !(filter_flags & FIF_PROMISC_IN_BSS) &&
539 !rt2x00dev->intf_ap_count);
540 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
542 !(filter_flags & FIF_ALLMULTI));
543 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
544 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
545 !(filter_flags & FIF_CONTROL));
546 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf,
551 struct rt2x00intf_conf *conf,
552 const unsigned int flags)
554 unsigned int beacon_base;
557 if (flags & CONFIG_UPDATE_TYPE) {
559 * Clear current synchronisation setup.
560 * For the Beacon base registers, we only need to clear
561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
568 * Enable synchronisation.
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
571 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
572 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
573 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
577 if (flags & CONFIG_UPDATE_MAC) {
578 reg = le32_to_cpu(conf->mac[1]);
579 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
580 conf->mac[1] = cpu_to_le32(reg);
582 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
583 conf->mac, sizeof(conf->mac));
586 if (flags & CONFIG_UPDATE_BSSID) {
587 reg = le32_to_cpu(conf->bssid[1]);
588 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
589 conf->bssid[1] = cpu_to_le32(reg);
591 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
592 conf->bssid, sizeof(conf->bssid));
596 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597 struct rt2x00lib_erp *erp,
602 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
603 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
604 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
605 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
607 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
609 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
610 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
611 !!erp->short_preamble);
612 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
615 if (changed & BSS_CHANGED_BASIC_RATES)
616 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
619 if (changed & BSS_CHANGED_BEACON_INT) {
620 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
621 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
622 erp->beacon_int * 16);
623 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
626 if (changed & BSS_CHANGED_ERP_SLOT) {
627 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
628 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
629 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
631 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
632 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
633 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
634 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
635 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
639 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
640 struct antenna_setup *ant)
646 rt61pci_bbp_read(rt2x00dev, 3, &r3);
647 rt61pci_bbp_read(rt2x00dev, 4, &r4);
648 rt61pci_bbp_read(rt2x00dev, 77, &r77);
650 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
653 * Configure the RX antenna.
656 case ANTENNA_HW_DIVERSITY:
657 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
658 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
659 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
662 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
663 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
664 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
667 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
671 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
672 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
673 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
674 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
676 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
680 rt61pci_bbp_write(rt2x00dev, 77, r77);
681 rt61pci_bbp_write(rt2x00dev, 3, r3);
682 rt61pci_bbp_write(rt2x00dev, 4, r4);
685 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
686 struct antenna_setup *ant)
692 rt61pci_bbp_read(rt2x00dev, 3, &r3);
693 rt61pci_bbp_read(rt2x00dev, 4, &r4);
694 rt61pci_bbp_read(rt2x00dev, 77, &r77);
696 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
697 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
698 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
701 * Configure the RX antenna.
704 case ANTENNA_HW_DIVERSITY:
705 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
708 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
709 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
713 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
714 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
718 rt61pci_bbp_write(rt2x00dev, 77, r77);
719 rt61pci_bbp_write(rt2x00dev, 3, r3);
720 rt61pci_bbp_write(rt2x00dev, 4, r4);
723 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
724 const int p1, const int p2)
728 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
730 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
731 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
733 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
734 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
736 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
739 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
740 struct antenna_setup *ant)
746 rt61pci_bbp_read(rt2x00dev, 3, &r3);
747 rt61pci_bbp_read(rt2x00dev, 4, &r4);
748 rt61pci_bbp_read(rt2x00dev, 77, &r77);
751 * Configure the RX antenna.
755 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
756 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
757 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
759 case ANTENNA_HW_DIVERSITY:
761 * FIXME: Antenna selection for the rf 2529 is very confusing
762 * in the legacy driver. Just default to antenna B until the
763 * legacy code can be properly translated into rt2x00 code.
767 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
768 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
769 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
773 rt61pci_bbp_write(rt2x00dev, 77, r77);
774 rt61pci_bbp_write(rt2x00dev, 3, r3);
775 rt61pci_bbp_write(rt2x00dev, 4, r4);
781 * value[0] -> non-LNA
787 static const struct antenna_sel antenna_sel_a[] = {
788 { 96, { 0x58, 0x78 } },
789 { 104, { 0x38, 0x48 } },
790 { 75, { 0xfe, 0x80 } },
791 { 86, { 0xfe, 0x80 } },
792 { 88, { 0xfe, 0x80 } },
793 { 35, { 0x60, 0x60 } },
794 { 97, { 0x58, 0x58 } },
795 { 98, { 0x58, 0x58 } },
798 static const struct antenna_sel antenna_sel_bg[] = {
799 { 96, { 0x48, 0x68 } },
800 { 104, { 0x2c, 0x3c } },
801 { 75, { 0xfe, 0x80 } },
802 { 86, { 0xfe, 0x80 } },
803 { 88, { 0xfe, 0x80 } },
804 { 35, { 0x50, 0x50 } },
805 { 97, { 0x48, 0x48 } },
806 { 98, { 0x48, 0x48 } },
809 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
810 struct antenna_setup *ant)
812 const struct antenna_sel *sel;
818 * We should never come here because rt2x00lib is supposed
819 * to catch this and send us the correct antenna explicitely.
821 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
822 ant->tx == ANTENNA_SW_DIVERSITY);
824 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
826 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
828 sel = antenna_sel_bg;
829 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
832 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
833 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
835 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
837 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
838 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
839 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
840 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
842 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
844 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
845 rt61pci_config_antenna_5x(rt2x00dev, ant);
846 else if (rt2x00_rf(rt2x00dev, RF2527))
847 rt61pci_config_antenna_2x(rt2x00dev, ant);
848 else if (rt2x00_rf(rt2x00dev, RF2529)) {
849 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
850 rt61pci_config_antenna_2x(rt2x00dev, ant);
852 rt61pci_config_antenna_2529(rt2x00dev, ant);
856 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
857 struct rt2x00lib_conf *libconf)
862 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
863 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
866 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
867 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
869 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
872 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
873 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
876 rt2x00dev->lna_gain = lna_gain;
879 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
880 struct rf_channel *rf, const int txpower)
886 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
887 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
889 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
891 rt61pci_bbp_read(rt2x00dev, 3, &r3);
892 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
893 rt61pci_bbp_write(rt2x00dev, 3, r3);
896 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
897 r94 += txpower - MAX_TXPOWER;
898 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
900 rt61pci_bbp_write(rt2x00dev, 94, r94);
902 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
903 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
904 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
905 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
909 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
910 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
911 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
912 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
916 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
917 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
918 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
919 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
924 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
927 struct rf_channel rf;
929 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
930 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
931 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
932 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
934 rt61pci_config_channel(rt2x00dev, &rf, txpower);
937 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
938 struct rt2x00lib_conf *libconf)
942 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
943 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
944 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
945 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
946 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
947 libconf->conf->long_frame_max_tx_count);
948 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
949 libconf->conf->short_frame_max_tx_count);
950 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
953 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
954 struct rt2x00lib_conf *libconf)
956 enum dev_state state =
957 (libconf->conf->flags & IEEE80211_CONF_PS) ?
958 STATE_SLEEP : STATE_AWAKE;
961 if (state == STATE_SLEEP) {
962 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®);
963 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN,
964 rt2x00dev->beacon_int - 10);
965 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP,
966 libconf->conf->listen_interval - 1);
967 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5);
969 /* We must first disable autowake before it can be enabled */
970 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
971 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
973 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1);
974 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
976 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
977 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
978 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
980 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
982 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®);
983 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0);
984 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
985 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0);
986 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0);
987 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
989 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
990 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
991 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
993 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
997 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
998 struct rt2x00lib_conf *libconf,
999 const unsigned int flags)
1001 /* Always recalculate LNA gain before changing configuration */
1002 rt61pci_config_lna_gain(rt2x00dev, libconf);
1004 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1005 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1006 libconf->conf->power_level);
1007 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1008 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1009 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1010 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1011 rt61pci_config_retry_limit(rt2x00dev, libconf);
1012 if (flags & IEEE80211_CONF_CHANGE_PS)
1013 rt61pci_config_ps(rt2x00dev, libconf);
1019 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1020 struct link_qual *qual)
1025 * Update FCS error count from register.
1027 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1028 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1031 * Update False CCA count from register.
1033 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1034 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1037 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1038 struct link_qual *qual, u8 vgc_level)
1040 if (qual->vgc_level != vgc_level) {
1041 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1042 qual->vgc_level = vgc_level;
1043 qual->vgc_level_reg = vgc_level;
1047 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1048 struct link_qual *qual)
1050 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1053 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1054 struct link_qual *qual, const u32 count)
1060 * Determine r17 bounds.
1062 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1065 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1072 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1079 * If we are not associated, we should go straight to the
1080 * dynamic CCA tuning.
1082 if (!rt2x00dev->intf_associated)
1083 goto dynamic_cca_tune;
1086 * Special big-R17 for very short distance
1088 if (qual->rssi >= -35) {
1089 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1094 * Special big-R17 for short distance
1096 if (qual->rssi >= -58) {
1097 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1102 * Special big-R17 for middle-short distance
1104 if (qual->rssi >= -66) {
1105 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1110 * Special mid-R17 for middle distance
1112 if (qual->rssi >= -74) {
1113 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1118 * Special case: Change up_bound based on the rssi.
1119 * Lower up_bound when rssi is weaker then -74 dBm.
1121 up_bound -= 2 * (-74 - qual->rssi);
1122 if (low_bound > up_bound)
1123 up_bound = low_bound;
1125 if (qual->vgc_level > up_bound) {
1126 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1133 * r17 does not yet exceed upper limit, continue and base
1134 * the r17 tuning on the false CCA count.
1136 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1137 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1138 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1139 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1143 * Firmware functions
1145 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1150 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1153 fw_name = FIRMWARE_RT2561;
1155 case RT2561s_PCI_ID:
1156 fw_name = FIRMWARE_RT2561s;
1159 fw_name = FIRMWARE_RT2661;
1169 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1170 const u8 *data, const size_t len)
1176 * Only support 8kb firmware files.
1179 return FW_BAD_LENGTH;
1182 * The last 2 bytes in the firmware array are the crc checksum itself.
1183 * This means that we should never pass those 2 bytes to the crc
1186 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1189 * Use the crc itu-t algorithm.
1191 crc = crc_itu_t(0, data, len - 2);
1192 crc = crc_itu_t_byte(crc, 0);
1193 crc = crc_itu_t_byte(crc, 0);
1195 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1198 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1199 const u8 *data, const size_t len)
1205 * Wait for stable hardware.
1207 for (i = 0; i < 100; i++) {
1208 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1215 ERROR(rt2x00dev, "Unstable hardware.\n");
1220 * Prepare MCU and mailbox for firmware loading.
1223 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1224 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1225 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1226 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1227 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1230 * Write firmware to device.
1233 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1234 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1235 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1237 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1240 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1241 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1243 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1244 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1246 for (i = 0; i < 100; i++) {
1247 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1248 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1254 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1259 * Hardware needs another millisecond before it is ready.
1264 * Reset MAC and BBP registers.
1267 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1268 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1269 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1271 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1272 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1273 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1274 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1276 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1277 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1278 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1284 * Initialization functions.
1286 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1288 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1291 if (entry->queue->qid == QID_RX) {
1292 rt2x00_desc_read(entry_priv->desc, 0, &word);
1294 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1296 rt2x00_desc_read(entry_priv->desc, 0, &word);
1298 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1299 rt2x00_get_field32(word, TXD_W0_VALID));
1303 static void rt61pci_clear_entry(struct queue_entry *entry)
1305 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1306 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1309 if (entry->queue->qid == QID_RX) {
1310 rt2x00_desc_read(entry_priv->desc, 5, &word);
1311 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1313 rt2x00_desc_write(entry_priv->desc, 5, word);
1315 rt2x00_desc_read(entry_priv->desc, 0, &word);
1316 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1317 rt2x00_desc_write(entry_priv->desc, 0, word);
1319 rt2x00_desc_read(entry_priv->desc, 0, &word);
1320 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1321 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1322 rt2x00_desc_write(entry_priv->desc, 0, word);
1326 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1328 struct queue_entry_priv_pci *entry_priv;
1332 * Initialize registers.
1334 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1335 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1336 rt2x00dev->tx[0].limit);
1337 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1338 rt2x00dev->tx[1].limit);
1339 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1340 rt2x00dev->tx[2].limit);
1341 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1342 rt2x00dev->tx[3].limit);
1343 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1345 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1346 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1347 rt2x00dev->tx[0].desc_size / 4);
1348 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1350 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1351 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1352 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1353 entry_priv->desc_dma);
1354 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1356 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1357 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1358 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1359 entry_priv->desc_dma);
1360 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1362 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1363 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1364 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1365 entry_priv->desc_dma);
1366 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1368 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1369 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1370 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1371 entry_priv->desc_dma);
1372 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1374 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1375 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1376 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1377 rt2x00dev->rx->desc_size / 4);
1378 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1379 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1381 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1382 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1383 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1384 entry_priv->desc_dma);
1385 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1387 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1388 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1389 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1390 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1391 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1392 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1394 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1395 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1396 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1397 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1398 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1399 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1401 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1402 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1403 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1408 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1412 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1413 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1414 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1415 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1416 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1418 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1419 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1420 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1421 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1422 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1423 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1424 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1425 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1426 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1427 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1430 * CCK TXD BBP registers
1432 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1433 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1434 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1435 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1436 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1437 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1438 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1439 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1440 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1441 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1444 * OFDM TXD BBP registers
1446 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1447 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1448 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1449 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1450 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1451 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1452 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1453 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1455 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1456 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1457 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1458 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1459 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1460 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1462 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1463 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1464 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1465 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1466 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1467 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1469 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1470 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
1471 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1472 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
1473 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1474 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1475 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1476 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1478 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1480 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1482 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1483 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1484 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1486 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1488 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1491 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1494 * Invalidate all Shared Keys (SEC_CSR0),
1495 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1497 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1498 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1499 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1501 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1502 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1503 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1504 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1506 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1508 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1510 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1514 * For the Beacon base registers we only need to clear
1515 * the first byte since that byte contains the VALID and OWNER
1516 * bits which (when set to 0) will invalidate the entire beacon.
1518 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1519 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1520 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1521 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1524 * We must clear the error counters.
1525 * These registers are cleared on read,
1526 * so we may pass a useless variable to store the value.
1528 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1529 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1530 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1533 * Reset MAC and BBP registers.
1535 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1536 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1537 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1538 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1540 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1541 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1542 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1543 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1545 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1546 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1547 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1552 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1557 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1558 rt61pci_bbp_read(rt2x00dev, 0, &value);
1559 if ((value != 0xff) && (value != 0x00))
1561 udelay(REGISTER_BUSY_DELAY);
1564 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1568 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1575 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1578 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1579 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1580 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1581 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1582 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1583 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1584 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1585 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1586 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1587 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1588 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1589 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1590 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1591 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1592 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1593 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1594 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1595 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1596 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1597 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1598 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1599 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1600 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1601 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1603 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1604 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1606 if (eeprom != 0xffff && eeprom != 0x0000) {
1607 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1608 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1609 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1617 * Device state switch handlers.
1619 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1620 enum dev_state state)
1624 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1625 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1626 (state == STATE_RADIO_RX_OFF) ||
1627 (state == STATE_RADIO_RX_OFF_LINK));
1628 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1631 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1632 enum dev_state state)
1634 int mask = (state == STATE_RADIO_IRQ_OFF) ||
1635 (state == STATE_RADIO_IRQ_OFF_ISR);
1639 * When interrupts are being enabled, the interrupt registers
1640 * should clear the register to assure a clean state.
1642 if (state == STATE_RADIO_IRQ_ON) {
1643 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1644 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1646 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1647 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1651 * Only toggle the interrupts bits we are going to use.
1652 * Non-checked interrupt bits are disabled by default.
1654 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1655 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1656 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1657 rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask);
1658 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1659 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1660 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1662 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1663 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1664 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1665 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1666 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1667 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1668 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1669 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1670 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1671 rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask);
1672 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1675 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1680 * Initialize all registers.
1682 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1683 rt61pci_init_registers(rt2x00dev) ||
1684 rt61pci_init_bbp(rt2x00dev)))
1690 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1691 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1692 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1697 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1702 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1705 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1711 put_to_sleep = (state != STATE_AWAKE);
1713 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1714 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1715 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1716 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1719 * Device is not guaranteed to be in the requested state yet.
1720 * We must wait until the register indicates that the
1721 * device has entered the correct state.
1723 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1724 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®2);
1725 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1726 if (state == !put_to_sleep)
1728 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1735 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1736 enum dev_state state)
1741 case STATE_RADIO_ON:
1742 retval = rt61pci_enable_radio(rt2x00dev);
1744 case STATE_RADIO_OFF:
1745 rt61pci_disable_radio(rt2x00dev);
1747 case STATE_RADIO_RX_ON:
1748 case STATE_RADIO_RX_ON_LINK:
1749 case STATE_RADIO_RX_OFF:
1750 case STATE_RADIO_RX_OFF_LINK:
1751 rt61pci_toggle_rx(rt2x00dev, state);
1753 case STATE_RADIO_IRQ_ON:
1754 case STATE_RADIO_IRQ_ON_ISR:
1755 case STATE_RADIO_IRQ_OFF:
1756 case STATE_RADIO_IRQ_OFF_ISR:
1757 rt61pci_toggle_irq(rt2x00dev, state);
1759 case STATE_DEEP_SLEEP:
1763 retval = rt61pci_set_state(rt2x00dev, state);
1770 if (unlikely(retval))
1771 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1778 * TX descriptor initialization
1780 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1781 struct txentry_desc *txdesc)
1783 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1784 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1785 __le32 *txd = entry_priv->desc;
1789 * Start writing the descriptor words.
1791 rt2x00_desc_read(txd, 1, &word);
1792 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid);
1793 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1794 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1795 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1796 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1797 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1798 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1799 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1800 rt2x00_desc_write(txd, 1, word);
1802 rt2x00_desc_read(txd, 2, &word);
1803 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1804 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1805 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1806 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1807 rt2x00_desc_write(txd, 2, word);
1809 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1810 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1811 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1814 rt2x00_desc_read(txd, 5, &word);
1815 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1816 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1817 skbdesc->entry->entry_idx);
1818 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1819 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1820 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1821 rt2x00_desc_write(txd, 5, word);
1823 if (txdesc->qid != QID_BEACON) {
1824 rt2x00_desc_read(txd, 6, &word);
1825 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1827 rt2x00_desc_write(txd, 6, word);
1829 rt2x00_desc_read(txd, 11, &word);
1830 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1832 rt2x00_desc_write(txd, 11, word);
1836 * Writing TXD word 0 must the last to prevent a race condition with
1837 * the device, whereby the device may take hold of the TXD before we
1838 * finished updating it.
1840 rt2x00_desc_read(txd, 0, &word);
1841 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1842 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1843 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1844 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1845 rt2x00_set_field32(&word, TXD_W0_ACK,
1846 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1847 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1848 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1849 rt2x00_set_field32(&word, TXD_W0_OFDM,
1850 (txdesc->rate_mode == RATE_MODE_OFDM));
1851 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1852 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1853 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1854 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1855 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1856 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1857 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1858 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1859 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1860 rt2x00_set_field32(&word, TXD_W0_BURST,
1861 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1862 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1863 rt2x00_desc_write(txd, 0, word);
1866 * Register descriptor details in skb frame descriptor.
1868 skbdesc->desc = txd;
1870 (txdesc->qid == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE;
1874 * TX data initialization
1876 static void rt61pci_write_beacon(struct queue_entry *entry,
1877 struct txentry_desc *txdesc)
1879 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1880 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1881 unsigned int beacon_base;
1885 * Disable beaconing while we are reloading the beacon data,
1886 * otherwise we might be sending out invalid data.
1888 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1889 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1890 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1893 * Write the TX descriptor for the beacon.
1895 rt61pci_write_tx_desc(entry, txdesc);
1898 * Dump beacon to userspace through debugfs.
1900 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1903 * Write entire beacon with descriptor to register.
1905 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1906 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1907 entry_priv->desc, TXINFO_SIZE);
1908 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1909 entry->skb->data, entry->skb->len);
1912 * Enable beaconing again.
1914 * For Wi-Fi faily generated beacons between participating
1915 * stations. Set TBTT phase adaptive adjustment step to 8us.
1917 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1919 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1920 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1921 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1922 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1925 * Clean up beacon skb.
1927 dev_kfree_skb_any(entry->skb);
1931 static void rt61pci_kick_tx_queue(struct data_queue *queue)
1933 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1936 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1937 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE));
1938 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK));
1939 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI));
1940 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO));
1941 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1944 static void rt61pci_kill_tx_queue(struct data_queue *queue)
1946 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1949 if (queue->qid == QID_BEACON) {
1950 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1954 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1955 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE));
1956 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK));
1957 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI));
1958 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO));
1959 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1963 * RX control handlers
1965 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1967 u8 offset = rt2x00dev->lna_gain;
1970 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1985 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1986 if (lna == 3 || lna == 2)
1990 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1993 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1994 struct rxdone_entry_desc *rxdesc)
1996 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1997 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2001 rt2x00_desc_read(entry_priv->desc, 0, &word0);
2002 rt2x00_desc_read(entry_priv->desc, 1, &word1);
2004 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
2005 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2007 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2008 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2010 if (rxdesc->cipher != CIPHER_NONE) {
2011 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2012 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2013 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2015 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2016 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2019 * Hardware has stripped IV/EIV data from 802.11 frame during
2020 * decryption. It has provided the data separately but rt2x00lib
2021 * should decide if it should be reinserted.
2023 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2026 * FIXME: Legacy driver indicates that the frame does
2027 * contain the Michael Mic. Unfortunately, in rt2x00
2028 * the MIC seems to be missing completely...
2030 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2032 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2033 rxdesc->flags |= RX_FLAG_DECRYPTED;
2034 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2035 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2039 * Obtain the status about this packet.
2040 * When frame was received with an OFDM bitrate,
2041 * the signal is the PLCP value. If it was received with
2042 * a CCK bitrate the signal is the rate in 100kbit/s.
2044 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2045 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2046 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2048 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2049 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2051 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2052 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2053 rxdesc->dev_flags |= RXDONE_MY_BSS;
2057 * Interrupt functions.
2059 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2061 struct data_queue *queue;
2062 struct queue_entry *entry;
2063 struct queue_entry *entry_done;
2064 struct queue_entry_priv_pci *entry_priv;
2065 struct txdone_entry_desc txdesc;
2073 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2074 * at most X times and also stop processing once the TX_STA_FIFO_VALID
2075 * flag is not set anymore.
2077 * The legacy drivers use X=TX_RING_SIZE but state in a comment
2078 * that the TX_STA_FIFO stack has a size of 16. We stick to our
2079 * tx ring size for now.
2081 for (i = 0; i < TX_ENTRIES; i++) {
2082 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
2083 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2087 * Skip this entry when it contains an invalid
2088 * queue identication number.
2090 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2091 queue = rt2x00queue_get_queue(rt2x00dev, type);
2092 if (unlikely(!queue))
2096 * Skip this entry when it contains an invalid
2099 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2100 if (unlikely(index >= queue->limit))
2103 entry = &queue->entries[index];
2104 entry_priv = entry->priv_data;
2105 rt2x00_desc_read(entry_priv->desc, 0, &word);
2107 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2108 !rt2x00_get_field32(word, TXD_W0_VALID))
2111 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2112 while (entry != entry_done) {
2114 * Just report any entries we missed as failed.
2117 "TX status report missed for entry %d\n",
2118 entry_done->entry_idx);
2120 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
2121 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2125 * Obtain the status about this packet.
2128 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2129 case 0: /* Success, maybe with retry */
2130 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2132 case 6: /* Failure, excessive retries */
2133 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2134 /* Don't break, this is a failed frame! */
2135 default: /* Failure */
2136 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2138 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2141 * the frame was retried at least once
2142 * -> hw used fallback rates
2145 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2147 rt2x00lib_txdone(entry, &txdesc);
2151 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2153 struct ieee80211_conf conf = { .flags = 0 };
2154 struct rt2x00lib_conf libconf = { .conf = &conf };
2156 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2159 static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance)
2161 struct rt2x00_dev *rt2x00dev = dev_instance;
2162 u32 reg = rt2x00dev->irqvalue[0];
2163 u32 reg_mcu = rt2x00dev->irqvalue[1];
2166 * Handle interrupts, walk through all bits
2167 * and run the tasks, the bits are checked in order of
2172 * 1 - Rx ring done interrupt.
2174 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2175 rt2x00pci_rxdone(rt2x00dev);
2178 * 2 - Tx ring done interrupt.
2180 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2181 rt61pci_txdone(rt2x00dev);
2184 * 3 - Handle MCU command done.
2187 rt2x00pci_register_write(rt2x00dev,
2188 M2H_CMD_DONE_CSR, 0xffffffff);
2191 * 4 - MCU Autowakeup interrupt.
2193 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2194 rt61pci_wakeup(rt2x00dev);
2197 * 5 - Beacon done interrupt.
2199 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2200 rt2x00lib_beacondone(rt2x00dev);
2202 /* Enable interrupts again. */
2203 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2204 STATE_RADIO_IRQ_ON_ISR);
2209 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2211 struct rt2x00_dev *rt2x00dev = dev_instance;
2216 * Get the interrupt sources & saved to local variable.
2217 * Write register value back to clear pending interrupts.
2219 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
2220 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2222 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
2223 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2225 if (!reg && !reg_mcu)
2228 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2231 /* Store irqvalues for use in the interrupt thread. */
2232 rt2x00dev->irqvalue[0] = reg;
2233 rt2x00dev->irqvalue[1] = reg_mcu;
2235 /* Disable interrupts, will be enabled again in the interrupt thread. */
2236 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2237 STATE_RADIO_IRQ_OFF_ISR);
2238 return IRQ_WAKE_THREAD;
2242 * Device probe functions.
2244 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2246 struct eeprom_93cx6 eeprom;
2252 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
2254 eeprom.data = rt2x00dev;
2255 eeprom.register_read = rt61pci_eepromregister_read;
2256 eeprom.register_write = rt61pci_eepromregister_write;
2257 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2258 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2259 eeprom.reg_data_in = 0;
2260 eeprom.reg_data_out = 0;
2261 eeprom.reg_data_clock = 0;
2262 eeprom.reg_chip_select = 0;
2264 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2265 EEPROM_SIZE / sizeof(u16));
2268 * Start validation of the data that has been read.
2270 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2271 if (!is_valid_ether_addr(mac)) {
2272 random_ether_addr(mac);
2273 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2276 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2277 if (word == 0xffff) {
2278 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2279 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2281 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2283 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2284 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2285 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2286 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2287 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2288 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2291 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2292 if (word == 0xffff) {
2293 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2294 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2295 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2296 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2297 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2298 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2299 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2300 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2301 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2304 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2305 if (word == 0xffff) {
2306 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2308 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2309 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2312 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2313 if (word == 0xffff) {
2314 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2315 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2316 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2317 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2320 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2321 if (word == 0xffff) {
2322 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2323 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2324 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2325 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2327 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2328 if (value < -10 || value > 10)
2329 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2330 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2331 if (value < -10 || value > 10)
2332 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2333 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2336 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2337 if (word == 0xffff) {
2338 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2339 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2340 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2341 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2343 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2344 if (value < -10 || value > 10)
2345 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2346 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2347 if (value < -10 || value > 10)
2348 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2349 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2355 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2362 * Read EEPROM word for configuration.
2364 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2367 * Identify RF chipset.
2369 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2370 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2371 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2372 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2374 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2375 !rt2x00_rf(rt2x00dev, RF5325) &&
2376 !rt2x00_rf(rt2x00dev, RF2527) &&
2377 !rt2x00_rf(rt2x00dev, RF2529)) {
2378 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2383 * Determine number of antennas.
2385 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2386 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2389 * Identify default antenna configuration.
2391 rt2x00dev->default_ant.tx =
2392 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2393 rt2x00dev->default_ant.rx =
2394 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2397 * Read the Frame type.
2399 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2400 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2403 * Detect if this device has a hardware controlled radio.
2405 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2406 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2409 * Read frequency offset and RF programming sequence.
2411 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2412 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2413 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2415 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2418 * Read external LNA informations.
2420 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2422 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2423 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2424 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2425 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2428 * When working with a RF2529 chip without double antenna,
2429 * the antenna settings should be gathered from the NIC
2432 if (rt2x00_rf(rt2x00dev, RF2529) &&
2433 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2434 rt2x00dev->default_ant.rx =
2435 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2436 rt2x00dev->default_ant.tx =
2437 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2439 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2440 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2441 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2442 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2446 * Store led settings, for correct led behaviour.
2447 * If the eeprom value is invalid,
2448 * switch to default led mode.
2450 #ifdef CONFIG_RT2X00_LIB_LEDS
2451 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2452 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2454 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2455 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2456 if (value == LED_MODE_SIGNAL_STRENGTH)
2457 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2460 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2461 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2462 rt2x00_get_field16(eeprom,
2463 EEPROM_LED_POLARITY_GPIO_0));
2464 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2465 rt2x00_get_field16(eeprom,
2466 EEPROM_LED_POLARITY_GPIO_1));
2467 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2468 rt2x00_get_field16(eeprom,
2469 EEPROM_LED_POLARITY_GPIO_2));
2470 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2471 rt2x00_get_field16(eeprom,
2472 EEPROM_LED_POLARITY_GPIO_3));
2473 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2474 rt2x00_get_field16(eeprom,
2475 EEPROM_LED_POLARITY_GPIO_4));
2476 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2477 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2478 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2479 rt2x00_get_field16(eeprom,
2480 EEPROM_LED_POLARITY_RDY_G));
2481 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2482 rt2x00_get_field16(eeprom,
2483 EEPROM_LED_POLARITY_RDY_A));
2484 #endif /* CONFIG_RT2X00_LIB_LEDS */
2490 * RF value list for RF5225 & RF5325
2491 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2493 static const struct rf_channel rf_vals_noseq[] = {
2494 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2495 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2496 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2497 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2498 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2499 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2500 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2501 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2502 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2503 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2504 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2505 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2506 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2507 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2509 /* 802.11 UNI / HyperLan 2 */
2510 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2511 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2512 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2513 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2514 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2515 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2516 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2517 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2519 /* 802.11 HyperLan 2 */
2520 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2521 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2522 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2523 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2524 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2525 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2526 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2527 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2528 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2529 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2532 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2533 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2534 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2535 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2536 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2537 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2539 /* MMAC(Japan)J52 ch 34,38,42,46 */
2540 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2541 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2542 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2543 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2547 * RF value list for RF5225 & RF5325
2548 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2550 static const struct rf_channel rf_vals_seq[] = {
2551 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2552 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2553 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2554 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2555 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2556 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2557 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2558 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2559 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2560 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2561 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2562 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2563 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2564 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2566 /* 802.11 UNI / HyperLan 2 */
2567 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2568 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2569 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2570 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2571 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2572 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2573 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2574 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2576 /* 802.11 HyperLan 2 */
2577 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2578 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2579 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2580 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2581 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2582 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2583 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2584 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2585 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2586 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2589 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2590 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2591 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2592 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2593 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2594 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2596 /* MMAC(Japan)J52 ch 34,38,42,46 */
2597 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2598 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2599 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2600 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2603 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2605 struct hw_mode_spec *spec = &rt2x00dev->spec;
2606 struct channel_info *info;
2611 * Disable powersaving as default.
2613 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2616 * Initialize all hw fields.
2618 rt2x00dev->hw->flags =
2619 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2620 IEEE80211_HW_SIGNAL_DBM |
2621 IEEE80211_HW_SUPPORTS_PS |
2622 IEEE80211_HW_PS_NULLFUNC_STACK;
2624 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2625 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2626 rt2x00_eeprom_addr(rt2x00dev,
2627 EEPROM_MAC_ADDR_0));
2630 * As rt61 has a global fallback table we cannot specify
2631 * more then one tx rate per frame but since the hw will
2632 * try several rates (based on the fallback table) we should
2633 * still initialize max_rates to the maximum number of rates
2634 * we are going to try. Otherwise mac80211 will truncate our
2635 * reported tx rates and the rc algortihm will end up with
2638 rt2x00dev->hw->max_rates = 7;
2639 rt2x00dev->hw->max_rate_tries = 1;
2642 * Initialize hw_mode information.
2644 spec->supported_bands = SUPPORT_BAND_2GHZ;
2645 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2647 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2648 spec->num_channels = 14;
2649 spec->channels = rf_vals_noseq;
2651 spec->num_channels = 14;
2652 spec->channels = rf_vals_seq;
2655 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2656 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2657 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2661 * Create channel information array
2663 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2667 spec->channels_info = info;
2669 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2670 for (i = 0; i < 14; i++) {
2671 info[i].max_power = MAX_TXPOWER;
2672 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2675 if (spec->num_channels > 14) {
2676 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2677 for (i = 14; i < spec->num_channels; i++) {
2678 info[i].max_power = MAX_TXPOWER;
2679 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2686 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2691 * Disable power saving.
2693 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2696 * Allocate eeprom data.
2698 retval = rt61pci_validate_eeprom(rt2x00dev);
2702 retval = rt61pci_init_eeprom(rt2x00dev);
2707 * Initialize hw specifications.
2709 retval = rt61pci_probe_hw_mode(rt2x00dev);
2714 * This device has multiple filters for control frames,
2715 * but has no a separate filter for PS Poll frames.
2717 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2720 * This device requires firmware and DMA mapped skbs.
2722 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2723 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2724 if (!modparam_nohwcrypt)
2725 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2726 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2729 * Set the rssi offset.
2731 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2737 * IEEE80211 stack callback functions.
2739 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2740 const struct ieee80211_tx_queue_params *params)
2742 struct rt2x00_dev *rt2x00dev = hw->priv;
2743 struct data_queue *queue;
2744 struct rt2x00_field32 field;
2750 * First pass the configuration through rt2x00lib, that will
2751 * update the queue settings and validate the input. After that
2752 * we are free to update the registers based on the value
2753 * in the queue parameter.
2755 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2760 * We only need to perform additional register initialization
2766 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2768 /* Update WMM TXOP register */
2769 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2770 field.bit_offset = (queue_idx & 1) * 16;
2771 field.bit_mask = 0xffff << field.bit_offset;
2773 rt2x00pci_register_read(rt2x00dev, offset, ®);
2774 rt2x00_set_field32(®, field, queue->txop);
2775 rt2x00pci_register_write(rt2x00dev, offset, reg);
2777 /* Update WMM registers */
2778 field.bit_offset = queue_idx * 4;
2779 field.bit_mask = 0xf << field.bit_offset;
2781 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®);
2782 rt2x00_set_field32(®, field, queue->aifs);
2783 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2785 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®);
2786 rt2x00_set_field32(®, field, queue->cw_min);
2787 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2789 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®);
2790 rt2x00_set_field32(®, field, queue->cw_max);
2791 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2796 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2798 struct rt2x00_dev *rt2x00dev = hw->priv;
2802 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2803 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2804 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2805 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2810 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2812 .start = rt2x00mac_start,
2813 .stop = rt2x00mac_stop,
2814 .add_interface = rt2x00mac_add_interface,
2815 .remove_interface = rt2x00mac_remove_interface,
2816 .config = rt2x00mac_config,
2817 .configure_filter = rt2x00mac_configure_filter,
2818 .set_key = rt2x00mac_set_key,
2819 .sw_scan_start = rt2x00mac_sw_scan_start,
2820 .sw_scan_complete = rt2x00mac_sw_scan_complete,
2821 .get_stats = rt2x00mac_get_stats,
2822 .bss_info_changed = rt2x00mac_bss_info_changed,
2823 .conf_tx = rt61pci_conf_tx,
2824 .get_tsf = rt61pci_get_tsf,
2825 .rfkill_poll = rt2x00mac_rfkill_poll,
2828 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2829 .irq_handler = rt61pci_interrupt,
2830 .irq_handler_thread = rt61pci_interrupt_thread,
2831 .probe_hw = rt61pci_probe_hw,
2832 .get_firmware_name = rt61pci_get_firmware_name,
2833 .check_firmware = rt61pci_check_firmware,
2834 .load_firmware = rt61pci_load_firmware,
2835 .initialize = rt2x00pci_initialize,
2836 .uninitialize = rt2x00pci_uninitialize,
2837 .get_entry_state = rt61pci_get_entry_state,
2838 .clear_entry = rt61pci_clear_entry,
2839 .set_device_state = rt61pci_set_device_state,
2840 .rfkill_poll = rt61pci_rfkill_poll,
2841 .link_stats = rt61pci_link_stats,
2842 .reset_tuner = rt61pci_reset_tuner,
2843 .link_tuner = rt61pci_link_tuner,
2844 .write_tx_desc = rt61pci_write_tx_desc,
2845 .write_beacon = rt61pci_write_beacon,
2846 .kick_tx_queue = rt61pci_kick_tx_queue,
2847 .kill_tx_queue = rt61pci_kill_tx_queue,
2848 .fill_rxdone = rt61pci_fill_rxdone,
2849 .config_shared_key = rt61pci_config_shared_key,
2850 .config_pairwise_key = rt61pci_config_pairwise_key,
2851 .config_filter = rt61pci_config_filter,
2852 .config_intf = rt61pci_config_intf,
2853 .config_erp = rt61pci_config_erp,
2854 .config_ant = rt61pci_config_ant,
2855 .config = rt61pci_config,
2858 static const struct data_queue_desc rt61pci_queue_rx = {
2859 .entry_num = RX_ENTRIES,
2860 .data_size = DATA_FRAME_SIZE,
2861 .desc_size = RXD_DESC_SIZE,
2862 .priv_size = sizeof(struct queue_entry_priv_pci),
2865 static const struct data_queue_desc rt61pci_queue_tx = {
2866 .entry_num = TX_ENTRIES,
2867 .data_size = DATA_FRAME_SIZE,
2868 .desc_size = TXD_DESC_SIZE,
2869 .priv_size = sizeof(struct queue_entry_priv_pci),
2872 static const struct data_queue_desc rt61pci_queue_bcn = {
2873 .entry_num = 4 * BEACON_ENTRIES,
2874 .data_size = 0, /* No DMA required for beacons */
2875 .desc_size = TXINFO_SIZE,
2876 .priv_size = sizeof(struct queue_entry_priv_pci),
2879 static const struct rt2x00_ops rt61pci_ops = {
2880 .name = KBUILD_MODNAME,
2883 .eeprom_size = EEPROM_SIZE,
2885 .tx_queues = NUM_TX_QUEUES,
2886 .extra_tx_headroom = 0,
2887 .rx = &rt61pci_queue_rx,
2888 .tx = &rt61pci_queue_tx,
2889 .bcn = &rt61pci_queue_bcn,
2890 .lib = &rt61pci_rt2x00_ops,
2891 .hw = &rt61pci_mac80211_ops,
2892 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2893 .debugfs = &rt61pci_rt2x00debug,
2894 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2898 * RT61pci module information.
2900 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2902 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2904 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2906 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2910 MODULE_AUTHOR(DRV_PROJECT);
2911 MODULE_VERSION(DRV_VERSION);
2912 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2913 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2914 "PCI & PCMCIA chipset based cards");
2915 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2916 MODULE_FIRMWARE(FIRMWARE_RT2561);
2917 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2918 MODULE_FIRMWARE(FIRMWARE_RT2661);
2919 MODULE_LICENSE("GPL");
2921 static struct pci_driver rt61pci_driver = {
2922 .name = KBUILD_MODNAME,
2923 .id_table = rt61pci_device_table,
2924 .probe = rt2x00pci_probe,
2925 .remove = __devexit_p(rt2x00pci_remove),
2926 .suspend = rt2x00pci_suspend,
2927 .resume = rt2x00pci_resume,
2930 static int __init rt61pci_init(void)
2932 return pci_register_driver(&rt61pci_driver);
2935 static void __exit rt61pci_exit(void)
2937 pci_unregister_driver(&rt61pci_driver);
2940 module_init(rt61pci_init);
2941 module_exit(rt61pci_exit);