2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
37 #include "rt2x00pci.h"
41 * Allow hardware encryption to be disabled.
43 static int modparam_nohwcrypt = 0;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
58 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
63 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
64 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
65 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
67 udelay(REGISTER_BUSY_DELAY);
73 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
74 const unsigned int word, const u8 value)
79 * Wait until the BBP becomes ready.
81 reg = rt61pci_bbp_check(rt2x00dev);
82 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
83 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
88 * Write the data into the BBP.
91 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
92 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
93 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
94 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
96 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
99 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
100 const unsigned int word, u8 *value)
105 * Wait until the BBP becomes ready.
107 reg = rt61pci_bbp_check(rt2x00dev);
108 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
109 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
114 * Write the request into the BBP.
117 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
118 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
119 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
121 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
124 * Wait until the BBP becomes ready.
126 reg = rt61pci_bbp_check(rt2x00dev);
127 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
128 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
133 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
136 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
137 const unsigned int word, const u32 value)
145 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
146 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
147 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
149 udelay(REGISTER_BUSY_DELAY);
152 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
157 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
158 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
159 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
160 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
162 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
163 rt2x00_rf_write(rt2x00dev, word, value);
166 #ifdef CONFIG_RT2X00_LIB_LEDS
168 * This function is only called from rt61pci_led_brightness()
169 * make gcc happy by placing this function inside the
170 * same ifdef statement as the caller.
172 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
173 const u8 command, const u8 token,
174 const u8 arg0, const u8 arg1)
178 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
180 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
181 ERROR(rt2x00dev, "mcu request error. "
182 "Request 0x%02x failed for token 0x%02x.\n",
187 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
188 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
189 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
190 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
191 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
193 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
194 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
195 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
196 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
198 #endif /* CONFIG_RT2X00_LIB_LEDS */
200 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
205 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
207 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
208 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
209 eeprom->reg_data_clock =
210 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
211 eeprom->reg_chip_select =
212 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
215 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
217 struct rt2x00_dev *rt2x00dev = eeprom->data;
220 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
221 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
222 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
223 !!eeprom->reg_data_clock);
224 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
225 !!eeprom->reg_chip_select);
227 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
230 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
231 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
233 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
234 const unsigned int word, u32 *data)
236 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
239 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
240 const unsigned int word, u32 data)
242 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
245 static const struct rt2x00debug rt61pci_rt2x00debug = {
246 .owner = THIS_MODULE,
248 .read = rt61pci_read_csr,
249 .write = rt61pci_write_csr,
250 .word_size = sizeof(u32),
251 .word_count = CSR_REG_SIZE / sizeof(u32),
254 .read = rt2x00_eeprom_read,
255 .write = rt2x00_eeprom_write,
256 .word_size = sizeof(u16),
257 .word_count = EEPROM_SIZE / sizeof(u16),
260 .read = rt61pci_bbp_read,
261 .write = rt61pci_bbp_write,
262 .word_size = sizeof(u8),
263 .word_count = BBP_SIZE / sizeof(u8),
266 .read = rt2x00_rf_read,
267 .write = rt61pci_rf_write,
268 .word_size = sizeof(u32),
269 .word_count = RF_SIZE / sizeof(u32),
272 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
274 #ifdef CONFIG_RT2X00_LIB_RFKILL
275 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
279 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
280 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
283 #define rt61pci_rfkill_poll NULL
284 #endif /* CONFIG_RT2X00_LIB_RFKILL */
286 #ifdef CONFIG_RT2X00_LIB_LEDS
287 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
288 enum led_brightness brightness)
290 struct rt2x00_led *led =
291 container_of(led_cdev, struct rt2x00_led, led_dev);
292 unsigned int enabled = brightness != LED_OFF;
293 unsigned int a_mode =
294 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
295 unsigned int bg_mode =
296 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
298 if (led->type == LED_TYPE_RADIO) {
299 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300 MCU_LEDCS_RADIO_STATUS, enabled);
302 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
303 (led->rt2x00dev->led_mcu_reg & 0xff),
304 ((led->rt2x00dev->led_mcu_reg >> 8)));
305 } else if (led->type == LED_TYPE_ASSOC) {
306 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
307 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
308 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
309 MCU_LEDCS_LINK_A_STATUS, a_mode);
311 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
312 (led->rt2x00dev->led_mcu_reg & 0xff),
313 ((led->rt2x00dev->led_mcu_reg >> 8)));
314 } else if (led->type == LED_TYPE_QUALITY) {
316 * The brightness is divided into 6 levels (0 - 5),
317 * this means we need to convert the brightness
318 * argument into the matching level within that range.
320 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
321 brightness / (LED_FULL / 6), 0);
325 static int rt61pci_blink_set(struct led_classdev *led_cdev,
326 unsigned long *delay_on,
327 unsigned long *delay_off)
329 struct rt2x00_led *led =
330 container_of(led_cdev, struct rt2x00_led, led_dev);
333 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
334 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
335 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
336 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
341 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
342 struct rt2x00_led *led,
345 led->rt2x00dev = rt2x00dev;
347 led->led_dev.brightness_set = rt61pci_brightness_set;
348 led->led_dev.blink_set = rt61pci_blink_set;
349 led->flags = LED_INITIALIZED;
351 #endif /* CONFIG_RT2X00_LIB_LEDS */
354 * Configuration handlers.
356 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
357 struct rt2x00lib_crypto *crypto,
358 struct ieee80211_key_conf *key)
360 struct hw_key_entry key_entry;
361 struct rt2x00_field32 field;
365 if (crypto->cmd == SET_KEY) {
367 * rt2x00lib can't determine the correct free
368 * key_idx for shared keys. We have 1 register
369 * with key valid bits. The goal is simple, read
370 * the register, if that is full we have no slots
372 * Note that each BSS is allowed to have up to 4
373 * shared keys, so put a mask over the allowed
376 mask = (0xf << crypto->bssidx);
378 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
381 if (reg && reg == mask)
384 key->hw_key_idx += reg ? ffz(reg) : 0;
387 * Upload key to hardware
389 memcpy(key_entry.key, crypto->key,
390 sizeof(key_entry.key));
391 memcpy(key_entry.tx_mic, crypto->tx_mic,
392 sizeof(key_entry.tx_mic));
393 memcpy(key_entry.rx_mic, crypto->rx_mic,
394 sizeof(key_entry.rx_mic));
396 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
397 rt2x00pci_register_multiwrite(rt2x00dev, reg,
398 &key_entry, sizeof(key_entry));
401 * The cipher types are stored over 2 registers.
402 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
403 * bssidx 1 and 2 keys are stored in SEC_CSR5.
404 * Using the correct defines correctly will cause overhead,
405 * so just calculate the correct offset.
407 if (key->hw_key_idx < 8) {
408 field.bit_offset = (3 * key->hw_key_idx);
409 field.bit_mask = 0x7 << field.bit_offset;
411 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®);
412 rt2x00_set_field32(®, field, crypto->cipher);
413 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
415 field.bit_offset = (3 * (key->hw_key_idx - 8));
416 field.bit_mask = 0x7 << field.bit_offset;
418 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®);
419 rt2x00_set_field32(®, field, crypto->cipher);
420 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
424 * The driver does not support the IV/EIV generation
425 * in hardware. However it doesn't support the IV/EIV
426 * inside the ieee80211 frame either, but requires it
427 * to be provided seperately for the descriptor.
428 * rt2x00lib will cut the IV/EIV data out of all frames
429 * given to us by mac80211, but we must tell mac80211
430 * to generate the IV/EIV data.
432 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
436 * SEC_CSR0 contains only single-bit fields to indicate
437 * a particular key is valid. Because using the FIELD32()
438 * defines directly will cause a lot of overhead we use
439 * a calculation to determine the correct bit directly.
441 mask = 1 << key->hw_key_idx;
443 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®);
444 if (crypto->cmd == SET_KEY)
446 else if (crypto->cmd == DISABLE_KEY)
448 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
453 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
454 struct rt2x00lib_crypto *crypto,
455 struct ieee80211_key_conf *key)
457 struct hw_pairwise_ta_entry addr_entry;
458 struct hw_key_entry key_entry;
462 if (crypto->cmd == SET_KEY) {
464 * rt2x00lib can't determine the correct free
465 * key_idx for pairwise keys. We have 2 registers
466 * with key valid bits. The goal is simple, read
467 * the first register, if that is full move to
469 * When both registers are full, we drop the key,
470 * otherwise we use the first invalid entry.
472 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
473 if (reg && reg == ~0) {
474 key->hw_key_idx = 32;
475 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
476 if (reg && reg == ~0)
480 key->hw_key_idx += reg ? ffz(reg) : 0;
483 * Upload key to hardware
485 memcpy(key_entry.key, crypto->key,
486 sizeof(key_entry.key));
487 memcpy(key_entry.tx_mic, crypto->tx_mic,
488 sizeof(key_entry.tx_mic));
489 memcpy(key_entry.rx_mic, crypto->rx_mic,
490 sizeof(key_entry.rx_mic));
492 memset(&addr_entry, 0, sizeof(addr_entry));
493 memcpy(&addr_entry, crypto->address, ETH_ALEN);
494 addr_entry.cipher = crypto->cipher;
496 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
497 rt2x00pci_register_multiwrite(rt2x00dev, reg,
498 &key_entry, sizeof(key_entry));
500 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
501 rt2x00pci_register_multiwrite(rt2x00dev, reg,
502 &addr_entry, sizeof(addr_entry));
505 * Enable pairwise lookup table for given BSS idx,
506 * without this received frames will not be decrypted
509 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®);
510 reg |= (1 << crypto->bssidx);
511 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
514 * The driver does not support the IV/EIV generation
515 * in hardware. However it doesn't support the IV/EIV
516 * inside the ieee80211 frame either, but requires it
517 * to be provided seperately for the descriptor.
518 * rt2x00lib will cut the IV/EIV data out of all frames
519 * given to us by mac80211, but we must tell mac80211
520 * to generate the IV/EIV data.
522 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
526 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
527 * a particular key is valid. Because using the FIELD32()
528 * defines directly will cause a lot of overhead we use
529 * a calculation to determine the correct bit directly.
531 if (key->hw_key_idx < 32) {
532 mask = 1 << key->hw_key_idx;
534 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®);
535 if (crypto->cmd == SET_KEY)
537 else if (crypto->cmd == DISABLE_KEY)
539 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
541 mask = 1 << (key->hw_key_idx - 32);
543 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®);
544 if (crypto->cmd == SET_KEY)
546 else if (crypto->cmd == DISABLE_KEY)
548 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
554 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
555 const unsigned int filter_flags)
560 * Start configuration steps.
561 * Note that the version error will always be dropped
562 * and broadcast frames will always be accepted since
563 * there is no filter for it at this time.
565 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
566 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
567 !(filter_flags & FIF_FCSFAIL));
568 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
569 !(filter_flags & FIF_PLCPFAIL));
570 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
571 !(filter_flags & FIF_CONTROL));
572 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
573 !(filter_flags & FIF_PROMISC_IN_BSS));
574 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
575 !(filter_flags & FIF_PROMISC_IN_BSS) &&
576 !rt2x00dev->intf_ap_count);
577 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
578 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
579 !(filter_flags & FIF_ALLMULTI));
580 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
581 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
582 !(filter_flags & FIF_CONTROL));
583 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
586 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00_intf *intf,
588 struct rt2x00intf_conf *conf,
589 const unsigned int flags)
591 unsigned int beacon_base;
594 if (flags & CONFIG_UPDATE_TYPE) {
596 * Clear current synchronisation setup.
597 * For the Beacon base registers we only need to clear
598 * the first byte since that byte contains the VALID and OWNER
599 * bits which (when set to 0) will invalidate the entire beacon.
601 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
602 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
605 * Enable synchronisation.
607 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
608 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
609 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
610 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
614 if (flags & CONFIG_UPDATE_MAC) {
615 reg = le32_to_cpu(conf->mac[1]);
616 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
617 conf->mac[1] = cpu_to_le32(reg);
619 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
620 conf->mac, sizeof(conf->mac));
623 if (flags & CONFIG_UPDATE_BSSID) {
624 reg = le32_to_cpu(conf->bssid[1]);
625 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
626 conf->bssid[1] = cpu_to_le32(reg);
628 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
629 conf->bssid, sizeof(conf->bssid));
633 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
634 struct rt2x00lib_erp *erp)
638 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
639 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
640 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
642 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
643 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
644 !!erp->short_preamble);
645 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
647 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
649 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
650 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time);
651 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
653 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
654 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs);
655 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
656 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs);
657 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
660 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
661 struct antenna_setup *ant)
667 rt61pci_bbp_read(rt2x00dev, 3, &r3);
668 rt61pci_bbp_read(rt2x00dev, 4, &r4);
669 rt61pci_bbp_read(rt2x00dev, 77, &r77);
671 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
672 rt2x00_rf(&rt2x00dev->chip, RF5325));
675 * Configure the RX antenna.
678 case ANTENNA_HW_DIVERSITY:
679 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
680 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
681 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
684 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
685 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
686 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
687 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
689 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
693 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
694 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
695 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
696 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
698 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
702 rt61pci_bbp_write(rt2x00dev, 77, r77);
703 rt61pci_bbp_write(rt2x00dev, 3, r3);
704 rt61pci_bbp_write(rt2x00dev, 4, r4);
707 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
708 struct antenna_setup *ant)
714 rt61pci_bbp_read(rt2x00dev, 3, &r3);
715 rt61pci_bbp_read(rt2x00dev, 4, &r4);
716 rt61pci_bbp_read(rt2x00dev, 77, &r77);
718 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
719 rt2x00_rf(&rt2x00dev->chip, RF2529));
720 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
721 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
724 * Configure the RX antenna.
727 case ANTENNA_HW_DIVERSITY:
728 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
731 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
732 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
736 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
737 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
741 rt61pci_bbp_write(rt2x00dev, 77, r77);
742 rt61pci_bbp_write(rt2x00dev, 3, r3);
743 rt61pci_bbp_write(rt2x00dev, 4, r4);
746 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
747 const int p1, const int p2)
751 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
753 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
754 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
756 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
757 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
759 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
762 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
763 struct antenna_setup *ant)
769 rt61pci_bbp_read(rt2x00dev, 3, &r3);
770 rt61pci_bbp_read(rt2x00dev, 4, &r4);
771 rt61pci_bbp_read(rt2x00dev, 77, &r77);
774 * Configure the RX antenna.
778 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
779 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
780 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
782 case ANTENNA_HW_DIVERSITY:
784 * FIXME: Antenna selection for the rf 2529 is very confusing
785 * in the legacy driver. Just default to antenna B until the
786 * legacy code can be properly translated into rt2x00 code.
790 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
791 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
792 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
796 rt61pci_bbp_write(rt2x00dev, 77, r77);
797 rt61pci_bbp_write(rt2x00dev, 3, r3);
798 rt61pci_bbp_write(rt2x00dev, 4, r4);
804 * value[0] -> non-LNA
810 static const struct antenna_sel antenna_sel_a[] = {
811 { 96, { 0x58, 0x78 } },
812 { 104, { 0x38, 0x48 } },
813 { 75, { 0xfe, 0x80 } },
814 { 86, { 0xfe, 0x80 } },
815 { 88, { 0xfe, 0x80 } },
816 { 35, { 0x60, 0x60 } },
817 { 97, { 0x58, 0x58 } },
818 { 98, { 0x58, 0x58 } },
821 static const struct antenna_sel antenna_sel_bg[] = {
822 { 96, { 0x48, 0x68 } },
823 { 104, { 0x2c, 0x3c } },
824 { 75, { 0xfe, 0x80 } },
825 { 86, { 0xfe, 0x80 } },
826 { 88, { 0xfe, 0x80 } },
827 { 35, { 0x50, 0x50 } },
828 { 97, { 0x48, 0x48 } },
829 { 98, { 0x48, 0x48 } },
832 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
833 struct antenna_setup *ant)
835 const struct antenna_sel *sel;
841 * We should never come here because rt2x00lib is supposed
842 * to catch this and send us the correct antenna explicitely.
844 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
845 ant->tx == ANTENNA_SW_DIVERSITY);
847 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
849 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
851 sel = antenna_sel_bg;
852 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
855 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
856 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
858 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
860 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
861 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
862 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
863 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
865 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
867 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
868 rt2x00_rf(&rt2x00dev->chip, RF5325))
869 rt61pci_config_antenna_5x(rt2x00dev, ant);
870 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
871 rt61pci_config_antenna_2x(rt2x00dev, ant);
872 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
873 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
874 rt61pci_config_antenna_2x(rt2x00dev, ant);
876 rt61pci_config_antenna_2529(rt2x00dev, ant);
880 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
881 struct rt2x00lib_conf *libconf)
886 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
887 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
890 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
891 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
893 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
896 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
897 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
900 rt2x00dev->lna_gain = lna_gain;
903 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
904 struct rf_channel *rf, const int txpower)
910 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
911 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
913 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
914 rt2x00_rf(&rt2x00dev->chip, RF2527));
916 rt61pci_bbp_read(rt2x00dev, 3, &r3);
917 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
918 rt61pci_bbp_write(rt2x00dev, 3, r3);
921 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
922 r94 += txpower - MAX_TXPOWER;
923 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
925 rt61pci_bbp_write(rt2x00dev, 94, r94);
927 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
928 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
929 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
930 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
934 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
935 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
936 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
937 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
941 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
942 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
943 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
944 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
949 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
952 struct rf_channel rf;
954 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
955 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
956 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
957 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
959 rt61pci_config_channel(rt2x00dev, &rf, txpower);
962 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
963 struct rt2x00lib_conf *libconf)
967 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
968 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT,
969 libconf->conf->long_frame_max_tx_count);
970 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT,
971 libconf->conf->short_frame_max_tx_count);
972 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
975 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
976 struct rt2x00lib_conf *libconf)
980 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
981 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
982 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
984 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
985 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
986 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
988 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
989 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
990 libconf->conf->beacon_int * 16);
991 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
994 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
995 struct rt2x00lib_conf *libconf,
996 const unsigned int flags)
998 /* Always recalculate LNA gain before changing configuration */
999 rt61pci_config_lna_gain(rt2x00dev, libconf);
1001 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1002 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1003 libconf->conf->power_level);
1004 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1005 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1006 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1007 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1008 rt61pci_config_retry_limit(rt2x00dev, libconf);
1009 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1010 rt61pci_config_duration(rt2x00dev, libconf);
1016 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1017 struct link_qual *qual)
1022 * Update FCS error count from register.
1024 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1025 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1028 * Update False CCA count from register.
1030 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1031 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1034 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1036 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1037 rt2x00dev->link.vgc_level = 0x20;
1040 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1042 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1047 rt61pci_bbp_read(rt2x00dev, 17, &r17);
1050 * Determine r17 bounds.
1052 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1055 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1062 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1069 * If we are not associated, we should go straight to the
1070 * dynamic CCA tuning.
1072 if (!rt2x00dev->intf_associated)
1073 goto dynamic_cca_tune;
1076 * Special big-R17 for very short distance
1080 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1085 * Special big-R17 for short distance
1088 if (r17 != up_bound)
1089 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1094 * Special big-R17 for middle-short distance
1098 if (r17 != low_bound)
1099 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1104 * Special mid-R17 for middle distance
1108 if (r17 != low_bound)
1109 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1114 * Special case: Change up_bound based on the rssi.
1115 * Lower up_bound when rssi is weaker then -74 dBm.
1117 up_bound -= 2 * (-74 - rssi);
1118 if (low_bound > up_bound)
1119 up_bound = low_bound;
1121 if (r17 > up_bound) {
1122 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1129 * r17 does not yet exceed upper limit, continue and base
1130 * the r17 tuning on the false CCA count.
1132 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1133 if (++r17 > up_bound)
1135 rt61pci_bbp_write(rt2x00dev, 17, r17);
1136 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1137 if (--r17 < low_bound)
1139 rt61pci_bbp_write(rt2x00dev, 17, r17);
1144 * Firmware functions
1146 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1150 switch (rt2x00dev->chip.rt) {
1152 fw_name = FIRMWARE_RT2561;
1155 fw_name = FIRMWARE_RT2561s;
1158 fw_name = FIRMWARE_RT2661;
1168 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1173 * Use the crc itu-t algorithm.
1174 * The last 2 bytes in the firmware array are the crc checksum itself,
1175 * this means that we should never pass those 2 bytes to the crc
1178 crc = crc_itu_t(0, data, len - 2);
1179 crc = crc_itu_t_byte(crc, 0);
1180 crc = crc_itu_t_byte(crc, 0);
1185 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1192 * Wait for stable hardware.
1194 for (i = 0; i < 100; i++) {
1195 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1202 ERROR(rt2x00dev, "Unstable hardware.\n");
1207 * Prepare MCU and mailbox for firmware loading.
1210 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1211 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1212 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1213 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1214 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1217 * Write firmware to device.
1220 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1221 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1222 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1224 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1227 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1228 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1230 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1231 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233 for (i = 0; i < 100; i++) {
1234 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1235 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1241 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1246 * Hardware needs another millisecond before it is ready.
1251 * Reset MAC and BBP registers.
1254 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1255 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1256 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1258 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1259 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1260 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1261 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1263 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1264 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1265 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1271 * Initialization functions.
1273 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1274 struct queue_entry *entry)
1276 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1277 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1280 rt2x00_desc_read(entry_priv->desc, 5, &word);
1281 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1283 rt2x00_desc_write(entry_priv->desc, 5, word);
1285 rt2x00_desc_read(entry_priv->desc, 0, &word);
1286 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1287 rt2x00_desc_write(entry_priv->desc, 0, word);
1290 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1291 struct queue_entry *entry)
1293 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1296 rt2x00_desc_read(entry_priv->desc, 0, &word);
1297 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1298 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1299 rt2x00_desc_write(entry_priv->desc, 0, word);
1302 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1304 struct queue_entry_priv_pci *entry_priv;
1308 * Initialize registers.
1310 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1311 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1312 rt2x00dev->tx[0].limit);
1313 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1314 rt2x00dev->tx[1].limit);
1315 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1316 rt2x00dev->tx[2].limit);
1317 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1318 rt2x00dev->tx[3].limit);
1319 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1321 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1322 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1323 rt2x00dev->tx[0].desc_size / 4);
1324 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1326 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1327 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1328 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1329 entry_priv->desc_dma);
1330 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1332 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1333 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1334 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1335 entry_priv->desc_dma);
1336 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1338 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1339 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1340 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1341 entry_priv->desc_dma);
1342 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1344 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1345 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1346 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1347 entry_priv->desc_dma);
1348 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1350 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1351 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1352 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1353 rt2x00dev->rx->desc_size / 4);
1354 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1355 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1357 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1358 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1359 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1360 entry_priv->desc_dma);
1361 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1363 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1364 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1365 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1366 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1367 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1368 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1370 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1371 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1372 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1373 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1374 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1375 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1377 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1378 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1379 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1384 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1388 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1389 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1390 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1391 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1392 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1394 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1395 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1396 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1397 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1398 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1399 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1400 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1401 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1402 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1403 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1406 * CCK TXD BBP registers
1408 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1409 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1410 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1411 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1412 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1413 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1414 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1415 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1416 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1417 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1420 * OFDM TXD BBP registers
1422 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1423 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1424 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1425 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1426 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1427 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1428 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1429 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1431 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1432 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1433 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1434 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1435 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1436 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1438 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1439 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1440 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1441 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1442 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1443 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1445 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1446 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0);
1447 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1448 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
1449 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1450 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1451 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1452 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1454 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1456 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1458 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1459 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1460 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1462 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1464 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1467 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1470 * Invalidate all Shared Keys (SEC_CSR0),
1471 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1473 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1474 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1475 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1477 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1478 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1479 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1480 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1482 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1484 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1486 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1490 * For the Beacon base registers we only need to clear
1491 * the first byte since that byte contains the VALID and OWNER
1492 * bits which (when set to 0) will invalidate the entire beacon.
1494 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1495 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1496 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1497 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1500 * We must clear the error counters.
1501 * These registers are cleared on read,
1502 * so we may pass a useless variable to store the value.
1504 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1505 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1506 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1509 * Reset MAC and BBP registers.
1511 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1512 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1513 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1514 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1516 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1517 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1518 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1519 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1521 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1522 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1523 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1528 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1533 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1534 rt61pci_bbp_read(rt2x00dev, 0, &value);
1535 if ((value != 0xff) && (value != 0x00))
1537 udelay(REGISTER_BUSY_DELAY);
1540 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1544 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1551 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1554 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1555 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1556 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1557 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1558 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1559 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1560 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1561 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1562 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1563 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1564 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1565 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1566 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1567 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1568 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1569 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1570 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1571 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1572 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1573 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1574 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1575 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1576 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1577 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1579 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1580 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1582 if (eeprom != 0xffff && eeprom != 0x0000) {
1583 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1584 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1585 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1593 * Device state switch handlers.
1595 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1596 enum dev_state state)
1600 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1601 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1602 (state == STATE_RADIO_RX_OFF) ||
1603 (state == STATE_RADIO_RX_OFF_LINK));
1604 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1607 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1608 enum dev_state state)
1610 int mask = (state == STATE_RADIO_IRQ_OFF);
1614 * When interrupts are being enabled, the interrupt registers
1615 * should clear the register to assure a clean state.
1617 if (state == STATE_RADIO_IRQ_ON) {
1618 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1619 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1621 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1622 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1626 * Only toggle the interrupts bits we are going to use.
1627 * Non-checked interrupt bits are disabled by default.
1629 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1630 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1631 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1632 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1633 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1634 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1636 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1637 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1638 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1639 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1640 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1641 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1642 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1643 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1644 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1645 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1648 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1653 * Initialize all registers.
1655 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1656 rt61pci_init_registers(rt2x00dev) ||
1657 rt61pci_init_bbp(rt2x00dev)))
1663 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1664 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1665 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1670 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1674 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1677 * Disable synchronisation.
1679 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1684 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1685 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1686 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1687 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1688 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1689 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1692 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1698 put_to_sleep = (state != STATE_AWAKE);
1700 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1701 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1702 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1703 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1706 * Device is not guaranteed to be in the requested state yet.
1707 * We must wait until the register indicates that the
1708 * device has entered the correct state.
1710 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1711 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1712 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1713 if (state == !put_to_sleep)
1721 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1722 enum dev_state state)
1727 case STATE_RADIO_ON:
1728 retval = rt61pci_enable_radio(rt2x00dev);
1730 case STATE_RADIO_OFF:
1731 rt61pci_disable_radio(rt2x00dev);
1733 case STATE_RADIO_RX_ON:
1734 case STATE_RADIO_RX_ON_LINK:
1735 case STATE_RADIO_RX_OFF:
1736 case STATE_RADIO_RX_OFF_LINK:
1737 rt61pci_toggle_rx(rt2x00dev, state);
1739 case STATE_RADIO_IRQ_ON:
1740 case STATE_RADIO_IRQ_OFF:
1741 rt61pci_toggle_irq(rt2x00dev, state);
1743 case STATE_DEEP_SLEEP:
1747 retval = rt61pci_set_state(rt2x00dev, state);
1754 if (unlikely(retval))
1755 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1762 * TX descriptor initialization
1764 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1765 struct sk_buff *skb,
1766 struct txentry_desc *txdesc)
1768 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1769 __le32 *txd = skbdesc->desc;
1773 * Start writing the descriptor words.
1775 rt2x00_desc_read(txd, 1, &word);
1776 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1777 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1778 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1779 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1780 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1781 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1782 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1783 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1784 rt2x00_desc_write(txd, 1, word);
1786 rt2x00_desc_read(txd, 2, &word);
1787 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1788 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1789 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1790 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1791 rt2x00_desc_write(txd, 2, word);
1793 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1794 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1795 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1798 rt2x00_desc_read(txd, 5, &word);
1799 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1800 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1801 skbdesc->entry->entry_idx);
1802 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1803 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1804 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1805 rt2x00_desc_write(txd, 5, word);
1807 rt2x00_desc_read(txd, 6, &word);
1808 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1810 rt2x00_desc_write(txd, 6, word);
1812 if (skbdesc->desc_len > TXINFO_SIZE) {
1813 rt2x00_desc_read(txd, 11, &word);
1814 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1815 rt2x00_desc_write(txd, 11, word);
1818 rt2x00_desc_read(txd, 0, &word);
1819 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1820 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1821 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1822 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1823 rt2x00_set_field32(&word, TXD_W0_ACK,
1824 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1825 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1826 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1827 rt2x00_set_field32(&word, TXD_W0_OFDM,
1828 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1829 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1830 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1831 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1832 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1833 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1834 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1835 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1836 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1837 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1838 rt2x00_set_field32(&word, TXD_W0_BURST,
1839 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1840 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1841 rt2x00_desc_write(txd, 0, word);
1845 * TX data initialization
1847 static void rt61pci_write_beacon(struct queue_entry *entry)
1849 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1850 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1851 unsigned int beacon_base;
1855 * Disable beaconing while we are reloading the beacon data,
1856 * otherwise we might be sending out invalid data.
1858 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1859 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1860 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1861 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1862 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1865 * Write entire beacon with descriptor to register.
1867 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1868 rt2x00pci_register_multiwrite(rt2x00dev,
1870 skbdesc->desc, skbdesc->desc_len);
1871 rt2x00pci_register_multiwrite(rt2x00dev,
1872 beacon_base + skbdesc->desc_len,
1873 entry->skb->data, entry->skb->len);
1876 * Clean up beacon skb.
1878 dev_kfree_skb_any(entry->skb);
1882 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1883 const enum data_queue_qid queue)
1887 if (queue == QID_BEACON) {
1889 * For Wi-Fi faily generated beacons between participating
1890 * stations. Set TBTT phase adaptive adjustment step to 8us.
1892 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1894 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1895 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1896 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1897 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1898 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1899 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1904 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1905 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1906 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1907 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1908 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1909 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1913 * RX control handlers
1915 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1917 u8 offset = rt2x00dev->lna_gain;
1920 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1935 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1936 if (lna == 3 || lna == 2)
1940 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1943 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1944 struct rxdone_entry_desc *rxdesc)
1946 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1947 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1951 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1952 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1954 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1955 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1957 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1959 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1960 rxdesc->cipher_status =
1961 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1964 if (rxdesc->cipher != CIPHER_NONE) {
1965 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1966 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1967 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1970 * Hardware has stripped IV/EIV data from 802.11 frame during
1971 * decryption. It has provided the data seperately but rt2x00lib
1972 * should decide if it should be reinserted.
1974 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1977 * FIXME: Legacy driver indicates that the frame does
1978 * contain the Michael Mic. Unfortunately, in rt2x00
1979 * the MIC seems to be missing completely...
1981 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1983 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1984 rxdesc->flags |= RX_FLAG_DECRYPTED;
1985 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1986 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1990 * Obtain the status about this packet.
1991 * When frame was received with an OFDM bitrate,
1992 * the signal is the PLCP value. If it was received with
1993 * a CCK bitrate the signal is the rate in 100kbit/s.
1995 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1996 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
1997 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1999 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2000 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2002 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2003 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2004 rxdesc->dev_flags |= RXDONE_MY_BSS;
2008 * Interrupt functions.
2010 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2012 struct data_queue *queue;
2013 struct queue_entry *entry;
2014 struct queue_entry *entry_done;
2015 struct queue_entry_priv_pci *entry_priv;
2016 struct txdone_entry_desc txdesc;
2024 * During each loop we will compare the freshly read
2025 * STA_CSR4 register value with the value read from
2026 * the previous loop. If the 2 values are equal then
2027 * we should stop processing because the chance it
2028 * quite big that the device has been unplugged and
2029 * we risk going into an endless loop.
2034 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
2035 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2043 * Skip this entry when it contains an invalid
2044 * queue identication number.
2046 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2047 queue = rt2x00queue_get_queue(rt2x00dev, type);
2048 if (unlikely(!queue))
2052 * Skip this entry when it contains an invalid
2055 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2056 if (unlikely(index >= queue->limit))
2059 entry = &queue->entries[index];
2060 entry_priv = entry->priv_data;
2061 rt2x00_desc_read(entry_priv->desc, 0, &word);
2063 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2064 !rt2x00_get_field32(word, TXD_W0_VALID))
2067 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2068 while (entry != entry_done) {
2070 * Just report any entries we missed as failed.
2073 "TX status report missed for entry %d\n",
2074 entry_done->entry_idx);
2077 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2080 rt2x00lib_txdone(entry_done, &txdesc);
2081 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2085 * Obtain the status about this packet.
2088 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2089 case 0: /* Success, maybe with retry */
2090 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2092 case 6: /* Failure, excessive retries */
2093 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2094 /* Don't break, this is a failed frame! */
2095 default: /* Failure */
2096 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2098 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2100 rt2x00lib_txdone(entry, &txdesc);
2104 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2106 struct rt2x00_dev *rt2x00dev = dev_instance;
2111 * Get the interrupt sources & saved to local variable.
2112 * Write register value back to clear pending interrupts.
2114 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
2115 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2117 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
2118 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2120 if (!reg && !reg_mcu)
2123 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2127 * Handle interrupts, walk through all bits
2128 * and run the tasks, the bits are checked in order of
2133 * 1 - Rx ring done interrupt.
2135 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2136 rt2x00pci_rxdone(rt2x00dev);
2139 * 2 - Tx ring done interrupt.
2141 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2142 rt61pci_txdone(rt2x00dev);
2145 * 3 - Handle MCU command done.
2148 rt2x00pci_register_write(rt2x00dev,
2149 M2H_CMD_DONE_CSR, 0xffffffff);
2155 * Device probe functions.
2157 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2159 struct eeprom_93cx6 eeprom;
2165 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
2167 eeprom.data = rt2x00dev;
2168 eeprom.register_read = rt61pci_eepromregister_read;
2169 eeprom.register_write = rt61pci_eepromregister_write;
2170 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2171 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2172 eeprom.reg_data_in = 0;
2173 eeprom.reg_data_out = 0;
2174 eeprom.reg_data_clock = 0;
2175 eeprom.reg_chip_select = 0;
2177 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2178 EEPROM_SIZE / sizeof(u16));
2181 * Start validation of the data that has been read.
2183 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2184 if (!is_valid_ether_addr(mac)) {
2185 random_ether_addr(mac);
2186 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2189 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2190 if (word == 0xffff) {
2191 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2192 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2194 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2196 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2197 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2198 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2199 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2200 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2201 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2204 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2205 if (word == 0xffff) {
2206 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2207 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2208 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2209 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2210 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2211 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2212 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2213 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2216 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2217 if (word == 0xffff) {
2218 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2220 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2221 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2224 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2225 if (word == 0xffff) {
2226 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2227 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2228 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2229 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2232 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2233 if (word == 0xffff) {
2234 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2235 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2236 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2237 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2239 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2240 if (value < -10 || value > 10)
2241 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2242 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2243 if (value < -10 || value > 10)
2244 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2245 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2248 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2249 if (word == 0xffff) {
2250 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2251 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2252 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2253 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2255 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2256 if (value < -10 || value > 10)
2257 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2258 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2259 if (value < -10 || value > 10)
2260 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2261 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2267 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2275 * Read EEPROM word for configuration.
2277 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2280 * Identify RF chipset.
2281 * To determine the RT chip we have to read the
2282 * PCI header of the device.
2284 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2285 PCI_CONFIG_HEADER_DEVICE, &device);
2286 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2287 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2288 rt2x00_set_chip(rt2x00dev, device, value, reg);
2290 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2291 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2292 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2293 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2294 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2299 * Determine number of antenna's.
2301 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2302 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2305 * Identify default antenna configuration.
2307 rt2x00dev->default_ant.tx =
2308 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2309 rt2x00dev->default_ant.rx =
2310 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2313 * Read the Frame type.
2315 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2316 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2319 * Detect if this device has an hardware controlled radio.
2321 #ifdef CONFIG_RT2X00_LIB_RFKILL
2322 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2323 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2324 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2327 * Read frequency offset and RF programming sequence.
2329 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2330 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2331 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2333 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2336 * Read external LNA informations.
2338 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2340 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2341 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2342 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2343 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2346 * When working with a RF2529 chip without double antenna
2347 * the antenna settings should be gathered from the NIC
2350 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2351 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2352 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2354 rt2x00dev->default_ant.tx = ANTENNA_B;
2355 rt2x00dev->default_ant.rx = ANTENNA_A;
2358 rt2x00dev->default_ant.tx = ANTENNA_B;
2359 rt2x00dev->default_ant.rx = ANTENNA_B;
2362 rt2x00dev->default_ant.tx = ANTENNA_A;
2363 rt2x00dev->default_ant.rx = ANTENNA_A;
2366 rt2x00dev->default_ant.tx = ANTENNA_A;
2367 rt2x00dev->default_ant.rx = ANTENNA_B;
2371 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2372 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2373 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2374 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2378 * Store led settings, for correct led behaviour.
2379 * If the eeprom value is invalid,
2380 * switch to default led mode.
2382 #ifdef CONFIG_RT2X00_LIB_LEDS
2383 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2384 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2386 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2387 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2388 if (value == LED_MODE_SIGNAL_STRENGTH)
2389 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2392 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2393 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2394 rt2x00_get_field16(eeprom,
2395 EEPROM_LED_POLARITY_GPIO_0));
2396 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2397 rt2x00_get_field16(eeprom,
2398 EEPROM_LED_POLARITY_GPIO_1));
2399 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2400 rt2x00_get_field16(eeprom,
2401 EEPROM_LED_POLARITY_GPIO_2));
2402 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2403 rt2x00_get_field16(eeprom,
2404 EEPROM_LED_POLARITY_GPIO_3));
2405 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2406 rt2x00_get_field16(eeprom,
2407 EEPROM_LED_POLARITY_GPIO_4));
2408 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2409 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2410 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2411 rt2x00_get_field16(eeprom,
2412 EEPROM_LED_POLARITY_RDY_G));
2413 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2414 rt2x00_get_field16(eeprom,
2415 EEPROM_LED_POLARITY_RDY_A));
2416 #endif /* CONFIG_RT2X00_LIB_LEDS */
2422 * RF value list for RF5225 & RF5325
2423 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2425 static const struct rf_channel rf_vals_noseq[] = {
2426 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2427 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2428 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2429 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2430 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2431 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2432 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2433 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2434 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2435 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2436 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2437 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2438 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2439 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2441 /* 802.11 UNI / HyperLan 2 */
2442 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2443 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2444 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2445 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2446 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2447 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2448 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2449 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2451 /* 802.11 HyperLan 2 */
2452 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2453 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2454 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2455 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2456 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2457 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2458 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2459 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2460 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2461 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2464 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2465 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2466 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2467 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2468 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2469 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2471 /* MMAC(Japan)J52 ch 34,38,42,46 */
2472 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2473 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2474 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2475 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2479 * RF value list for RF5225 & RF5325
2480 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2482 static const struct rf_channel rf_vals_seq[] = {
2483 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2484 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2485 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2486 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2487 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2488 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2489 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2490 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2491 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2492 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2493 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2494 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2495 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2496 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2498 /* 802.11 UNI / HyperLan 2 */
2499 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2500 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2501 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2502 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2503 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2504 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2505 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2506 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2508 /* 802.11 HyperLan 2 */
2509 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2510 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2511 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2512 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2513 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2514 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2515 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2516 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2517 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2518 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2521 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2522 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2523 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2524 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2525 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2526 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2528 /* MMAC(Japan)J52 ch 34,38,42,46 */
2529 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2530 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2531 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2532 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2535 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2537 struct hw_mode_spec *spec = &rt2x00dev->spec;
2538 struct channel_info *info;
2543 * Initialize all hw fields.
2545 rt2x00dev->hw->flags =
2546 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2547 IEEE80211_HW_SIGNAL_DBM;
2548 rt2x00dev->hw->extra_tx_headroom = 0;
2550 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2551 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2552 rt2x00_eeprom_addr(rt2x00dev,
2553 EEPROM_MAC_ADDR_0));
2556 * Initialize hw_mode information.
2558 spec->supported_bands = SUPPORT_BAND_2GHZ;
2559 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2561 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2562 spec->num_channels = 14;
2563 spec->channels = rf_vals_noseq;
2565 spec->num_channels = 14;
2566 spec->channels = rf_vals_seq;
2569 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2570 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2571 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2572 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2576 * Create channel information array
2578 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2582 spec->channels_info = info;
2584 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2585 for (i = 0; i < 14; i++)
2586 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2588 if (spec->num_channels > 14) {
2589 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2590 for (i = 14; i < spec->num_channels; i++)
2591 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2597 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2602 * Allocate eeprom data.
2604 retval = rt61pci_validate_eeprom(rt2x00dev);
2608 retval = rt61pci_init_eeprom(rt2x00dev);
2613 * Initialize hw specifications.
2615 retval = rt61pci_probe_hw_mode(rt2x00dev);
2620 * This device requires firmware and DMA mapped skbs.
2622 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2623 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2624 if (!modparam_nohwcrypt)
2625 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2628 * Set the rssi offset.
2630 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2636 * IEEE80211 stack callback functions.
2638 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2639 const struct ieee80211_tx_queue_params *params)
2641 struct rt2x00_dev *rt2x00dev = hw->priv;
2642 struct data_queue *queue;
2643 struct rt2x00_field32 field;
2648 * First pass the configuration through rt2x00lib, that will
2649 * update the queue settings and validate the input. After that
2650 * we are free to update the registers based on the value
2651 * in the queue parameter.
2653 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2657 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2659 /* Update WMM TXOP register */
2660 if (queue_idx < 2) {
2661 field.bit_offset = queue_idx * 16;
2662 field.bit_mask = 0xffff << field.bit_offset;
2664 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
2665 rt2x00_set_field32(®, field, queue->txop);
2666 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2667 } else if (queue_idx < 4) {
2668 field.bit_offset = (queue_idx - 2) * 16;
2669 field.bit_mask = 0xffff << field.bit_offset;
2671 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
2672 rt2x00_set_field32(®, field, queue->txop);
2673 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2676 /* Update WMM registers */
2677 field.bit_offset = queue_idx * 4;
2678 field.bit_mask = 0xf << field.bit_offset;
2680 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®);
2681 rt2x00_set_field32(®, field, queue->aifs);
2682 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2684 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®);
2685 rt2x00_set_field32(®, field, queue->cw_min);
2686 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2688 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®);
2689 rt2x00_set_field32(®, field, queue->cw_max);
2690 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2695 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2697 struct rt2x00_dev *rt2x00dev = hw->priv;
2701 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2702 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2703 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2704 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2709 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2711 .start = rt2x00mac_start,
2712 .stop = rt2x00mac_stop,
2713 .add_interface = rt2x00mac_add_interface,
2714 .remove_interface = rt2x00mac_remove_interface,
2715 .config = rt2x00mac_config,
2716 .config_interface = rt2x00mac_config_interface,
2717 .configure_filter = rt2x00mac_configure_filter,
2718 .set_key = rt2x00mac_set_key,
2719 .get_stats = rt2x00mac_get_stats,
2720 .bss_info_changed = rt2x00mac_bss_info_changed,
2721 .conf_tx = rt61pci_conf_tx,
2722 .get_tx_stats = rt2x00mac_get_tx_stats,
2723 .get_tsf = rt61pci_get_tsf,
2726 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2727 .irq_handler = rt61pci_interrupt,
2728 .probe_hw = rt61pci_probe_hw,
2729 .get_firmware_name = rt61pci_get_firmware_name,
2730 .get_firmware_crc = rt61pci_get_firmware_crc,
2731 .load_firmware = rt61pci_load_firmware,
2732 .initialize = rt2x00pci_initialize,
2733 .uninitialize = rt2x00pci_uninitialize,
2734 .init_rxentry = rt61pci_init_rxentry,
2735 .init_txentry = rt61pci_init_txentry,
2736 .set_device_state = rt61pci_set_device_state,
2737 .rfkill_poll = rt61pci_rfkill_poll,
2738 .link_stats = rt61pci_link_stats,
2739 .reset_tuner = rt61pci_reset_tuner,
2740 .link_tuner = rt61pci_link_tuner,
2741 .write_tx_desc = rt61pci_write_tx_desc,
2742 .write_tx_data = rt2x00pci_write_tx_data,
2743 .write_beacon = rt61pci_write_beacon,
2744 .kick_tx_queue = rt61pci_kick_tx_queue,
2745 .fill_rxdone = rt61pci_fill_rxdone,
2746 .config_shared_key = rt61pci_config_shared_key,
2747 .config_pairwise_key = rt61pci_config_pairwise_key,
2748 .config_filter = rt61pci_config_filter,
2749 .config_intf = rt61pci_config_intf,
2750 .config_erp = rt61pci_config_erp,
2751 .config_ant = rt61pci_config_ant,
2752 .config = rt61pci_config,
2755 static const struct data_queue_desc rt61pci_queue_rx = {
2756 .entry_num = RX_ENTRIES,
2757 .data_size = DATA_FRAME_SIZE,
2758 .desc_size = RXD_DESC_SIZE,
2759 .priv_size = sizeof(struct queue_entry_priv_pci),
2762 static const struct data_queue_desc rt61pci_queue_tx = {
2763 .entry_num = TX_ENTRIES,
2764 .data_size = DATA_FRAME_SIZE,
2765 .desc_size = TXD_DESC_SIZE,
2766 .priv_size = sizeof(struct queue_entry_priv_pci),
2769 static const struct data_queue_desc rt61pci_queue_bcn = {
2770 .entry_num = 4 * BEACON_ENTRIES,
2771 .data_size = 0, /* No DMA required for beacons */
2772 .desc_size = TXINFO_SIZE,
2773 .priv_size = sizeof(struct queue_entry_priv_pci),
2776 static const struct rt2x00_ops rt61pci_ops = {
2777 .name = KBUILD_MODNAME,
2780 .eeprom_size = EEPROM_SIZE,
2782 .tx_queues = NUM_TX_QUEUES,
2783 .rx = &rt61pci_queue_rx,
2784 .tx = &rt61pci_queue_tx,
2785 .bcn = &rt61pci_queue_bcn,
2786 .lib = &rt61pci_rt2x00_ops,
2787 .hw = &rt61pci_mac80211_ops,
2788 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2789 .debugfs = &rt61pci_rt2x00debug,
2790 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2794 * RT61pci module information.
2796 static struct pci_device_id rt61pci_device_table[] = {
2798 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2800 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2802 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2806 MODULE_AUTHOR(DRV_PROJECT);
2807 MODULE_VERSION(DRV_VERSION);
2808 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2809 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2810 "PCI & PCMCIA chipset based cards");
2811 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2812 MODULE_FIRMWARE(FIRMWARE_RT2561);
2813 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2814 MODULE_FIRMWARE(FIRMWARE_RT2661);
2815 MODULE_LICENSE("GPL");
2817 static struct pci_driver rt61pci_driver = {
2818 .name = KBUILD_MODNAME,
2819 .id_table = rt61pci_device_table,
2820 .probe = rt2x00pci_probe,
2821 .remove = __devexit_p(rt2x00pci_remove),
2822 .suspend = rt2x00pci_suspend,
2823 .resume = rt2x00pci_resume,
2826 static int __init rt61pci_init(void)
2828 return pci_register_driver(&rt61pci_driver);
2831 static void __exit rt61pci_exit(void)
2833 pci_unregister_driver(&rt61pci_driver);
2836 module_init(rt61pci_init);
2837 module_exit(rt61pci_exit);