2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/usb.h>
35 #include "rt2x00usb.h"
40 * All access to the CSR registers will go through the methods
41 * rt73usb_register_read and rt73usb_register_write.
42 * BBP and RF register require indirect register access,
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
44 * These indirect registers work with busy bits,
45 * and we will try maximal REGISTER_BUSY_COUNT times to access
46 * the register while taking a REGISTER_BUSY_DELAY us delay
47 * between each attampt. When the busy bit is still set at that time,
48 * the access attempt is considered to have failed,
49 * and we will print an error.
50 * The _lock versions must be used if you already hold the usb_cache_mutex
52 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
53 const unsigned int offset, u32 *value)
56 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
57 USB_VENDOR_REQUEST_IN, offset,
58 ®, sizeof(u32), REGISTER_TIMEOUT);
59 *value = le32_to_cpu(reg);
62 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
63 const unsigned int offset, u32 *value)
66 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
67 USB_VENDOR_REQUEST_IN, offset,
68 ®, sizeof(u32), REGISTER_TIMEOUT);
69 *value = le32_to_cpu(reg);
72 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
73 const unsigned int offset,
74 void *value, const u32 length)
76 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
79 value, length, timeout);
82 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
83 const unsigned int offset, u32 value)
85 __le32 reg = cpu_to_le32(value);
86 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
87 USB_VENDOR_REQUEST_OUT, offset,
88 ®, sizeof(u32), REGISTER_TIMEOUT);
91 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
92 const unsigned int offset, u32 value)
94 __le32 reg = cpu_to_le32(value);
95 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
96 USB_VENDOR_REQUEST_OUT, offset,
97 ®, sizeof(u32), REGISTER_TIMEOUT);
100 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
101 const unsigned int offset,
102 void *value, const u32 length)
104 int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
107 value, length, timeout);
110 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
116 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, ®);
117 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
119 udelay(REGISTER_BUSY_DELAY);
125 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
130 mutex_lock(&rt2x00dev->usb_cache_mutex);
133 * Wait until the BBP becomes ready.
135 reg = rt73usb_bbp_check(rt2x00dev);
136 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
137 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
138 mutex_unlock(&rt2x00dev->usb_cache_mutex);
143 * Write the data into the BBP.
146 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
147 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
148 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
149 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
151 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
152 mutex_unlock(&rt2x00dev->usb_cache_mutex);
155 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
156 const unsigned int word, u8 *value)
160 mutex_lock(&rt2x00dev->usb_cache_mutex);
163 * Wait until the BBP becomes ready.
165 reg = rt73usb_bbp_check(rt2x00dev);
166 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
167 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
168 mutex_unlock(&rt2x00dev->usb_cache_mutex);
173 * Write the request into the BBP.
176 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
177 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
178 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
180 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
183 * Wait until the BBP becomes ready.
185 reg = rt73usb_bbp_check(rt2x00dev);
186 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
187 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
192 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
193 mutex_unlock(&rt2x00dev->usb_cache_mutex);
196 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
197 const unsigned int word, const u32 value)
205 mutex_lock(&rt2x00dev->usb_cache_mutex);
207 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
208 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, ®);
209 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
211 udelay(REGISTER_BUSY_DELAY);
214 mutex_unlock(&rt2x00dev->usb_cache_mutex);
215 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
220 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
223 * RF5225 and RF2527 contain 21 bits per RF register value,
224 * all others contain 20 bits.
226 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
227 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
228 rt2x00_rf(&rt2x00dev->chip, RF2527)));
229 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
230 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
232 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
233 rt2x00_rf_write(rt2x00dev, word, value);
234 mutex_unlock(&rt2x00dev->usb_cache_mutex);
237 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
238 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
240 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
241 const unsigned int word, u32 *data)
243 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
246 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
247 const unsigned int word, u32 data)
249 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
252 static const struct rt2x00debug rt73usb_rt2x00debug = {
253 .owner = THIS_MODULE,
255 .read = rt73usb_read_csr,
256 .write = rt73usb_write_csr,
257 .word_size = sizeof(u32),
258 .word_count = CSR_REG_SIZE / sizeof(u32),
261 .read = rt2x00_eeprom_read,
262 .write = rt2x00_eeprom_write,
263 .word_size = sizeof(u16),
264 .word_count = EEPROM_SIZE / sizeof(u16),
267 .read = rt73usb_bbp_read,
268 .write = rt73usb_bbp_write,
269 .word_size = sizeof(u8),
270 .word_count = BBP_SIZE / sizeof(u8),
273 .read = rt2x00_rf_read,
274 .write = rt73usb_rf_write,
275 .word_size = sizeof(u32),
276 .word_count = RF_SIZE / sizeof(u32),
279 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
281 #ifdef CONFIG_RT73USB_LEDS
282 static void rt73usb_led_brightness(struct led_classdev *led_cdev,
283 enum led_brightness brightness)
285 struct rt2x00_led *led =
286 container_of(led_cdev, struct rt2x00_led, led_dev);
287 unsigned int enabled = brightness != LED_OFF;
288 unsigned int a_mode =
289 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
290 unsigned int bg_mode =
291 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
294 NOTICE(led->rt2x00dev,
295 "Ignoring LED brightness command for led %d", led->type);
299 if (led->type == LED_TYPE_RADIO) {
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_RADIO_STATUS, enabled);
303 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
304 0, led->rt2x00dev->led_mcu_reg,
306 } else if (led->type == LED_TYPE_ASSOC) {
307 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
308 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
309 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
310 MCU_LEDCS_LINK_A_STATUS, a_mode);
312 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
313 0, led->rt2x00dev->led_mcu_reg,
315 } else if (led->type == LED_TYPE_QUALITY) {
317 * The brightness is divided into 6 levels (0 - 5),
318 * this means we need to convert the brightness
319 * argument into the matching level within that range.
321 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
322 brightness / (LED_FULL / 6),
323 led->rt2x00dev->led_mcu_reg,
328 #define rt73usb_led_brightness NULL
329 #endif /* CONFIG_RT73USB_LEDS */
332 * Configuration handlers.
334 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
335 struct rt2x00_intf *intf,
336 struct rt2x00intf_conf *conf,
337 const unsigned int flags)
339 unsigned int beacon_base;
342 if (flags & CONFIG_UPDATE_TYPE) {
344 * Clear current synchronisation setup.
345 * For the Beacon base registers we only need to clear
346 * the first byte since that byte contains the VALID and OWNER
347 * bits which (when set to 0) will invalidate the entire beacon.
349 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
350 rt73usb_register_write(rt2x00dev, beacon_base, 0);
353 * Enable synchronisation.
355 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
356 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
357 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
360 if (flags & CONFIG_UPDATE_MAC) {
361 reg = le32_to_cpu(conf->mac[1]);
362 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
363 conf->mac[1] = cpu_to_le32(reg);
365 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
366 conf->mac, sizeof(conf->mac));
369 if (flags & CONFIG_UPDATE_BSSID) {
370 reg = le32_to_cpu(conf->bssid[1]);
371 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
372 conf->bssid[1] = cpu_to_le32(reg);
374 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
375 conf->bssid, sizeof(conf->bssid));
379 static int rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
380 const int short_preamble,
381 const int ack_timeout,
382 const int ack_consume_time)
387 * When in atomic context, we should let rt2x00lib
388 * try this configuration again later.
393 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
394 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
395 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
397 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
398 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
400 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
405 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
406 const int basic_rate_mask)
408 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
411 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
412 struct rf_channel *rf, const int txpower)
418 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
419 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
421 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
422 rt2x00_rf(&rt2x00dev->chip, RF2527));
424 rt73usb_bbp_read(rt2x00dev, 3, &r3);
425 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
426 rt73usb_bbp_write(rt2x00dev, 3, r3);
429 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
430 r94 += txpower - MAX_TXPOWER;
431 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
433 rt73usb_bbp_write(rt2x00dev, 94, r94);
435 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
436 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
437 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
438 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
440 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
441 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
442 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
443 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
445 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
446 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
447 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
448 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
453 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
456 struct rf_channel rf;
458 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
459 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
460 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
461 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
463 rt73usb_config_channel(rt2x00dev, &rf, txpower);
466 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
467 struct antenna_setup *ant)
474 rt73usb_bbp_read(rt2x00dev, 3, &r3);
475 rt73usb_bbp_read(rt2x00dev, 4, &r4);
476 rt73usb_bbp_read(rt2x00dev, 77, &r77);
478 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
481 * Configure the RX antenna.
484 case ANTENNA_HW_DIVERSITY:
485 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
486 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
487 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
488 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
491 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
492 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
493 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
494 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
496 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
498 case ANTENNA_SW_DIVERSITY:
500 * NOTE: We should never come here because rt2x00lib is
501 * supposed to catch this and send us the correct antenna
502 * explicitely. However we are nog going to bug about this.
503 * Instead, just default to antenna B.
506 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
507 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
508 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
509 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
511 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
515 rt73usb_bbp_write(rt2x00dev, 77, r77);
516 rt73usb_bbp_write(rt2x00dev, 3, r3);
517 rt73usb_bbp_write(rt2x00dev, 4, r4);
520 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
521 struct antenna_setup *ant)
527 rt73usb_bbp_read(rt2x00dev, 3, &r3);
528 rt73usb_bbp_read(rt2x00dev, 4, &r4);
529 rt73usb_bbp_read(rt2x00dev, 77, &r77);
531 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
532 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
533 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
536 * Configure the RX antenna.
539 case ANTENNA_HW_DIVERSITY:
540 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
543 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
544 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
546 case ANTENNA_SW_DIVERSITY:
548 * NOTE: We should never come here because rt2x00lib is
549 * supposed to catch this and send us the correct antenna
550 * explicitely. However we are nog going to bug about this.
551 * Instead, just default to antenna B.
554 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
555 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
559 rt73usb_bbp_write(rt2x00dev, 77, r77);
560 rt73usb_bbp_write(rt2x00dev, 3, r3);
561 rt73usb_bbp_write(rt2x00dev, 4, r4);
567 * value[0] -> non-LNA
573 static const struct antenna_sel antenna_sel_a[] = {
574 { 96, { 0x58, 0x78 } },
575 { 104, { 0x38, 0x48 } },
576 { 75, { 0xfe, 0x80 } },
577 { 86, { 0xfe, 0x80 } },
578 { 88, { 0xfe, 0x80 } },
579 { 35, { 0x60, 0x60 } },
580 { 97, { 0x58, 0x58 } },
581 { 98, { 0x58, 0x58 } },
584 static const struct antenna_sel antenna_sel_bg[] = {
585 { 96, { 0x48, 0x68 } },
586 { 104, { 0x2c, 0x3c } },
587 { 75, { 0xfe, 0x80 } },
588 { 86, { 0xfe, 0x80 } },
589 { 88, { 0xfe, 0x80 } },
590 { 35, { 0x50, 0x50 } },
591 { 97, { 0x48, 0x48 } },
592 { 98, { 0x48, 0x48 } },
595 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
596 struct antenna_setup *ant)
598 const struct antenna_sel *sel;
603 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
605 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
607 sel = antenna_sel_bg;
608 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
611 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
612 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
614 rt73usb_register_read(rt2x00dev, PHY_CSR0, ®);
616 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
617 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
618 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
619 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
621 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
623 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
624 rt2x00_rf(&rt2x00dev->chip, RF5225))
625 rt73usb_config_antenna_5x(rt2x00dev, ant);
626 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
627 rt2x00_rf(&rt2x00dev->chip, RF2527))
628 rt73usb_config_antenna_2x(rt2x00dev, ant);
631 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
632 struct rt2x00lib_conf *libconf)
636 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
637 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
638 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
640 rt73usb_register_read(rt2x00dev, MAC_CSR8, ®);
641 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
642 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
643 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
644 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
646 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
647 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
648 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
650 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
651 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
652 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
654 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
655 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
656 libconf->conf->beacon_int * 16);
657 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
660 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
661 struct rt2x00lib_conf *libconf,
662 const unsigned int flags)
664 if (flags & CONFIG_UPDATE_PHYMODE)
665 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
666 if (flags & CONFIG_UPDATE_CHANNEL)
667 rt73usb_config_channel(rt2x00dev, &libconf->rf,
668 libconf->conf->power_level);
669 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
670 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
671 if (flags & CONFIG_UPDATE_ANTENNA)
672 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
673 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
674 rt73usb_config_duration(rt2x00dev, libconf);
680 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
681 struct link_qual *qual)
686 * Update FCS error count from register.
688 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
689 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
692 * Update False CCA count from register.
694 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
695 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
698 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
700 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
701 rt2x00dev->link.vgc_level = 0x20;
704 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
706 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
711 rt73usb_bbp_read(rt2x00dev, 17, &r17);
714 * Determine r17 bounds.
716 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
720 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
728 } else if (rssi > -84) {
736 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
743 * If we are not associated, we should go straight to the
744 * dynamic CCA tuning.
746 if (!rt2x00dev->intf_associated)
747 goto dynamic_cca_tune;
750 * Special big-R17 for very short distance
754 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
759 * Special big-R17 for short distance
763 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
768 * Special big-R17 for middle-short distance
772 if (r17 != low_bound)
773 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
778 * Special mid-R17 for middle distance
781 if (r17 != (low_bound + 0x10))
782 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
787 * Special case: Change up_bound based on the rssi.
788 * Lower up_bound when rssi is weaker then -74 dBm.
790 up_bound -= 2 * (-74 - rssi);
791 if (low_bound > up_bound)
792 up_bound = low_bound;
794 if (r17 > up_bound) {
795 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
802 * r17 does not yet exceed upper limit, continue and base
803 * the r17 tuning on the false CCA count.
805 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
809 rt73usb_bbp_write(rt2x00dev, 17, r17);
810 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
814 rt73usb_bbp_write(rt2x00dev, 17, r17);
819 * Firmware name function.
821 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
823 return FIRMWARE_RT2571;
827 * Initialization functions.
829 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
841 * Wait for stable hardware.
843 for (i = 0; i < 100; i++) {
844 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
851 ERROR(rt2x00dev, "Unstable hardware.\n");
856 * Write firmware to device.
857 * We setup a seperate cache for this action,
858 * since we are going to write larger chunks of data
859 * then normally used cache size.
861 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
863 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
867 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
868 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
869 timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
871 memcpy(cache, ptr, buflen);
873 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
874 USB_VENDOR_REQUEST_OUT,
875 FIRMWARE_IMAGE_BASE + i, 0,
876 cache, buflen, timeout);
884 * Send firmware request to device to load firmware,
885 * we need to specify a long timeout time.
887 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
888 0, USB_MODE_FIRMWARE,
889 REGISTER_TIMEOUT_FIRMWARE);
891 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
898 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
902 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
903 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
904 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
905 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
906 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
908 rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®);
909 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
910 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
911 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
912 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
913 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
914 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
915 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
916 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
917 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
920 * CCK TXD BBP registers
922 rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®);
923 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
924 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
925 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
926 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
927 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
928 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
929 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
930 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
931 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
934 * OFDM TXD BBP registers
936 rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®);
937 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
938 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
939 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
940 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
941 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
942 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
943 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
945 rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®);
946 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
947 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
948 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
949 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
950 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
952 rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®);
953 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
954 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
955 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
956 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
957 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
959 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
961 rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
962 rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
963 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
965 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
967 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
970 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
972 rt73usb_register_read(rt2x00dev, MAC_CSR14, ®);
973 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
974 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
975 rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
978 * Invalidate all Shared Keys (SEC_CSR0),
979 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
981 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
982 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
983 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
986 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
987 rt2x00_rf(&rt2x00dev->chip, RF2527))
988 rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
989 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
991 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
992 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
993 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
995 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
996 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
997 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
998 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1000 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1001 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1002 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1003 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1005 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
1006 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1007 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1011 * For the Beacon base registers we only need to clear
1012 * the first byte since that byte contains the VALID and OWNER
1013 * bits which (when set to 0) will invalidate the entire beacon.
1015 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1016 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1017 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1018 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1021 * We must clear the error counters.
1022 * These registers are cleared on read,
1023 * so we may pass a useless variable to store the value.
1025 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
1026 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
1027 rt73usb_register_read(rt2x00dev, STA_CSR2, ®);
1030 * Reset MAC and BBP registers.
1032 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1033 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1034 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1035 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1037 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1038 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1039 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1040 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1042 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1043 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1044 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1049 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1056 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1057 rt73usb_bbp_read(rt2x00dev, 0, &value);
1058 if ((value != 0xff) && (value != 0x00))
1059 goto continue_csr_init;
1060 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1061 udelay(REGISTER_BUSY_DELAY);
1064 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1068 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1069 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1070 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1071 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1072 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1073 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1074 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1075 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1076 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1077 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1078 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1079 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1080 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1081 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1082 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1083 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1084 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1085 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1086 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1087 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1088 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1089 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1090 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1091 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1092 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1094 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1095 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1097 if (eeprom != 0xffff && eeprom != 0x0000) {
1098 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1099 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1100 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1108 * Device state switch handlers.
1110 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1111 enum dev_state state)
1115 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1116 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1117 state == STATE_RADIO_RX_OFF);
1118 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1121 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1124 * Initialize all registers.
1126 if (rt73usb_init_registers(rt2x00dev) ||
1127 rt73usb_init_bbp(rt2x00dev)) {
1128 ERROR(rt2x00dev, "Register initialization failed.\n");
1135 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1137 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1140 * Disable synchronisation.
1142 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1144 rt2x00usb_disable_radio(rt2x00dev);
1147 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1154 put_to_sleep = (state != STATE_AWAKE);
1156 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1157 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1158 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1159 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1162 * Device is not guaranteed to be in the requested state yet.
1163 * We must wait until the register indicates that the
1164 * device has entered the correct state.
1166 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1167 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1169 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1170 if (current_state == !put_to_sleep)
1175 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1176 "current device state %d.\n", !put_to_sleep, current_state);
1181 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1182 enum dev_state state)
1187 case STATE_RADIO_ON:
1188 retval = rt73usb_enable_radio(rt2x00dev);
1190 case STATE_RADIO_OFF:
1191 rt73usb_disable_radio(rt2x00dev);
1193 case STATE_RADIO_RX_ON:
1194 case STATE_RADIO_RX_ON_LINK:
1195 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1197 case STATE_RADIO_RX_OFF:
1198 case STATE_RADIO_RX_OFF_LINK:
1199 rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1201 case STATE_DEEP_SLEEP:
1205 retval = rt73usb_set_state(rt2x00dev, state);
1216 * TX descriptor initialization
1218 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1219 struct sk_buff *skb,
1220 struct txentry_desc *txdesc,
1221 struct ieee80211_tx_control *control)
1223 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1224 __le32 *txd = skbdesc->desc;
1228 * Start writing the descriptor words.
1230 rt2x00_desc_read(txd, 1, &word);
1231 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1232 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1233 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1234 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1235 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1236 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1237 rt2x00_desc_write(txd, 1, word);
1239 rt2x00_desc_read(txd, 2, &word);
1240 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1241 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1242 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1243 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1244 rt2x00_desc_write(txd, 2, word);
1246 rt2x00_desc_read(txd, 5, &word);
1247 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1248 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1249 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1250 rt2x00_desc_write(txd, 5, word);
1252 rt2x00_desc_read(txd, 0, &word);
1253 rt2x00_set_field32(&word, TXD_W0_BURST,
1254 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1255 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1256 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1257 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1258 rt2x00_set_field32(&word, TXD_W0_ACK,
1259 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1260 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1261 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1262 rt2x00_set_field32(&word, TXD_W0_OFDM,
1263 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1264 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1265 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1267 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1268 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1269 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1270 rt2x00_set_field32(&word, TXD_W0_BURST2,
1271 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1272 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1273 rt2x00_desc_write(txd, 0, word);
1276 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1277 struct sk_buff *skb)
1282 * The length _must_ be a multiple of 4,
1283 * but it must _not_ be a multiple of the USB packet size.
1285 length = roundup(skb->len, 4);
1286 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1292 * TX data initialization
1294 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1295 const unsigned int queue)
1299 if (queue != RT2X00_BCN_QUEUE_BEACON)
1303 * For Wi-Fi faily generated beacons between participating stations.
1304 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1306 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1308 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
1309 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1310 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1311 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1312 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1313 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1318 * RX control handlers
1320 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1326 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1341 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1342 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1343 if (lna == 3 || lna == 2)
1352 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1353 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1355 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1358 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1359 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1362 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1365 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1366 struct rxdone_entry_desc *rxdesc)
1368 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1369 __le32 *rxd = (__le32 *)entry->skb->data;
1370 unsigned int offset = entry->queue->desc_size + 2;
1375 * Copy descriptor to the available headroom inside the skbuffer.
1377 skb_push(entry->skb, offset);
1378 memcpy(entry->skb->data, rxd, entry->queue->desc_size);
1379 rxd = (__le32 *)entry->skb->data;
1382 * The descriptor is now aligned to 4 bytes and thus it is
1383 * now safe to read it on all architectures.
1385 rt2x00_desc_read(rxd, 0, &word0);
1386 rt2x00_desc_read(rxd, 1, &word1);
1389 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1390 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1393 * Obtain the status about this packet.
1395 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1396 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1397 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1398 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1399 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1402 * Adjust the skb memory window to the frame boundaries.
1404 skb_pull(entry->skb, offset + entry->queue->desc_size);
1405 skb_trim(entry->skb, rxdesc->size);
1408 * Set descriptor and data pointer.
1410 skbdesc->data = entry->skb->data;
1411 skbdesc->data_len = rxdesc->size;
1412 skbdesc->desc = rxd;
1413 skbdesc->desc_len = entry->queue->desc_size;
1417 * Device probe functions.
1419 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1425 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1428 * Start validation of the data that has been read.
1430 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1431 if (!is_valid_ether_addr(mac)) {
1432 DECLARE_MAC_BUF(macbuf);
1434 random_ether_addr(mac);
1435 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1438 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1439 if (word == 0xffff) {
1440 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1441 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1443 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1445 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1446 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1447 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1448 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1449 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1450 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1453 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1454 if (word == 0xffff) {
1455 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1456 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1457 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1460 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1461 if (word == 0xffff) {
1462 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1463 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1464 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1465 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1466 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1467 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1468 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1469 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1470 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1472 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1473 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1476 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1477 if (word == 0xffff) {
1478 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1479 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1480 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1481 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1484 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1485 if (word == 0xffff) {
1486 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1487 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1488 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1489 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1491 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1492 if (value < -10 || value > 10)
1493 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1494 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1495 if (value < -10 || value > 10)
1496 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1497 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1500 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1501 if (word == 0xffff) {
1502 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1503 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1504 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1505 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1507 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1508 if (value < -10 || value > 10)
1509 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1510 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1511 if (value < -10 || value > 10)
1512 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1513 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1519 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1526 * Read EEPROM word for configuration.
1528 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1531 * Identify RF chipset.
1533 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1534 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
1535 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1537 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1538 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1542 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1543 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1544 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1545 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1546 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1551 * Identify default antenna configuration.
1553 rt2x00dev->default_ant.tx =
1554 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1555 rt2x00dev->default_ant.rx =
1556 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1559 * Read the Frame type.
1561 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1562 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1565 * Read frequency offset.
1567 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1568 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1571 * Read external LNA informations.
1573 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1575 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1576 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1577 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1581 * Store led settings, for correct led behaviour.
1583 #ifdef CONFIG_RT73USB_LEDS
1584 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1587 case LED_MODE_TXRX_ACTIVITY:
1589 case LED_MODE_ALPHA:
1590 case LED_MODE_DEFAULT:
1591 rt2x00dev->led_flags =
1592 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
1594 case LED_MODE_SIGNAL_STRENGTH:
1595 rt2x00dev->led_flags =
1596 LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
1597 LED_SUPPORT_QUALITY;
1601 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1602 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1603 rt2x00_get_field16(eeprom,
1604 EEPROM_LED_POLARITY_GPIO_0));
1605 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1606 rt2x00_get_field16(eeprom,
1607 EEPROM_LED_POLARITY_GPIO_1));
1608 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1609 rt2x00_get_field16(eeprom,
1610 EEPROM_LED_POLARITY_GPIO_2));
1611 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1612 rt2x00_get_field16(eeprom,
1613 EEPROM_LED_POLARITY_GPIO_3));
1614 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1615 rt2x00_get_field16(eeprom,
1616 EEPROM_LED_POLARITY_GPIO_4));
1617 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1618 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1619 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1620 rt2x00_get_field16(eeprom,
1621 EEPROM_LED_POLARITY_RDY_G));
1622 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1623 rt2x00_get_field16(eeprom,
1624 EEPROM_LED_POLARITY_RDY_A));
1625 #endif /* CONFIG_RT73USB_LEDS */
1631 * RF value list for RF2528
1634 static const struct rf_channel rf_vals_bg_2528[] = {
1635 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1636 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1637 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1638 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1639 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1640 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1641 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1642 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1643 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1644 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1645 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1646 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1647 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1648 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1652 * RF value list for RF5226
1653 * Supports: 2.4 GHz & 5.2 GHz
1655 static const struct rf_channel rf_vals_5226[] = {
1656 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1657 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1658 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1659 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1660 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1661 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1662 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1663 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1664 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1665 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1666 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1667 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1668 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1669 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1671 /* 802.11 UNI / HyperLan 2 */
1672 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1673 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1674 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1675 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1676 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1677 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1678 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1679 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1681 /* 802.11 HyperLan 2 */
1682 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1683 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1684 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1685 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1686 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1687 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1688 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1689 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1690 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1691 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1694 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1695 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1696 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1697 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1698 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1699 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1701 /* MMAC(Japan)J52 ch 34,38,42,46 */
1702 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1703 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1704 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1705 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1709 * RF value list for RF5225 & RF2527
1710 * Supports: 2.4 GHz & 5.2 GHz
1712 static const struct rf_channel rf_vals_5225_2527[] = {
1713 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1714 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1715 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1716 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1717 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1718 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1719 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1720 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1721 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1722 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1723 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1724 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1725 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1726 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1728 /* 802.11 UNI / HyperLan 2 */
1729 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1730 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1731 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1732 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1733 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1734 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1735 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1736 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1738 /* 802.11 HyperLan 2 */
1739 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1740 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1741 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1742 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1743 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1744 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1745 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1746 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1747 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1748 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1751 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1752 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1753 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1754 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1755 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1756 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1758 /* MMAC(Japan)J52 ch 34,38,42,46 */
1759 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1760 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1761 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1762 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1766 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1768 struct hw_mode_spec *spec = &rt2x00dev->spec;
1773 * Initialize all hw fields.
1775 rt2x00dev->hw->flags =
1776 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1777 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1778 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1779 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1780 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1781 rt2x00dev->hw->queues = 4;
1783 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1784 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1785 rt2x00_eeprom_addr(rt2x00dev,
1786 EEPROM_MAC_ADDR_0));
1789 * Convert tx_power array in eeprom.
1791 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1792 for (i = 0; i < 14; i++)
1793 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1796 * Initialize hw_mode information.
1798 spec->supported_bands = SUPPORT_BAND_2GHZ;
1799 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1800 spec->tx_power_a = NULL;
1801 spec->tx_power_bg = txpower;
1802 spec->tx_power_default = DEFAULT_TXPOWER;
1804 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1805 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1806 spec->channels = rf_vals_bg_2528;
1807 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1808 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1809 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1810 spec->channels = rf_vals_5226;
1811 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1812 spec->num_channels = 14;
1813 spec->channels = rf_vals_5225_2527;
1814 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1815 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1816 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1817 spec->channels = rf_vals_5225_2527;
1820 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1821 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1822 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1823 for (i = 0; i < 14; i++)
1824 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1826 spec->tx_power_a = txpower;
1830 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1835 * Allocate eeprom data.
1837 retval = rt73usb_validate_eeprom(rt2x00dev);
1841 retval = rt73usb_init_eeprom(rt2x00dev);
1846 * Initialize hw specifications.
1848 rt73usb_probe_hw_mode(rt2x00dev);
1851 * This device requires firmware.
1853 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1854 __set_bit(DRIVER_REQUIRE_FIRMWARE_CRC_ITU_T, &rt2x00dev->flags);
1857 * Set the rssi offset.
1859 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1865 * IEEE80211 stack callback functions.
1867 static void rt73usb_configure_filter(struct ieee80211_hw *hw,
1868 unsigned int changed_flags,
1869 unsigned int *total_flags,
1871 struct dev_addr_list *mc_list)
1873 struct rt2x00_dev *rt2x00dev = hw->priv;
1877 * Mask off any flags we are going to ignore from
1878 * the total_flags field.
1889 * Apply some rules to the filters:
1890 * - Some filters imply different filters to be set.
1891 * - Some things we can't filter out at all.
1894 *total_flags |= FIF_ALLMULTI;
1895 if (*total_flags & FIF_OTHER_BSS ||
1896 *total_flags & FIF_PROMISC_IN_BSS)
1897 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1900 * Check if there is any work left for us.
1902 if (rt2x00dev->packet_filter == *total_flags)
1904 rt2x00dev->packet_filter = *total_flags;
1907 * When in atomic context, reschedule and let rt2x00lib
1908 * call this function again.
1911 queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
1916 * Start configuration steps.
1917 * Note that the version error will always be dropped
1918 * and broadcast frames will always be accepted since
1919 * there is no filter for it at this time.
1921 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1922 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
1923 !(*total_flags & FIF_FCSFAIL));
1924 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
1925 !(*total_flags & FIF_PLCPFAIL));
1926 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
1927 !(*total_flags & FIF_CONTROL));
1928 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
1929 !(*total_flags & FIF_PROMISC_IN_BSS));
1930 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
1931 !(*total_flags & FIF_PROMISC_IN_BSS));
1932 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
1933 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
1934 !(*total_flags & FIF_ALLMULTI));
1935 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
1936 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
1937 !(*total_flags & FIF_CONTROL));
1938 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1941 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1942 u32 short_retry, u32 long_retry)
1944 struct rt2x00_dev *rt2x00dev = hw->priv;
1947 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
1948 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1949 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1950 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1957 * Mac80211 demands get_tsf must be atomic.
1958 * This is not possible for rt73usb since all register access
1959 * functions require sleeping. Untill mac80211 no longer needs
1960 * get_tsf to be atomic, this function should be disabled.
1962 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1964 struct rt2x00_dev *rt2x00dev = hw->priv;
1968 rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®);
1969 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1970 rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®);
1971 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1976 #define rt73usb_get_tsf NULL
1979 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1980 struct ieee80211_tx_control *control)
1982 struct rt2x00_dev *rt2x00dev = hw->priv;
1983 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1984 struct skb_frame_desc *skbdesc;
1985 unsigned int beacon_base;
1986 unsigned int timeout;
1989 if (unlikely(!intf->beacon))
1993 * Add the descriptor in front of the skb.
1995 skb_push(skb, intf->beacon->queue->desc_size);
1996 memset(skb->data, 0, intf->beacon->queue->desc_size);
1999 * Fill in skb descriptor
2001 skbdesc = get_skb_frame_desc(skb);
2002 memset(skbdesc, 0, sizeof(*skbdesc));
2003 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2004 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2005 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2006 skbdesc->desc = skb->data;
2007 skbdesc->desc_len = intf->beacon->queue->desc_size;
2008 skbdesc->entry = intf->beacon;
2011 * Disable beaconing while we are reloading the beacon data,
2012 * otherwise we might be sending out invalid data.
2014 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
2015 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
2016 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
2017 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
2018 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2021 * mac80211 doesn't provide the control->queue variable
2022 * for beacons. Set our own queue identification so
2023 * it can be used during descriptor initialization.
2025 control->queue = RT2X00_BCN_QUEUE_BEACON;
2026 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2029 * Write entire beacon with descriptor to register,
2030 * and kick the beacon generator.
2032 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2033 timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
2034 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2035 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
2036 skb->data, skb->len, timeout);
2037 rt73usb_kick_tx_queue(rt2x00dev, control->queue);
2042 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2044 .start = rt2x00mac_start,
2045 .stop = rt2x00mac_stop,
2046 .add_interface = rt2x00mac_add_interface,
2047 .remove_interface = rt2x00mac_remove_interface,
2048 .config = rt2x00mac_config,
2049 .config_interface = rt2x00mac_config_interface,
2050 .configure_filter = rt73usb_configure_filter,
2051 .get_stats = rt2x00mac_get_stats,
2052 .set_retry_limit = rt73usb_set_retry_limit,
2053 .bss_info_changed = rt2x00mac_bss_info_changed,
2054 .conf_tx = rt2x00mac_conf_tx,
2055 .get_tx_stats = rt2x00mac_get_tx_stats,
2056 .get_tsf = rt73usb_get_tsf,
2057 .beacon_update = rt73usb_beacon_update,
2060 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2061 .probe_hw = rt73usb_probe_hw,
2062 .get_firmware_name = rt73usb_get_firmware_name,
2063 .load_firmware = rt73usb_load_firmware,
2064 .initialize = rt2x00usb_initialize,
2065 .uninitialize = rt2x00usb_uninitialize,
2066 .init_rxentry = rt2x00usb_init_rxentry,
2067 .init_txentry = rt2x00usb_init_txentry,
2068 .set_device_state = rt73usb_set_device_state,
2069 .link_stats = rt73usb_link_stats,
2070 .reset_tuner = rt73usb_reset_tuner,
2071 .link_tuner = rt73usb_link_tuner,
2072 .led_brightness = rt73usb_led_brightness,
2073 .write_tx_desc = rt73usb_write_tx_desc,
2074 .write_tx_data = rt2x00usb_write_tx_data,
2075 .get_tx_data_len = rt73usb_get_tx_data_len,
2076 .kick_tx_queue = rt73usb_kick_tx_queue,
2077 .fill_rxdone = rt73usb_fill_rxdone,
2078 .config_intf = rt73usb_config_intf,
2079 .config_preamble = rt73usb_config_preamble,
2080 .config = rt73usb_config,
2083 static const struct data_queue_desc rt73usb_queue_rx = {
2084 .entry_num = RX_ENTRIES,
2085 .data_size = DATA_FRAME_SIZE,
2086 .desc_size = RXD_DESC_SIZE,
2087 .priv_size = sizeof(struct queue_entry_priv_usb_rx),
2090 static const struct data_queue_desc rt73usb_queue_tx = {
2091 .entry_num = TX_ENTRIES,
2092 .data_size = DATA_FRAME_SIZE,
2093 .desc_size = TXD_DESC_SIZE,
2094 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2097 static const struct data_queue_desc rt73usb_queue_bcn = {
2098 .entry_num = 4 * BEACON_ENTRIES,
2099 .data_size = MGMT_FRAME_SIZE,
2100 .desc_size = TXINFO_SIZE,
2101 .priv_size = sizeof(struct queue_entry_priv_usb_tx),
2104 static const struct rt2x00_ops rt73usb_ops = {
2105 .name = KBUILD_MODNAME,
2108 .eeprom_size = EEPROM_SIZE,
2110 .rx = &rt73usb_queue_rx,
2111 .tx = &rt73usb_queue_tx,
2112 .bcn = &rt73usb_queue_bcn,
2113 .lib = &rt73usb_rt2x00_ops,
2114 .hw = &rt73usb_mac80211_ops,
2115 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2116 .debugfs = &rt73usb_rt2x00debug,
2117 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2121 * rt73usb module information.
2123 static struct usb_device_id rt73usb_device_table[] = {
2125 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2127 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2129 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2130 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2132 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2133 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2134 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2135 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2137 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2139 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2141 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2142 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2144 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2146 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2147 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2149 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2151 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2152 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2154 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2156 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2157 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2159 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2160 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2162 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2163 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2164 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2165 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2167 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2168 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2170 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2171 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2172 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2174 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2176 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2177 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2179 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2181 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2182 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2186 MODULE_AUTHOR(DRV_PROJECT);
2187 MODULE_VERSION(DRV_VERSION);
2188 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2189 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2190 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2191 MODULE_FIRMWARE(FIRMWARE_RT2571);
2192 MODULE_LICENSE("GPL");
2194 static struct usb_driver rt73usb_driver = {
2195 .name = KBUILD_MODNAME,
2196 .id_table = rt73usb_device_table,
2197 .probe = rt2x00usb_probe,
2198 .disconnect = rt2x00usb_disconnect,
2199 .suspend = rt2x00usb_suspend,
2200 .resume = rt2x00usb_resume,
2203 static int __init rt73usb_init(void)
2205 return usb_register(&rt73usb_driver);
2208 static void __exit rt73usb_exit(void)
2210 usb_deregister(&rt73usb_driver);
2213 module_init(rt73usb_init);
2214 module_exit(rt73usb_exit);