1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
36 #include <linux/export.h>
37 #include <linux/kmemleak.h>
39 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
46 static const u8 ac_to_hwq[] = {
53 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
56 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
57 __le16 fc = rtl_get_fc(skb);
58 u8 queue_index = skb_get_queue_mapping(skb);
60 if (unlikely(ieee80211_is_beacon(fc)))
62 if (ieee80211_is_mgmt(fc))
64 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
65 if (ieee80211_is_nullfunc(fc))
68 return ac_to_hwq[queue_index];
71 /* Update PCI dependent default settings*/
72 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
76 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
77 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
81 ppsc->reg_rfps_level = 0;
82 ppsc->support_aspm = false;
84 /*Update PCI ASPM setting */
85 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
86 switch (rtlpci->const_pci_aspm) {
92 /*ASPM dynamically enabled/disable. */
93 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
97 /*ASPM with Clock Req dynamically enabled/disable. */
98 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
99 RT_RF_OFF_LEVL_CLK_REQ);
104 * Always enable ASPM and Clock Req
105 * from initialization to halt.
107 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
108 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
109 RT_RF_OFF_LEVL_CLK_REQ);
114 * Always enable ASPM without Clock Req
115 * from initialization to halt.
117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
118 RT_RF_OFF_LEVL_CLK_REQ);
119 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
123 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
125 /*Update Radio OFF setting */
126 switch (rtlpci->const_hwsw_rfoff_d3) {
128 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
129 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
133 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
143 /*Set HW definition to determine if it supports ASPM. */
144 switch (rtlpci->const_support_pciaspm) {
146 /*Not support ASPM. */
147 bool support_aspm = false;
148 ppsc->support_aspm = support_aspm;
153 bool support_aspm = true;
154 bool support_backdoor = true;
155 ppsc->support_aspm = support_aspm;
157 /*if (priv->oem_id == RT_CID_TOSHIBA &&
158 !priv->ndis_adapter.amd_l1_patch)
159 support_backdoor = false; */
161 ppsc->support_backdoor = support_backdoor;
166 /*ASPM value set by chipset. */
167 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
168 bool support_aspm = true;
169 ppsc->support_aspm = support_aspm;
173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
174 "switch case not processed\n");
178 /* toshiba aspm issue, toshiba will set aspm selfly
179 * so we should not set aspm in driver */
180 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
181 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
183 ppsc->support_aspm = false;
186 static bool _rtl_pci_platform_switch_device_pci_aspm(
187 struct ieee80211_hw *hw,
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
193 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
196 pci_write_config_byte(rtlpci->pdev, 0x80, value);
201 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
202 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
207 pci_write_config_byte(rtlpci->pdev, 0x81, value);
209 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
213 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
222 /*Retrieve original configuration settings. */
223 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
224 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
225 pcibridge_linkctrlreg;
229 if (!ppsc->support_aspm)
232 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
233 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
234 "PCI(Bridge) UNKNOWN\n");
239 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
240 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
241 _rtl_pci_switch_clk_req(hw, 0x0);
244 /*for promising device will in L0 state after an I/O. */
245 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
247 /*Set corresponding value. */
248 aspmlevel |= BIT(0) | BIT(1);
249 linkctrl_reg &= ~aspmlevel;
250 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
255 /*4 Disable Pci Bridge ASPM */
256 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
257 pcibridge_linkctrlreg);
263 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
264 *power saving We should follow the sequence to enable
265 *RTL8192SE first then enable Pci Bridge ASPM
266 *or the system will show bluescreen.
268 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
274 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
275 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
276 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
277 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
278 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
280 u8 u_pcibridge_aspmsetting;
281 u8 u_device_aspmsetting;
283 if (!ppsc->support_aspm)
286 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
287 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
288 "PCI(Bridge) UNKNOWN\n");
292 /*4 Enable Pci Bridge ASPM */
294 u_pcibridge_aspmsetting =
295 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
296 rtlpci->const_hostpci_aspm_setting;
298 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
299 u_pcibridge_aspmsetting &= ~BIT(0);
301 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
302 u_pcibridge_aspmsetting);
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
305 "PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
306 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
308 u_pcibridge_aspmsetting);
312 /*Get ASPM level (with/without Clock Req) */
313 aspmlevel = rtlpci->const_devicepci_aspm_setting;
314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
319 u_device_aspmsetting |= aspmlevel;
321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
331 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
333 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
339 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
341 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
343 if (offset_e0 == 0xA0) {
344 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
345 if (offset_e4 & BIT(23))
352 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
354 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
355 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
356 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
360 num4bbytes = (capabilityoffset + 0x10) / 4;
362 /*Read Link Control Register */
363 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
365 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
368 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
369 struct ieee80211_hw *hw)
371 struct rtl_priv *rtlpriv = rtl_priv(hw);
372 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
377 /*Link Control Register */
378 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
379 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
381 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
382 pcipriv->ndis_adapter.linkctrl_reg);
384 pci_read_config_byte(pdev, 0x98, &tmp);
386 pci_write_config_byte(pdev, 0x98, tmp);
389 pci_write_config_byte(pdev, 0x70f, tmp);
392 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
394 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
396 _rtl_pci_update_default_setting(hw);
398 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
399 /*Always enable ASPM & Clock Req. */
400 rtl_pci_enable_aspm(hw);
401 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
406 static void _rtl_pci_io_handler_init(struct device *dev,
407 struct ieee80211_hw *hw)
409 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 rtlpriv->io.dev = dev;
413 rtlpriv->io.write8_async = pci_write8_async;
414 rtlpriv->io.write16_async = pci_write16_async;
415 rtlpriv->io.write32_async = pci_write32_async;
417 rtlpriv->io.read8_sync = pci_read8_sync;
418 rtlpriv->io.read16_sync = pci_read16_sync;
419 rtlpriv->io.read32_sync = pci_read32_sync;
423 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
427 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
428 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
430 struct rtl_priv *rtlpriv = rtl_priv(hw);
431 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
432 u8 additionlen = FCS_LEN;
433 struct sk_buff *next_skb;
435 /* here open is 4, wep/tkip is 8, aes is 12*/
436 if (info->control.hw_key)
437 additionlen += info->control.hw_key->icv_len;
439 /* The most skb num is 6 */
440 tcb_desc->empkt_num = 0;
441 spin_lock_bh(&rtlpriv->locks.waitq_lock);
442 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
443 struct ieee80211_tx_info *next_info;
445 next_info = IEEE80211_SKB_CB(next_skb);
446 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
447 tcb_desc->empkt_len[tcb_desc->empkt_num] =
448 next_skb->len + additionlen;
449 tcb_desc->empkt_num++;
454 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
458 if (tcb_desc->empkt_num >= 5)
461 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
466 /* just for early mode now */
467 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
469 struct rtl_priv *rtlpriv = rtl_priv(hw);
470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
471 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
472 struct sk_buff *skb = NULL;
473 struct ieee80211_tx_info *info = NULL;
476 if (!rtlpriv->rtlhal.earlymode_enable)
479 /* we juse use em for BE/BK/VI/VO */
480 for (tid = 7; tid >= 0; tid--) {
481 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
482 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
483 while (!mac->act_scanning &&
484 rtlpriv->psc.rfpwr_state == ERFON) {
485 struct rtl_tcb_desc tcb_desc;
486 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
488 spin_lock_bh(&rtlpriv->locks.waitq_lock);
489 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
490 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
491 skb = skb_dequeue(&mac->skb_waitq[tid]);
493 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
496 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
498 /* Some macaddr can't do early mode. like
499 * multicast/broadcast/no_qos data */
500 info = IEEE80211_SKB_CB(skb);
501 if (info->flags & IEEE80211_TX_CTL_AMPDU)
502 _rtl_update_earlymode_info(hw, skb,
505 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
511 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
516 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
518 while (skb_queue_len(&ring->queue)) {
519 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
521 struct ieee80211_tx_info *info;
525 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
529 *beacon packet will only use the first
530 *descriptor defautly,and the own may not
531 *be cleared by the hardware
535 ring->idx = (ring->idx + 1) % ring->entries;
537 skb = __skb_dequeue(&ring->queue);
538 pci_unmap_single(rtlpci->pdev,
540 get_desc((u8 *) entry, true,
541 HW_DESC_TXBUFF_ADDR),
542 skb->len, PCI_DMA_TODEVICE);
544 /* remove early mode header */
545 if (rtlpriv->rtlhal.earlymode_enable)
546 skb_pull(skb, EM_HDR_LEN);
548 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
549 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
551 skb_queue_len(&ring->queue),
552 *(u16 *) (skb->data + 22));
554 if (prio == TXCMD_QUEUE) {
560 /* for sw LPS, just after NULL skb send out, we can
561 * sure AP kown we are sleeped, our we should not let
563 fc = rtl_get_fc(skb);
564 if (ieee80211_is_nullfunc(fc)) {
565 if (ieee80211_has_pm(fc)) {
566 rtlpriv->mac80211.offchan_delay = true;
567 rtlpriv->psc.state_inap = true;
569 rtlpriv->psc.state_inap = false;
573 /* update tid tx pkt num */
574 tid = rtl_get_tid(skb);
576 rtlpriv->link_info.tidtx_inperiod[tid]++;
578 info = IEEE80211_SKB_CB(skb);
579 ieee80211_tx_info_clear_status(info);
581 info->flags |= IEEE80211_TX_STAT_ACK;
582 /*info->status.rates[0].count = 1; */
584 ieee80211_tx_status_irqsafe(hw, skb);
586 if ((ring->entries - skb_queue_len(&ring->queue))
589 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
590 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
592 skb_queue_len(&ring->queue));
594 ieee80211_wake_queue(hw,
595 skb_get_queue_mapping
602 if (((rtlpriv->link_info.num_rx_inperiod +
603 rtlpriv->link_info.num_tx_inperiod) > 8) ||
604 (rtlpriv->link_info.num_rx_inperiod > 2)) {
605 schedule_work(&rtlpriv->works.lps_leave_work);
609 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
610 struct ieee80211_rx_status rx_status)
612 struct rtl_priv *rtlpriv = rtl_priv(hw);
613 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
614 __le16 fc = rtl_get_fc(skb);
615 bool unicast = false;
616 struct sk_buff *uskb = NULL;
620 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
622 if (is_broadcast_ether_addr(hdr->addr1)) {
624 } else if (is_multicast_ether_addr(hdr->addr1)) {
628 rtlpriv->stats.rxbytesunicast += skb->len;
631 rtl_is_special_data(hw, skb, false);
633 if (ieee80211_is_data(fc)) {
634 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
637 rtlpriv->link_info.num_rx_inperiod++;
641 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
642 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
643 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
644 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
645 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
648 if (unlikely(!rtl_action_proc(hw, skb, false)))
651 uskb = dev_alloc_skb(skb->len + 128);
653 return; /* exit if allocation failed */
654 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
655 pdata = (u8 *)skb_put(uskb, skb->len);
656 memcpy(pdata, skb->data, skb->len);
658 ieee80211_rx_irqsafe(hw, uskb);
661 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
663 struct rtl_priv *rtlpriv = rtl_priv(hw);
664 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
665 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
667 struct ieee80211_rx_status rx_status = { 0 };
668 unsigned int count = rtlpci->rxringcount;
673 struct rtl_stats stats = {
678 int index = rtlpci->rx_ring[rx_queue_idx].idx;
683 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
686 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
688 struct sk_buff *new_skb = NULL;
690 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
693 /*wait data to be filled by hardware */
697 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
701 if (stats.crc || stats.hwerror)
704 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
705 if (unlikely(!new_skb)) {
706 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
707 "can't alloc skb for rx\n");
711 pci_unmap_single(rtlpci->pdev,
712 *((dma_addr_t *) skb->cb),
713 rtlpci->rxbuffersize,
716 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
718 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
721 * NOTICE This can not be use for mac80211,
722 * this is done in mac80211 code,
723 * if you done here sec DHCP will fail
724 * skb_trim(skb, skb->len - 4);
727 _rtl_receive_one(hw, skb, rx_status);
729 if (((rtlpriv->link_info.num_rx_inperiod +
730 rtlpriv->link_info.num_tx_inperiod) > 8) ||
731 (rtlpriv->link_info.num_rx_inperiod > 2)) {
732 schedule_work(&rtlpriv->works.lps_leave_work);
735 dev_kfree_skb_any(skb);
738 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
739 *((dma_addr_t *) skb->cb) =
740 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
741 rtlpci->rxbuffersize,
745 bufferaddress = (*((dma_addr_t *)skb->cb));
747 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
749 (u8 *)&bufferaddress);
750 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
752 (u8 *)&rtlpci->rxbuffersize);
754 if (index == rtlpci->rxringcount - 1)
755 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
759 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
762 index = (index + 1) % rtlpci->rxringcount;
765 rtlpci->rx_ring[rx_queue_idx].idx = index;
768 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
770 struct ieee80211_hw *hw = dev_id;
771 struct rtl_priv *rtlpriv = rtl_priv(hw);
772 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
776 irqreturn_t ret = IRQ_HANDLED;
778 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
780 /*read ISR: 4/8bytes */
781 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
783 /*Shared IRQ or HW disappared */
784 if (!inta || inta == 0xffff) {
789 /*<1> beacon related */
790 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
791 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
792 "beacon ok interrupt!\n");
795 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
796 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
797 "beacon err interrupt!\n");
800 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
801 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
804 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
805 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
806 "prepare beacon for interrupt!\n");
807 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
811 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
812 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
814 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
815 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
816 "Manage ok interrupt!\n");
817 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
820 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
821 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
822 "HIGH_QUEUE ok interrupt!\n");
823 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
826 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
827 rtlpriv->link_info.num_tx_inperiod++;
829 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
830 "BK Tx OK interrupt!\n");
831 _rtl_pci_tx_isr(hw, BK_QUEUE);
834 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
835 rtlpriv->link_info.num_tx_inperiod++;
837 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
838 "BE TX OK interrupt!\n");
839 _rtl_pci_tx_isr(hw, BE_QUEUE);
842 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
843 rtlpriv->link_info.num_tx_inperiod++;
845 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
846 "VI TX OK interrupt!\n");
847 _rtl_pci_tx_isr(hw, VI_QUEUE);
850 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
851 rtlpriv->link_info.num_tx_inperiod++;
853 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
854 "Vo TX OK interrupt!\n");
855 _rtl_pci_tx_isr(hw, VO_QUEUE);
858 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
859 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
860 rtlpriv->link_info.num_tx_inperiod++;
862 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
863 "CMD TX OK interrupt!\n");
864 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
869 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
870 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
871 _rtl_pci_rx_interrupt(hw);
874 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
875 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
876 "rx descriptor unavailable!\n");
877 _rtl_pci_rx_interrupt(hw);
880 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
881 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
882 _rtl_pci_rx_interrupt(hw);
885 if (rtlpriv->rtlhal.earlymode_enable)
886 tasklet_schedule(&rtlpriv->works.irq_tasklet);
889 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
893 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
895 _rtl_pci_tx_chk_waitq(hw);
898 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
901 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
902 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
903 struct rtl8192_tx_ring *ring = NULL;
904 struct ieee80211_hdr *hdr = NULL;
905 struct ieee80211_tx_info *info = NULL;
906 struct sk_buff *pskb = NULL;
907 struct rtl_tx_desc *pdesc = NULL;
908 struct rtl_tcb_desc tcb_desc;
911 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
912 ring = &rtlpci->tx_ring[BEACON_QUEUE];
913 pskb = __skb_dequeue(&ring->queue);
915 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
916 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
917 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
918 pskb->len, PCI_DMA_TODEVICE);
922 /*NB: the beacon data buffer must be 32-bit aligned. */
923 pskb = ieee80211_beacon_get(hw, mac->vif);
926 hdr = rtl_get_hdr(pskb);
927 info = IEEE80211_SKB_CB(pskb);
928 pdesc = &ring->desc[0];
929 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
930 info, NULL, pskb, BEACON_QUEUE, &tcb_desc);
932 __skb_queue_tail(&ring->queue, pskb);
934 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
940 static void rtl_lps_leave_work_callback(struct work_struct *work)
942 struct rtl_works *rtlworks =
943 container_of(work, struct rtl_works, lps_leave_work);
944 struct ieee80211_hw *hw = rtlworks->hw;
949 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
951 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
954 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
955 rtlpci->txringcount[i] = RT_TXDESC_NUM;
958 *we just alloc 2 desc for beacon queue,
959 *because we just need first desc in hw beacon.
961 rtlpci->txringcount[BEACON_QUEUE] = 2;
964 *BE queue need more descriptor for performance
965 *consideration or, No more tx desc will happen,
966 *and may cause mac80211 mem leakage.
968 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
970 rtlpci->rxbuffersize = 9100; /*2048/1024; */
971 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
974 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
975 struct pci_dev *pdev)
977 struct rtl_priv *rtlpriv = rtl_priv(hw);
978 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
979 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
980 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
982 rtlpci->up_first_time = true;
983 rtlpci->being_init_adapter = false;
988 /*Tx/Rx related var */
989 _rtl_pci_init_trx_var(hw);
991 /*IBSS*/ mac->beacon_interval = 100;
994 mac->min_space_cfg = 0;
995 mac->max_mss_density = 0;
996 /*set sane AMPDU defaults */
997 mac->current_ampdu_density = 7;
998 mac->current_ampdu_factor = 3;
1001 rtlpci->acm_method = eAcmWay2_SW;
1004 tasklet_init(&rtlpriv->works.irq_tasklet,
1005 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1007 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1008 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1010 INIT_WORK(&rtlpriv->works.lps_leave_work, rtl_lps_leave_work_callback);
1013 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1014 unsigned int prio, unsigned int entries)
1016 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1017 struct rtl_priv *rtlpriv = rtl_priv(hw);
1018 struct rtl_tx_desc *ring;
1020 u32 nextdescaddress;
1023 ring = pci_alloc_consistent(rtlpci->pdev,
1024 sizeof(*ring) * entries, &dma);
1026 if (!ring || (unsigned long)ring & 0xFF) {
1027 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1028 "Cannot allocate TX ring (prio = %d)\n", prio);
1032 memset(ring, 0, sizeof(*ring) * entries);
1033 rtlpci->tx_ring[prio].desc = ring;
1034 rtlpci->tx_ring[prio].dma = dma;
1035 rtlpci->tx_ring[prio].idx = 0;
1036 rtlpci->tx_ring[prio].entries = entries;
1037 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1042 for (i = 0; i < entries; i++) {
1043 nextdescaddress = (u32) dma +
1044 ((i + 1) % entries) *
1047 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1048 true, HW_DESC_TX_NEXTDESC_ADDR,
1049 (u8 *)&nextdescaddress);
1055 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1057 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1058 struct rtl_priv *rtlpriv = rtl_priv(hw);
1059 struct rtl_rx_desc *entry = NULL;
1060 int i, rx_queue_idx;
1064 *rx_queue_idx 0:RX_MPDU_QUEUE
1065 *rx_queue_idx 1:RX_CMD_QUEUE
1067 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1069 rtlpci->rx_ring[rx_queue_idx].desc =
1070 pci_alloc_consistent(rtlpci->pdev,
1071 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1072 desc) * rtlpci->rxringcount,
1073 &rtlpci->rx_ring[rx_queue_idx].dma);
1075 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1076 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1077 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1078 "Cannot allocate RX ring\n");
1082 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1083 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1084 rtlpci->rxringcount);
1086 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1088 /* If amsdu_8k is disabled, set buffersize to 4096. This
1089 * change will reduce memory fragmentation.
1091 if (rtlpci->rxbuffersize > 4096 &&
1092 rtlpriv->rtlhal.disable_amsdu_8k)
1093 rtlpci->rxbuffersize = 4096;
1095 for (i = 0; i < rtlpci->rxringcount; i++) {
1096 struct sk_buff *skb =
1097 dev_alloc_skb(rtlpci->rxbuffersize);
1101 kmemleak_not_leak(skb);
1102 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1104 /*skb->dev = dev; */
1106 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1109 *just set skb->cb to mapping addr
1110 *for pci_unmap_single use
1112 *((dma_addr_t *) skb->cb) =
1113 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1114 rtlpci->rxbuffersize,
1115 PCI_DMA_FROMDEVICE);
1117 bufferaddress = (*((dma_addr_t *)skb->cb));
1118 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1119 HW_DESC_RXBUFF_ADDR,
1120 (u8 *)&bufferaddress);
1121 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1125 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1130 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1131 HW_DESC_RXERO, &tmp_one);
1136 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1139 struct rtl_priv *rtlpriv = rtl_priv(hw);
1140 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1141 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1143 while (skb_queue_len(&ring->queue)) {
1144 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1145 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1147 pci_unmap_single(rtlpci->pdev,
1149 ops->get_desc((u8 *) entry, true,
1150 HW_DESC_TXBUFF_ADDR),
1151 skb->len, PCI_DMA_TODEVICE);
1153 ring->idx = (ring->idx + 1) % ring->entries;
1157 pci_free_consistent(rtlpci->pdev,
1158 sizeof(*ring->desc) * ring->entries,
1159 ring->desc, ring->dma);
1164 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1166 int i, rx_queue_idx;
1168 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1169 /*rx_queue_idx 1:RX_CMD_QUEUE */
1170 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1172 for (i = 0; i < rtlpci->rxringcount; i++) {
1173 struct sk_buff *skb =
1174 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1178 pci_unmap_single(rtlpci->pdev,
1179 *((dma_addr_t *) skb->cb),
1180 rtlpci->rxbuffersize,
1181 PCI_DMA_FROMDEVICE);
1185 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1186 pci_free_consistent(rtlpci->pdev,
1187 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1188 desc) * rtlpci->rxringcount,
1189 rtlpci->rx_ring[rx_queue_idx].desc,
1190 rtlpci->rx_ring[rx_queue_idx].dma);
1191 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1196 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1202 ret = _rtl_pci_init_rx_ring(hw);
1206 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1207 ret = _rtl_pci_init_tx_ring(hw, i,
1208 rtlpci->txringcount[i]);
1210 goto err_free_rings;
1216 _rtl_pci_free_rx_ring(rtlpci);
1218 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1219 if (rtlpci->tx_ring[i].desc)
1220 _rtl_pci_free_tx_ring(hw, i);
1225 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1231 _rtl_pci_free_rx_ring(rtlpci);
1234 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1235 _rtl_pci_free_tx_ring(hw, i);
1240 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244 int i, rx_queue_idx;
1245 unsigned long flags;
1248 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1249 /*rx_queue_idx 1:RX_CMD_QUEUE */
1250 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1253 *force the rx_ring[RX_MPDU_QUEUE/
1254 *RX_CMD_QUEUE].idx to the first one
1256 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1257 struct rtl_rx_desc *entry = NULL;
1259 for (i = 0; i < rtlpci->rxringcount; i++) {
1260 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1261 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1266 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1271 *after reset, release previous pending packet,
1272 *and force the tx idx to the first one
1274 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1275 if (rtlpci->tx_ring[i].desc) {
1276 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1278 while (skb_queue_len(&ring->queue)) {
1279 struct rtl_tx_desc *entry;
1280 struct sk_buff *skb;
1282 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1284 entry = &ring->desc[ring->idx];
1285 skb = __skb_dequeue(&ring->queue);
1286 pci_unmap_single(rtlpci->pdev,
1291 HW_DESC_TXBUFF_ADDR),
1292 skb->len, PCI_DMA_TODEVICE);
1293 ring->idx = (ring->idx + 1) % ring->entries;
1294 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1305 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1306 struct ieee80211_sta *sta,
1307 struct sk_buff *skb)
1309 struct rtl_priv *rtlpriv = rtl_priv(hw);
1310 struct rtl_sta_info *sta_entry = NULL;
1311 u8 tid = rtl_get_tid(skb);
1315 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1317 if (!rtlpriv->rtlhal.earlymode_enable)
1319 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1321 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1326 /* maybe every tid should be checked */
1327 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1330 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1331 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1332 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1337 static int rtl_pci_tx(struct ieee80211_hw *hw,
1338 struct ieee80211_sta *sta,
1339 struct sk_buff *skb,
1340 struct rtl_tcb_desc *ptcb_desc)
1342 struct rtl_priv *rtlpriv = rtl_priv(hw);
1343 struct rtl_sta_info *sta_entry = NULL;
1344 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1345 struct rtl8192_tx_ring *ring;
1346 struct rtl_tx_desc *pdesc;
1348 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1349 unsigned long flags;
1350 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1351 __le16 fc = rtl_get_fc(skb);
1352 u8 *pda_addr = hdr->addr1;
1353 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1360 if (ieee80211_is_auth(fc)) {
1361 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n");
1365 if (rtlpriv->psc.sw_ps_enabled) {
1366 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1367 !ieee80211_has_pm(fc))
1368 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1371 rtl_action_proc(hw, skb, true);
1373 if (is_multicast_ether_addr(pda_addr))
1374 rtlpriv->stats.txbytesmulticast += skb->len;
1375 else if (is_broadcast_ether_addr(pda_addr))
1376 rtlpriv->stats.txbytesbroadcast += skb->len;
1378 rtlpriv->stats.txbytesunicast += skb->len;
1380 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1381 ring = &rtlpci->tx_ring[hw_queue];
1382 if (hw_queue != BEACON_QUEUE)
1383 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1388 pdesc = &ring->desc[idx];
1389 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1392 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1393 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1394 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1395 hw_queue, ring->idx, idx,
1396 skb_queue_len(&ring->queue));
1398 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1402 if (ieee80211_is_data_qos(fc)) {
1403 tid = rtl_get_tid(skb);
1405 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1406 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1407 IEEE80211_SCTL_SEQ) >> 4;
1410 if (!ieee80211_has_morefrags(hdr->frame_control))
1411 sta_entry->tids[tid].seq_number = seq_number;
1415 if (ieee80211_is_data(fc))
1416 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1418 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1419 info, sta, skb, hw_queue, ptcb_desc);
1421 __skb_queue_tail(&ring->queue, skb);
1423 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1424 HW_DESC_OWN, &temp_one);
1427 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1428 hw_queue != BEACON_QUEUE) {
1430 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1431 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1432 hw_queue, ring->idx, idx,
1433 skb_queue_len(&ring->queue));
1435 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1438 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1440 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1445 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1447 struct rtl_priv *rtlpriv = rtl_priv(hw);
1448 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1449 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1452 struct rtl8192_tx_ring *ring;
1454 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1456 ring = &pcipriv->dev.tx_ring[queue_id];
1457 queue_len = skb_queue_len(&ring->queue);
1458 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1459 queue_id == TXCMD_QUEUE) {
1467 /* we just wait 1s for all queues */
1468 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1469 is_hal_stop(rtlhal) || i >= 200)
1474 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1476 struct rtl_priv *rtlpriv = rtl_priv(hw);
1477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1479 _rtl_pci_deinit_trx_ring(hw);
1481 synchronize_irq(rtlpci->pdev->irq);
1482 tasklet_kill(&rtlpriv->works.irq_tasklet);
1483 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1485 flush_workqueue(rtlpriv->works.rtl_wq);
1486 destroy_workqueue(rtlpriv->works.rtl_wq);
1490 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1492 struct rtl_priv *rtlpriv = rtl_priv(hw);
1495 _rtl_pci_init_struct(hw, pdev);
1497 err = _rtl_pci_init_trx_ring(hw);
1499 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1500 "tx ring initialization failed\n");
1507 static int rtl_pci_start(struct ieee80211_hw *hw)
1509 struct rtl_priv *rtlpriv = rtl_priv(hw);
1510 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1511 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1512 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1516 rtl_pci_reset_trx_ring(hw);
1518 rtlpci->driver_is_goingto_unload = false;
1519 err = rtlpriv->cfg->ops->hw_init(hw);
1521 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1522 "Failed to config hardware!\n");
1526 rtlpriv->cfg->ops->enable_interrupt(hw);
1527 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1529 rtl_init_rx_config(hw);
1531 /*should be after adapter start and interrupt enable. */
1532 set_hal_start(rtlhal);
1534 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1536 rtlpci->up_first_time = false;
1538 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1542 static void rtl_pci_stop(struct ieee80211_hw *hw)
1544 struct rtl_priv *rtlpriv = rtl_priv(hw);
1545 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1546 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1547 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1548 unsigned long flags;
1549 u8 RFInProgressTimeOut = 0;
1552 *should be before disable interrupt&adapter
1553 *and will do it immediately.
1555 set_hal_stop(rtlhal);
1557 rtlpriv->cfg->ops->disable_interrupt(hw);
1558 cancel_work_sync(&rtlpriv->works.lps_leave_work);
1560 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1561 while (ppsc->rfchange_inprogress) {
1562 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1563 if (RFInProgressTimeOut > 100) {
1564 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1568 RFInProgressTimeOut++;
1569 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1571 ppsc->rfchange_inprogress = true;
1572 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1574 rtlpci->driver_is_goingto_unload = true;
1575 rtlpriv->cfg->ops->hw_disable(hw);
1576 /* some things are not needed if firmware not available */
1577 if (!rtlpriv->max_fw_size)
1579 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1581 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1582 ppsc->rfchange_inprogress = false;
1583 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1585 rtl_pci_enable_aspm(hw);
1588 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1589 struct ieee80211_hw *hw)
1591 struct rtl_priv *rtlpriv = rtl_priv(hw);
1592 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1593 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1594 struct pci_dev *bridge_pdev = pdev->bus->self;
1601 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1602 venderid = pdev->vendor;
1603 deviceid = pdev->device;
1604 pci_read_config_byte(pdev, 0x8, &revisionid);
1605 pci_read_config_word(pdev, 0x3C, &irqline);
1607 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1608 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1609 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1610 * the correct driver is r8192e_pci, thus this routine should
1613 if (deviceid == RTL_PCI_8192SE_DID &&
1614 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1617 if (deviceid == RTL_PCI_8192_DID ||
1618 deviceid == RTL_PCI_0044_DID ||
1619 deviceid == RTL_PCI_0047_DID ||
1620 deviceid == RTL_PCI_8192SE_DID ||
1621 deviceid == RTL_PCI_8174_DID ||
1622 deviceid == RTL_PCI_8173_DID ||
1623 deviceid == RTL_PCI_8172_DID ||
1624 deviceid == RTL_PCI_8171_DID) {
1625 switch (revisionid) {
1626 case RTL_PCI_REVISION_ID_8192PCIE:
1627 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1628 "8192 PCI-E is found - vid/did=%x/%x\n",
1629 venderid, deviceid);
1630 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1632 case RTL_PCI_REVISION_ID_8192SE:
1633 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1634 "8192SE is found - vid/did=%x/%x\n",
1635 venderid, deviceid);
1636 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1639 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1640 "Err: Unknown device - vid/did=%x/%x\n",
1641 venderid, deviceid);
1642 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1646 } else if (deviceid == RTL_PCI_8192CET_DID ||
1647 deviceid == RTL_PCI_8192CE_DID ||
1648 deviceid == RTL_PCI_8191CE_DID ||
1649 deviceid == RTL_PCI_8188CE_DID) {
1650 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1651 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1652 "8192C PCI-E is found - vid/did=%x/%x\n",
1653 venderid, deviceid);
1654 } else if (deviceid == RTL_PCI_8192DE_DID ||
1655 deviceid == RTL_PCI_8192DE_DID2) {
1656 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1657 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1658 "8192D PCI-E is found - vid/did=%x/%x\n",
1659 venderid, deviceid);
1661 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1662 "Err: Unknown device - vid/did=%x/%x\n",
1663 venderid, deviceid);
1665 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1668 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1669 if (revisionid == 0 || revisionid == 1) {
1670 if (revisionid == 0) {
1671 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1672 "Find 92DE MAC0\n");
1673 rtlhal->interfaceindex = 0;
1674 } else if (revisionid == 1) {
1675 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1676 "Find 92DE MAC1\n");
1677 rtlhal->interfaceindex = 1;
1680 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1681 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1682 venderid, deviceid, revisionid);
1683 rtlhal->interfaceindex = 0;
1687 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1688 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1689 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1692 /*find bridge info if available */
1693 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1694 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1695 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1696 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1697 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1698 "Pci Bridge Vendor is found index: %d\n",
1705 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1706 PCI_BRIDGE_VENDOR_UNKNOWN) {
1707 pcipriv->ndis_adapter.pcibridge_busnum =
1708 bridge_pdev->bus->number;
1709 pcipriv->ndis_adapter.pcibridge_devnum =
1710 PCI_SLOT(bridge_pdev->devfn);
1711 pcipriv->ndis_adapter.pcibridge_funcnum =
1712 PCI_FUNC(bridge_pdev->devfn);
1713 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1714 pci_pcie_cap(bridge_pdev);
1715 pcipriv->ndis_adapter.num4bytes =
1716 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1718 rtl_pci_get_linkcontrol_field(hw);
1720 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1721 PCI_BRIDGE_VENDOR_AMD) {
1722 pcipriv->ndis_adapter.amd_l1_patch =
1723 rtl_pci_get_amd_l1_patch(hw);
1727 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1728 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1729 pcipriv->ndis_adapter.busnumber,
1730 pcipriv->ndis_adapter.devnumber,
1731 pcipriv->ndis_adapter.funcnumber,
1732 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1734 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1735 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1736 pcipriv->ndis_adapter.pcibridge_busnum,
1737 pcipriv->ndis_adapter.pcibridge_devnum,
1738 pcipriv->ndis_adapter.pcibridge_funcnum,
1739 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1740 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1741 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1742 pcipriv->ndis_adapter.amd_l1_patch);
1744 rtl_pci_parse_configuration(pdev, hw);
1749 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1750 const struct pci_device_id *id)
1752 struct ieee80211_hw *hw = NULL;
1754 struct rtl_priv *rtlpriv = NULL;
1755 struct rtl_pci_priv *pcipriv = NULL;
1756 struct rtl_pci *rtlpci;
1757 unsigned long pmem_start, pmem_len, pmem_flags;
1760 err = pci_enable_device(pdev);
1762 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1767 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1768 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1770 "Unable to obtain 32bit DMA for consistent allocations\n");
1776 pci_set_master(pdev);
1778 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1779 sizeof(struct rtl_priv), &rtl_ops);
1782 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1787 SET_IEEE80211_DEV(hw, &pdev->dev);
1788 pci_set_drvdata(pdev, hw);
1791 pcipriv = (void *)rtlpriv->priv;
1792 pcipriv->dev.pdev = pdev;
1793 init_completion(&rtlpriv->firmware_loading_complete);
1795 /* init cfg & intf_ops */
1796 rtlpriv->rtlhal.interface = INTF_PCI;
1797 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1798 rtlpriv->intf_ops = &rtl_pci_ops;
1801 *init dbgp flags before all
1802 *other functions, because we will
1803 *use it in other funtions like
1804 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1805 *you can not use these macro
1808 rtl_dbgp_flag_init(hw);
1811 err = pci_request_regions(pdev, KBUILD_MODNAME);
1813 RT_ASSERT(false, "Can't obtain PCI resources\n");
1817 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1818 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1819 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1821 /*shared mem start */
1822 rtlpriv->io.pci_mem_start =
1823 (unsigned long)pci_iomap(pdev,
1824 rtlpriv->cfg->bar_id, pmem_len);
1825 if (rtlpriv->io.pci_mem_start == 0) {
1826 RT_ASSERT(false, "Can't map PCI mem\n");
1831 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1832 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1833 pmem_start, pmem_len, pmem_flags,
1834 rtlpriv->io.pci_mem_start);
1836 /* Disable Clk Request */
1837 pci_write_config_byte(pdev, 0x81, 0);
1839 pci_write_config_byte(pdev, 0x44, 0);
1840 pci_write_config_byte(pdev, 0x04, 0x06);
1841 pci_write_config_byte(pdev, 0x04, 0x07);
1844 if (!_rtl_pci_find_adapter(pdev, hw)) {
1849 /* Init IO handler */
1850 _rtl_pci_io_handler_init(&pdev->dev, hw);
1852 /*like read eeprom and so on */
1853 rtlpriv->cfg->ops->read_eeprom_info(hw);
1856 rtl_pci_init_aspm(hw);
1858 /* Init mac80211 sw */
1859 err = rtl_init_core(hw);
1861 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1862 "Can't allocate sw for mac80211\n");
1867 err = rtl_pci_init(hw, pdev);
1869 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1873 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1874 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1879 rtlpriv->cfg->ops->init_sw_leds(hw);
1881 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1883 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1884 "failed to create sysfs device attributes\n");
1888 rtlpci = rtl_pcidev(pcipriv);
1889 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1890 IRQF_SHARED, KBUILD_MODNAME, hw);
1892 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1893 "%s: failed to register IRQ handler\n",
1894 wiphy_name(hw->wiphy));
1897 rtlpci->irq_alloc = 1;
1902 rtl_deinit_core(hw);
1903 _rtl_pci_io_handler_release(hw);
1905 if (rtlpriv->io.pci_mem_start != 0)
1906 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1909 pci_release_regions(pdev);
1910 complete(&rtlpriv->firmware_loading_complete);
1914 ieee80211_free_hw(hw);
1915 pci_set_drvdata(pdev, NULL);
1916 pci_disable_device(pdev);
1921 EXPORT_SYMBOL(rtl_pci_probe);
1923 void rtl_pci_disconnect(struct pci_dev *pdev)
1925 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1926 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1927 struct rtl_priv *rtlpriv = rtl_priv(hw);
1928 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1929 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1931 /* just in case driver is removed before firmware callback */
1932 wait_for_completion(&rtlpriv->firmware_loading_complete);
1933 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1935 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1937 /*ieee80211_unregister_hw will call ops_stop */
1938 if (rtlmac->mac80211_registered == 1) {
1939 ieee80211_unregister_hw(hw);
1940 rtlmac->mac80211_registered = 0;
1942 rtl_deinit_deferred_work(hw);
1943 rtlpriv->intf_ops->adapter_stop(hw);
1945 rtlpriv->cfg->ops->disable_interrupt(hw);
1948 rtl_deinit_rfkill(hw);
1951 rtl_deinit_core(hw);
1952 _rtl_pci_io_handler_release(hw);
1953 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1955 if (rtlpci->irq_alloc) {
1956 free_irq(rtlpci->pdev->irq, hw);
1957 rtlpci->irq_alloc = 0;
1960 if (rtlpriv->io.pci_mem_start != 0) {
1961 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1962 pci_release_regions(pdev);
1965 pci_disable_device(pdev);
1967 rtl_pci_disable_aspm(hw);
1969 pci_set_drvdata(pdev, NULL);
1971 ieee80211_free_hw(hw);
1973 EXPORT_SYMBOL(rtl_pci_disconnect);
1975 /***************************************
1976 kernel pci power state define:
1977 PCI_D0 ((pci_power_t __force) 0)
1978 PCI_D1 ((pci_power_t __force) 1)
1979 PCI_D2 ((pci_power_t __force) 2)
1980 PCI_D3hot ((pci_power_t __force) 3)
1981 PCI_D3cold ((pci_power_t __force) 4)
1982 PCI_UNKNOWN ((pci_power_t __force) 5)
1984 This function is called when system
1985 goes into suspend state mac80211 will
1986 call rtl_mac_stop() from the mac80211
1987 suspend function first, So there is
1988 no need to call hw_disable here.
1989 ****************************************/
1990 int rtl_pci_suspend(struct device *dev)
1992 struct pci_dev *pdev = to_pci_dev(dev);
1993 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1994 struct rtl_priv *rtlpriv = rtl_priv(hw);
1996 rtlpriv->cfg->ops->hw_suspend(hw);
1997 rtl_deinit_rfkill(hw);
2001 EXPORT_SYMBOL(rtl_pci_suspend);
2003 int rtl_pci_resume(struct device *dev)
2005 struct pci_dev *pdev = to_pci_dev(dev);
2006 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2007 struct rtl_priv *rtlpriv = rtl_priv(hw);
2009 rtlpriv->cfg->ops->hw_resume(hw);
2010 rtl_init_rfkill(hw);
2013 EXPORT_SYMBOL(rtl_pci_resume);
2015 struct rtl_intf_ops rtl_pci_ops = {
2016 .read_efuse_byte = read_efuse_byte,
2017 .adapter_start = rtl_pci_start,
2018 .adapter_stop = rtl_pci_stop,
2019 .adapter_tx = rtl_pci_tx,
2020 .flush = rtl_pci_flush,
2021 .reset_trx_ring = rtl_pci_reset_trx_ring,
2022 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2024 .disable_aspm = rtl_pci_disable_aspm,
2025 .enable_aspm = rtl_pci_enable_aspm,