drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/fw_common.h"
  41 #include "dm.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 #define LLT_CONFIG      5
  46
  47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  48                                       u8 set_bits, u8 clear_bits)
  49 {
  50         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52
  53         rtlpci->reg_bcn_ctrl_val |= set_bits;
  54         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  55
  56         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  57 }
  58
  59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62         u8 tmp1byte;
  63
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  65         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  67         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  68         tmp1byte &= ~(BIT(0));
  69         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  70 }
  71
  72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         u8 tmp1byte;
  76
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  78         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  80         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  81         tmp1byte |= BIT(0);
  82         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  83 }
  84
  85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  86 {
  87         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  88 }
  89
  90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  91 {
  92         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  93 }
  94
  95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  96 {
  97         struct rtl_priv *rtlpriv = rtl_priv(hw);
  98         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  99         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 100
 101         switch (variable) {
 102         case HW_VAR_RCR:
 103                 *((u32 *) (val)) = rtlpci->receive_config;
 104                 break;
 105         case HW_VAR_RF_STATE:
 106                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 107                 break;
 108         case HW_VAR_FWLPS_RF_ON:{
 109                         enum rf_pwrstate rfState;
 110                         u32 val_rcr;
 111
 112                         rtlpriv->cfg->ops->get_hw_reg(hw,
 113                                                       HW_VAR_RF_STATE,
 114                                                       (u8 *) (&rfState));
 115                         if (rfState == ERFOFF) {
 116                                 *((bool *) (val)) = true;
 117                         } else {
 118                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 119                                 val_rcr &= 0x00070000;
 120                                 if (val_rcr)
 121                                         *((bool *) (val)) = false;
 122                                 else
 123                                         *((bool *) (val)) = true;
 124                         }
 125                         break;
 126                 }
 127         case HW_VAR_FW_PSMODE_STATUS:
 128                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 129                 break;
 130         case HW_VAR_CORRECT_TSF:{
 131                 u64 tsf;
 132                 u32 *ptsf_low = (u32 *)&tsf;
 133                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 134
 135                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 136                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 137
 138                 *((u64 *) (val)) = tsf;
 139
 140                 break;
 141                 }
 142         default:
 143                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 144                          "switch case not processed\n");
 145                 break;
 146         }
 147 }
 148
 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 rate_cfg = ((u16 *) val)[0];
 170                         u8 rate_index = 0;
 171                         rate_cfg &= 0x15f;
 172                         rate_cfg |= 0x01;
 173                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 174                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 175                                        (rate_cfg >> 8) & 0xff);
 176                         while (rate_cfg > 0x1) {
 177                                 rate_cfg = (rate_cfg >> 1);
 178                                 rate_index++;
 179                         }
 180                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 181                                        rate_index);
 182                         break;
 183                 }
 184         case HW_VAR_BSSID:{
 185                         for (idx = 0; idx < ETH_ALEN; idx++) {
 186                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 187                                                val[idx]);
 188                         }
 189                         break;
 190                 }
 191         case HW_VAR_SIFS:{
 192                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 193                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 194
 195                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 196                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 197
 198                         if (!mac->ht_enable)
 199                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 200                                                0x0e0e);
 201                         else
 202                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 203                                                *((u16 *) val));
 204                         break;
 205                 }
 206         case HW_VAR_SLOT_TIME:{
 207                         u8 e_aci;
 208
 209                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 210                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 211
 212                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 213
 214                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 215                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 216                                                               HW_VAR_AC_PARAM,
 217                                                               &e_aci);
 218                         }
 219                         break;
 220                 }
 221         case HW_VAR_ACK_PREAMBLE:{
 222                         u8 reg_tmp;
 223                         u8 short_preamble = (bool)*val;
 224                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 225                         if (short_preamble)
 226                                 reg_tmp |= 0x80;
 227
 228                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 229                         break;
 230                 }
 231         case HW_VAR_AMPDU_MIN_SPACE:{
 232                         u8 min_spacing_to_set;
 233                         u8 sec_min_space;
 234
 235                         min_spacing_to_set = *val;
 236                         if (min_spacing_to_set <= 7) {
 237                                 sec_min_space = 0;
 238
 239                                 if (min_spacing_to_set < sec_min_space)
 240                                         min_spacing_to_set = sec_min_space;
 241
 242                                 mac->min_space_cfg = ((mac->min_space_cfg &
 243                                                        0xf8) |
 244                                                       min_spacing_to_set);
 245
 246                                 *val = min_spacing_to_set;
 247
 248                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 249                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 250                                          mac->min_space_cfg);
 251
 252                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 253                                                mac->min_space_cfg);
 254                         }
 255                         break;
 256                 }
 257         case HW_VAR_SHORTGI_DENSITY:{
 258                         u8 density_to_set;
 259
 260                         density_to_set = *val;
 261                         mac->min_space_cfg |= (density_to_set << 3);
 262
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 265                                  mac->min_space_cfg);
 266
 267                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 268                                        mac->min_space_cfg);
 269
 270                         break;
 271                 }
 272         case HW_VAR_AMPDU_FACTOR:{
 273                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 274                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 275
 276                         u8 factor_toset;
 277                         u8 *p_regtoset = NULL;
 278                         u8 index = 0;
 279
 280                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 281                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 282                             BT_CSR_BC4))
 283                                 p_regtoset = regtoset_bt;
 284                         else
 285                                 p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *(val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                          factor_toset);
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *(val);
 320                         rtl92c_dm_init_edca_turbo(hw);
 321
 322                         if (rtlpci->acm_method != eAcmWay2_SW)
 323                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 324                                                               HW_VAR_ACM_CTRL,
 325                                                               (&e_aci));
 326                         break;
 327                 }
 328         case HW_VAR_ACM_CTRL:{
 329                         u8 e_aci = *(val);
 330                         union aci_aifsn *p_aci_aifsn =
 331                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                         u8 acm = p_aci_aifsn->f.acm;
 333                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                         acm_ctrl =
 336                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 337
 338                         if (acm) {
 339                                 switch (e_aci) {
 340                                 case AC0_BE:
 341                                         acm_ctrl |= AcmHw_BeqEn;
 342                                         break;
 343                                 case AC2_VI:
 344                                         acm_ctrl |= AcmHw_ViqEn;
 345                                         break;
 346                                 case AC3_VO:
 347                                         acm_ctrl |= AcmHw_VoqEn;
 348                                         break;
 349                                 default:
 350                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 351                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 352                                                  acm);
 353                                         break;
 354                                 }
 355                         } else {
 356                                 switch (e_aci) {
 357                                 case AC0_BE:
 358                                         acm_ctrl &= (~AcmHw_BeqEn);
 359                                         break;
 360                                 case AC2_VI:
 361                                         acm_ctrl &= (~AcmHw_ViqEn);
 362                                         break;
 363                                 case AC3_VO:
 364                                         acm_ctrl &= (~AcmHw_BeqEn);
 365                                         break;
 366                                 default:
 367                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                                                  "switch case not processed\n");
 369                                         break;
 370                                 }
 371                         }
 372
 373                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 374                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 375                                  acm_ctrl);
 376                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 377                         break;
 378                 }
 379         case HW_VAR_RCR:{
 380                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 381                         rtlpci->receive_config = ((u32 *) (val))[0];
 382                         break;
 383                 }
 384         case HW_VAR_RETRY_LIMIT:{
 385                         u8 retry_limit = val[0];
 386
 387                         rtl_write_word(rtlpriv, REG_RL,
 388                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 389                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 390                         break;
 391                 }
 392         case HW_VAR_DUAL_TSF_RST:
 393                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 394                 break;
 395         case HW_VAR_EFUSE_BYTES:
 396                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 397                 break;
 398         case HW_VAR_EFUSE_USAGE:
 399                 rtlefuse->efuse_usedpercentage = *val;
 400                 break;
 401         case HW_VAR_IO_CMD:
 402                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 403                 break;
 404         case HW_VAR_WPA_CONFIG:
 405                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 406                 break;
 407         case HW_VAR_SET_RPWM:{
 408                         u8 rpwm_val;
 409
 410                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 411                         udelay(1);
 412
 413                         if (rpwm_val & BIT(7)) {
 414                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 415                         } else {
 416                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 417                                                *val | BIT(7));
 418                         }
 419
 420                         break;
 421                 }
 422         case HW_VAR_H2C_FW_PWRMODE:{
 423                         u8 psmode = *val;
 424
 425                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 426                             (!IS_92C_SERIAL(rtlhal->version))) {
 427                                 rtl92c_dm_rf_saving(hw, true);
 428                         }
 429
 430                         rtl92c_set_fw_pwrmode_cmd(hw, *val);
 431                         break;
 432                 }
 433         case HW_VAR_FW_PSMODE_STATUS:
 434                 ppsc->fw_current_inpsmode = *((bool *) val);
 435                 break;
 436         case HW_VAR_H2C_FW_JOINBSSRPT:{
 437                         u8 mstatus = *val;
 438                         u8 tmp_regcr, tmp_reg422;
 439                         bool recover = false;
 440
 441                         if (mstatus == RT_MEDIA_CONNECT) {
 442                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 443                                                               NULL);
 444
 445                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 446                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 447                                                (tmp_regcr | BIT(0)));
 448
 449                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 450                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 451
 452                                 tmp_reg422 =
 453                                     rtl_read_byte(rtlpriv,
 454                                                   REG_FWHW_TXQ_CTRL + 2);
 455                                 if (tmp_reg422 & BIT(6))
 456                                         recover = true;
 457                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 458                                                tmp_reg422 & (~BIT(6)));
 459
 460                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 461
 462                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 463                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 464
 465                                 if (recover) {
 466                                         rtl_write_byte(rtlpriv,
 467                                                        REG_FWHW_TXQ_CTRL + 2,
 468                                                        tmp_reg422);
 469                                 }
 470
 471                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 472                                                (tmp_regcr & ~(BIT(0))));
 473                         }
 474                         rtl92c_set_fw_joinbss_report_cmd(hw, *val);
 475
 476                         break;
 477                 }
 478         case HW_VAR_AID:{
 479                         u16 u2btmp;
 480                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 481                         u2btmp &= 0xC000;
 482                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 483                                                 mac->assoc_id));
 484
 485                         break;
 486                 }
 487         case HW_VAR_CORRECT_TSF:{
 488                         u8 btype_ibss = val[0];
 489
 490                         if (btype_ibss)
 491                                 _rtl92ce_stop_tx_beacon(hw);
 492
 493                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 494
 495                         rtl_write_dword(rtlpriv, REG_TSFTR,
 496                                         (u32) (mac->tsf & 0xffffffff));
 497                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 498                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 499
 500                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 501
 502                         if (btype_ibss)
 503                                 _rtl92ce_resume_tx_beacon(hw);
 504
 505                         break;
 506
 507                 }
 508         default:
 509                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 510                          "switch case not processed\n");
 511                 break;
 512         }
 513 }
 514
 515 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 516 {
 517         struct rtl_priv *rtlpriv = rtl_priv(hw);
 518         bool status = true;
 519         long count = 0;
 520         u32 value = _LLT_INIT_ADDR(address) |
 521             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 522
 523         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 524
 525         do {
 526                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 527                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 528                         break;
 529
 530                 if (count > POLLING_LLT_THRESHOLD) {
 531                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 532                                  "Failed to polling write LLT done at address %d!\n",
 533                                  address);
 534                         status = false;
 535                         break;
 536                 }
 537         } while (++count);
 538
 539         return status;
 540 }
 541
 542 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 543 {
 544         struct rtl_priv *rtlpriv = rtl_priv(hw);
 545         unsigned short i;
 546         u8 txpktbuf_bndy;
 547         u8 maxPage;
 548         bool status;
 549
 550 #if LLT_CONFIG == 1
 551         maxPage = 255;
 552         txpktbuf_bndy = 252;
 553 #elif LLT_CONFIG == 2
 554         maxPage = 127;
 555         txpktbuf_bndy = 124;
 556 #elif LLT_CONFIG == 3
 557         maxPage = 255;
 558         txpktbuf_bndy = 174;
 559 #elif LLT_CONFIG == 4
 560         maxPage = 255;
 561         txpktbuf_bndy = 246;
 562 #elif LLT_CONFIG == 5
 563         maxPage = 255;
 564         txpktbuf_bndy = 246;
 565 #endif
 566
 567 #if LLT_CONFIG == 1
 568         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 569         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 570 #elif LLT_CONFIG == 2
 571         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 572 #elif LLT_CONFIG == 3
 573         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 574 #elif LLT_CONFIG == 4
 575         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 576 #elif LLT_CONFIG == 5
 577         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 578
 579         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 580 #endif
 581
 582         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 583         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 584
 585         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 586         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 587
 588         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 589         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 590         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 591
 592         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 593                 status = _rtl92ce_llt_write(hw, i, i + 1);
 594                 if (true != status)
 595                         return status;
 596         }
 597
 598         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 599         if (true != status)
 600                 return status;
 601
 602         for (i = txpktbuf_bndy; i < maxPage; i++) {
 603                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 604                 if (true != status)
 605                         return status;
 606         }
 607
 608         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 609         if (true != status)
 610                 return status;
 611
 612         return true;
 613 }
 614
 615 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 616 {
 617         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 618         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 619         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 620         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 621
 622         if (rtlpci->up_first_time)
 623                 return;
 624
 625         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 626                 rtl92ce_sw_led_on(hw, pLed0);
 627         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 628                 rtl92ce_sw_led_on(hw, pLed0);
 629         else
 630                 rtl92ce_sw_led_off(hw, pLed0);
 631 }
 632
 633 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 634 {
 635         struct rtl_priv *rtlpriv = rtl_priv(hw);
 636         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 637         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 638         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 639
 640         unsigned char bytetmp;
 641         unsigned short wordtmp;
 642         u16 retry;
 643
 644         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 645         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 646                 u32 value32;
 647                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 648                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 649                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 650         }
 651         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 652         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 653
 654         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 655                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 656
 657                 u4b_tmp &= (~0x00024800);
 658                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 659         }
 660
 661         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 662         udelay(2);
 663
 664         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 665         udelay(2);
 666
 667         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 668         udelay(2);
 669
 670         retry = 0;
 671         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 672                  rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 673
 674         while ((bytetmp & BIT(0)) && retry < 1000) {
 675                 retry++;
 676                 udelay(50);
 677                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 678                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 679                          rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 680                 udelay(50);
 681         }
 682
 683         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 684
 685         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 686         udelay(2);
 687
 688         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 689                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 690                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 691         }
 692
 693         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 694
 695         if (!_rtl92ce_llt_table_init(hw))
 696                 return false;
 697
 698         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 699         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 700
 701         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 702
 703         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 704         wordtmp &= 0xf;
 705         wordtmp |= 0xF771;
 706         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 707
 708         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 709         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 710         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 711
 712         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 713
 714         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 715                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 716                         DMA_BIT_MASK(32));
 717         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 718                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 719                         DMA_BIT_MASK(32));
 720         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 721                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 722         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 723                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 724         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 725                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 726         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 727                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 728         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 729                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 730                         DMA_BIT_MASK(32));
 731         rtl_write_dword(rtlpriv, REG_RX_DESA,
 732                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 733                         DMA_BIT_MASK(32));
 734
 735         if (IS_92C_SERIAL(rtlhal->version))
 736                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 737         else
 738                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 739
 740         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 741
 742         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 743         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 744         do {
 745                 retry++;
 746                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 747         } while ((retry < 200) && (bytetmp & BIT(7)));
 748
 749         _rtl92ce_gen_refresh_led_state(hw);
 750
 751         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 752
 753         return true;
 754 }
 755
 756 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 757 {
 758         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 759         struct rtl_priv *rtlpriv = rtl_priv(hw);
 760         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 761         u8 reg_bw_opmode;
 762         u32 reg_prsr;
 763
 764         reg_bw_opmode = BW_OPMODE_20MHZ;
 765         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 766
 767         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 768
 769         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 770
 771         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 772
 773         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 774
 775         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 776
 777         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 778
 779         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 780
 781         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 782
 783         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 784
 785         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 786         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 787         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 788         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 789
 790         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 791             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 792                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 793         else
 794                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 795
 796         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 797
 798         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 799
 800         rtlpci->reg_bcn_ctrl_val = 0x1f;
 801         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 802
 803         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 804
 805         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 806
 807         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 808         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 809
 810         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 811             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 812                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 813                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 814         } else {
 815                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 816                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 817         }
 818
 819         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 820              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 821                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 822         else
 823                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 824
 825         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 826
 827         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 828         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 829
 830         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 831
 832         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 833
 834         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 835         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 836
 837 }
 838
 839 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 840 {
 841         struct rtl_priv *rtlpriv = rtl_priv(hw);
 842         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 843
 844         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 845         rtl_write_word(rtlpriv, 0x350, 0x870c);
 846         rtl_write_byte(rtlpriv, 0x352, 0x1);
 847
 848         if (ppsc->support_backdoor)
 849                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 850         else
 851                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 852
 853         rtl_write_word(rtlpriv, 0x350, 0x2718);
 854         rtl_write_byte(rtlpriv, 0x352, 0x1);
 855 }
 856
 857 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 858 {
 859         struct rtl_priv *rtlpriv = rtl_priv(hw);
 860         u8 sec_reg_value;
 861
 862         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 863                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 864                  rtlpriv->sec.pairwise_enc_algorithm,
 865                  rtlpriv->sec.group_enc_algorithm);
 866
 867         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 868                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 869                          "not open hw encryption\n");
 870                 return;
 871         }
 872
 873         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 874
 875         if (rtlpriv->sec.use_defaultkey) {
 876                 sec_reg_value |= SCR_TxUseDK;
 877                 sec_reg_value |= SCR_RxUseDK;
 878         }
 879
 880         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 881
 882         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 883
 884         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 885                  "The SECR-value %x\n", sec_reg_value);
 886
 887         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 888
 889 }
 890
 891 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 892 {
 893         struct rtl_priv *rtlpriv = rtl_priv(hw);
 894         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 895         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 896         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 897         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 898         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 899         static bool iqk_initialized; /* initialized to false */
 900         bool rtstatus = true;
 901         bool is92c;
 902         int err;
 903         u8 tmp_u1b;
 904
 905         rtlpci->being_init_adapter = true;
 906         rtlpriv->intf_ops->disable_aspm(hw);
 907         rtstatus = _rtl92ce_init_mac(hw);
 908         if (!rtstatus) {
 909                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 910                 err = 1;
 911                 return err;
 912         }
 913
 914         err = rtl92c_download_fw(hw);
 915         if (err) {
 916                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 917                          "Failed to download FW. Init HW without FW now..\n");
 918                 err = 1;
 919                 return err;
 920         }
 921
 922         rtlhal->last_hmeboxnum = 0;
 923         rtl92c_phy_mac_config(hw);
 924         rtl92c_phy_bb_config(hw);
 925         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 926         rtl92c_phy_rf_config(hw);
 927         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 928                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 929         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 930                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 931         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 932         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 933         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 934         _rtl92ce_hw_configure(hw);
 935         rtl_cam_reset_all_entry(hw);
 936         rtl92ce_enable_hw_security_config(hw);
 937
 938         ppsc->rfpwr_state = ERFON;
 939
 940         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 941         _rtl92ce_enable_aspm_back_door(hw);
 942         rtlpriv->intf_ops->enable_aspm(hw);
 943
 944         rtl8192ce_bt_hw_init(hw);
 945
 946         if (ppsc->rfpwr_state == ERFON) {
 947                 rtl92c_phy_set_rfpath_switch(hw, 1);
 948                 if (iqk_initialized) {
 949                         rtl92c_phy_iq_calibrate(hw, true);
 950                 } else {
 951                         rtl92c_phy_iq_calibrate(hw, false);
 952                         iqk_initialized = true;
 953                 }
 954
 955                 rtl92c_dm_check_txpower_tracking(hw);
 956                 rtl92c_phy_lc_calibrate(hw);
 957         }
 958
 959         is92c = IS_92C_SERIAL(rtlhal->version);
 960         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 961         if (!(tmp_u1b & BIT(0))) {
 962                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 963                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
 964         }
 965
 966         if (!(tmp_u1b & BIT(1)) && is92c) {
 967                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 968                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
 969         }
 970
 971         if (!(tmp_u1b & BIT(4))) {
 972                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 973                 tmp_u1b &= 0x0F;
 974                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 975                 udelay(10);
 976                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 977                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
 978         }
 979         rtl92c_dm_init(hw);
 980         rtlpci->being_init_adapter = false;
 981         return err;
 982 }
 983
 984 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
 985 {
 986         struct rtl_priv *rtlpriv = rtl_priv(hw);
 987         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 988         enum version_8192c version = VERSION_UNKNOWN;
 989         u32 value32;
 990         const char *versionid;
 991
 992         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
 993         if (value32 & TRP_VAUX_EN) {
 994                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
 995                            VERSION_A_CHIP_88C;
 996         } else {
 997                 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
 998                            VERSION_B_CHIP_88C;
 999         }
1000
1001         switch (version) {
1002         case VERSION_B_CHIP_92C:
1003                 versionid = "B_CHIP_92C";
1004                 break;
1005         case VERSION_B_CHIP_88C:
1006                 versionid = "B_CHIP_88C";
1007                 break;
1008         case VERSION_A_CHIP_92C:
1009                 versionid = "A_CHIP_92C";
1010                 break;
1011         case VERSION_A_CHIP_88C:
1012                 versionid = "A_CHIP_88C";
1013                 break;
1014         default:
1015                 versionid = "Unknown. Bug?";
1016                 break;
1017         }
1018
1019         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1020                  "Chip Version ID: %s\n", versionid);
1021
1022         switch (version & 0x3) {
1023         case CHIP_88C:
1024                 rtlphy->rf_type = RF_1T1R;
1025                 break;
1026         case CHIP_92C:
1027                 rtlphy->rf_type = RF_2T2R;
1028                 break;
1029         case CHIP_92C_1T2R:
1030                 rtlphy->rf_type = RF_1T2R;
1031                 break;
1032         default:
1033                 rtlphy->rf_type = RF_1T1R;
1034                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1035                          "ERROR RF_Type is set!!\n");
1036                 break;
1037         }
1038
1039         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1040                  rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1041
1042         return version;
1043 }
1044
1045 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1046                                      enum nl80211_iftype type)
1047 {
1048         struct rtl_priv *rtlpriv = rtl_priv(hw);
1049         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1050         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1051         bt_msr &= 0xfc;
1052
1053         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1054             type == NL80211_IFTYPE_STATION) {
1055                 _rtl92ce_stop_tx_beacon(hw);
1056                 _rtl92ce_enable_bcn_sub_func(hw);
1057         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1058                 _rtl92ce_resume_tx_beacon(hw);
1059                 _rtl92ce_disable_bcn_sub_func(hw);
1060         } else {
1061                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1062                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1063                          type);
1064         }
1065
1066         switch (type) {
1067         case NL80211_IFTYPE_UNSPECIFIED:
1068                 bt_msr |= MSR_NOLINK;
1069                 ledaction = LED_CTL_LINK;
1070                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1071                          "Set Network type to NO LINK!\n");
1072                 break;
1073         case NL80211_IFTYPE_ADHOC:
1074                 bt_msr |= MSR_ADHOC;
1075                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1076                          "Set Network type to Ad Hoc!\n");
1077                 break;
1078         case NL80211_IFTYPE_STATION:
1079                 bt_msr |= MSR_INFRA;
1080                 ledaction = LED_CTL_LINK;
1081                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1082                          "Set Network type to STA!\n");
1083                 break;
1084         case NL80211_IFTYPE_AP:
1085                 bt_msr |= MSR_AP;
1086                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1087                          "Set Network type to AP!\n");
1088                 break;
1089         default:
1090                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1091                          "Network type %d not supported!\n", type);
1092                 return 1;
1093                 break;
1094
1095         }
1096
1097         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1098         rtlpriv->cfg->ops->led_control(hw, ledaction);
1099         if ((bt_msr & 0xfc) == MSR_AP)
1100                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1101         else
1102                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1103         return 0;
1104 }
1105
1106 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1107 {
1108         struct rtl_priv *rtlpriv = rtl_priv(hw);
1109         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1110
1111         if (rtlpriv->psc.rfpwr_state != ERFON)
1112                 return;
1113
1114         if (check_bssid) {
1115                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1116                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1117                                               (u8 *) (&reg_rcr));
1118                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1119         } else if (!check_bssid) {
1120                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1121                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1122                 rtlpriv->cfg->ops->set_hw_reg(hw,
1123                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1124         }
1125
1126 }
1127
1128 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1129 {
1130         struct rtl_priv *rtlpriv = rtl_priv(hw);
1131
1132         if (_rtl92ce_set_media_status(hw, type))
1133                 return -EOPNOTSUPP;
1134
1135         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1136                 if (type != NL80211_IFTYPE_AP)
1137                         rtl92ce_set_check_bssid(hw, true);
1138         } else {
1139                 rtl92ce_set_check_bssid(hw, false);
1140         }
1141
1142         return 0;
1143 }
1144
1145 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1146 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1147 {
1148         struct rtl_priv *rtlpriv = rtl_priv(hw);
1149         rtl92c_dm_init_edca_turbo(hw);
1150         switch (aci) {
1151         case AC1_BK:
1152                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1153                 break;
1154         case AC0_BE:
1155                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1156                 break;
1157         case AC2_VI:
1158                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1159                 break;
1160         case AC3_VO:
1161                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1162                 break;
1163         default:
1164                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1165                 break;
1166         }
1167 }
1168
1169 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1170 {
1171         struct rtl_priv *rtlpriv = rtl_priv(hw);
1172         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1173
1174         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1175         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1176 }
1177
1178 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1179 {
1180         struct rtl_priv *rtlpriv = rtl_priv(hw);
1181         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1182
1183         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1184         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1185         synchronize_irq(rtlpci->pdev->irq);
1186 }
1187
1188 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1189 {
1190         struct rtl_priv *rtlpriv = rtl_priv(hw);
1191         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1192         u8 u1b_tmp;
1193         u32 u4b_tmp;
1194
1195         rtlpriv->intf_ops->enable_aspm(hw);
1196         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1197         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1198         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1199         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1200         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1201         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1202         if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1203                 rtl92c_firmware_selfreset(hw);
1204         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1205         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1206         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1207         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1208         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1209              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1210              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1211                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1212                                 (u1b_tmp << 8));
1213         } else {
1214                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1215                                 (u1b_tmp << 8));
1216         }
1217         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1218         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1219         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1220         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1221         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1222                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1223                 u4b_tmp |= 0x03824800;
1224                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1225         } else {
1226                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1227         }
1228
1229         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1230         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1231 }
1232
1233 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1234 {
1235         struct rtl_priv *rtlpriv = rtl_priv(hw);
1236         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1237         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1238         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1239         enum nl80211_iftype opmode;
1240
1241         mac->link_state = MAC80211_NOLINK;
1242         opmode = NL80211_IFTYPE_UNSPECIFIED;
1243         _rtl92ce_set_media_status(hw, opmode);
1244         if (rtlpci->driver_is_goingto_unload ||
1245             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1246                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1247         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1248         _rtl92ce_poweroff_adapter(hw);
1249 }
1250
1251 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1252                                   u32 *p_inta, u32 *p_intb)
1253 {
1254         struct rtl_priv *rtlpriv = rtl_priv(hw);
1255         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1256
1257         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1258         rtl_write_dword(rtlpriv, ISR, *p_inta);
1259
1260         /*
1261          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1262          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1263          */
1264 }
1265
1266 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1267 {
1268
1269         struct rtl_priv *rtlpriv = rtl_priv(hw);
1270         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1271         u16 bcn_interval, atim_window;
1272
1273         bcn_interval = mac->beacon_interval;
1274         atim_window = 2;        /*FIX MERGE */
1275         rtl92ce_disable_interrupt(hw);
1276         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1277         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1278         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1279         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1280         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1281         rtl_write_byte(rtlpriv, 0x606, 0x30);
1282         rtl92ce_enable_interrupt(hw);
1283 }
1284
1285 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1286 {
1287         struct rtl_priv *rtlpriv = rtl_priv(hw);
1288         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1289         u16 bcn_interval = mac->beacon_interval;
1290
1291         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1292                  "beacon_interval:%d\n", bcn_interval);
1293         rtl92ce_disable_interrupt(hw);
1294         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1295         rtl92ce_enable_interrupt(hw);
1296 }
1297
1298 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1299                                    u32 add_msr, u32 rm_msr)
1300 {
1301         struct rtl_priv *rtlpriv = rtl_priv(hw);
1302         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1303
1304         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1305                  add_msr, rm_msr);
1306
1307         if (add_msr)
1308                 rtlpci->irq_mask[0] |= add_msr;
1309         if (rm_msr)
1310                 rtlpci->irq_mask[0] &= (~rm_msr);
1311         rtl92ce_disable_interrupt(hw);
1312         rtl92ce_enable_interrupt(hw);
1313 }
1314
1315 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1316                                                  bool autoload_fail,
1317                                                  u8 *hwinfo)
1318 {
1319         struct rtl_priv *rtlpriv = rtl_priv(hw);
1320         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1321         u8 rf_path, index, tempval;
1322         u16 i;
1323
1324         for (rf_path = 0; rf_path < 2; rf_path++) {
1325                 for (i = 0; i < 3; i++) {
1326                         if (!autoload_fail) {
1327                                 rtlefuse->
1328                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1329                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1330                                 rtlefuse->
1331                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1332                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1333                                            i];
1334                         } else {
1335                                 rtlefuse->
1336                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1337                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1338                                 rtlefuse->
1339                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1340                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1341                         }
1342                 }
1343         }
1344
1345         for (i = 0; i < 3; i++) {
1346                 if (!autoload_fail)
1347                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1348                 else
1349                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1350                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1351                     (tempval & 0xf);
1352                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1353                     ((tempval & 0xf0) >> 4);
1354         }
1355
1356         for (rf_path = 0; rf_path < 2; rf_path++)
1357                 for (i = 0; i < 3; i++)
1358                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1359                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1360                                 rf_path, i,
1361                                 rtlefuse->
1362                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1363         for (rf_path = 0; rf_path < 2; rf_path++)
1364                 for (i = 0; i < 3; i++)
1365                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1366                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1367                                 rf_path, i,
1368                                 rtlefuse->
1369                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1370         for (rf_path = 0; rf_path < 2; rf_path++)
1371                 for (i = 0; i < 3; i++)
1372                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1373                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1374                                 rf_path, i,
1375                                 rtlefuse->
1376                                 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]);
1377
1378         for (rf_path = 0; rf_path < 2; rf_path++) {
1379                 for (i = 0; i < 14; i++) {
1380                         index = _rtl92c_get_chnl_group((u8) i);
1381
1382                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1383                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1384                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1385                             rtlefuse->
1386                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1387
1388                         if ((rtlefuse->
1389                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1390                              rtlefuse->
1391                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1392                             > 0) {
1393                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1394                                     rtlefuse->
1395                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1396                                     [index] -
1397                                     rtlefuse->
1398                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1399                                     [index];
1400                         } else {
1401                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1402                         }
1403                 }
1404
1405                 for (i = 0; i < 14; i++) {
1406                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1407                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1408                                 rf_path, i,
1409                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1410                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1411                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1412                 }
1413         }
1414
1415         for (i = 0; i < 3; i++) {
1416                 if (!autoload_fail) {
1417                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1418                             hwinfo[EEPROM_TXPWR_GROUP + i];
1419                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1420                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1421                 } else {
1422                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1423                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1424                 }
1425         }
1426
1427         for (rf_path = 0; rf_path < 2; rf_path++) {
1428                 for (i = 0; i < 14; i++) {
1429                         index = _rtl92c_get_chnl_group((u8) i);
1430
1431                         if (rf_path == RF90_PATH_A) {
1432                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1433                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1434                                      & 0xf);
1435                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1436                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1437                                      & 0xf);
1438                         } else if (rf_path == RF90_PATH_B) {
1439                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1440                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1441                                       & 0xf0) >> 4);
1442                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1443                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1444                                       & 0xf0) >> 4);
1445                         }
1446
1447                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1448                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1449                                 rf_path, i,
1450                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1451                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1452                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1453                                 rf_path, i,
1454                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1455                 }
1456         }
1457
1458         for (i = 0; i < 14; i++) {
1459                 index = _rtl92c_get_chnl_group((u8) i);
1460
1461                 if (!autoload_fail)
1462                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1463                 else
1464                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1465
1466                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1467                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1468                     ((tempval >> 4) & 0xF);
1469
1470                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1471                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1472
1473                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1474                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1475
1476                 index = _rtl92c_get_chnl_group((u8) i);
1477
1478                 if (!autoload_fail)
1479                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1480                 else
1481                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1482
1483                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1484                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1485                     ((tempval >> 4) & 0xF);
1486         }
1487
1488         rtlefuse->legacy_ht_txpowerdiff =
1489             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1490
1491         for (i = 0; i < 14; i++)
1492                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1493                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1494                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1495         for (i = 0; i < 14; i++)
1496                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1497                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1498                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1499         for (i = 0; i < 14; i++)
1500                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1501                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1502                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1503         for (i = 0; i < 14; i++)
1504                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1505                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1506                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1507
1508         if (!autoload_fail)
1509                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1510         else
1511                 rtlefuse->eeprom_regulatory = 0;
1512         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1513                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1514
1515         if (!autoload_fail) {
1516                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1517                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1518         } else {
1519                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1520                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1521         }
1522         RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1523                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1524                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1525
1526         if (!autoload_fail)
1527                 tempval = hwinfo[EEPROM_THERMAL_METER];
1528         else
1529                 tempval = EEPROM_DEFAULT_THERMALMETER;
1530         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1531
1532         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1533                 rtlefuse->apk_thermalmeterignore = true;
1534
1535         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1536         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1537                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1538 }
1539
1540 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1541 {
1542         struct rtl_priv *rtlpriv = rtl_priv(hw);
1543         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1544         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1545         u16 i, usvalue;
1546         u8 hwinfo[HWSET_MAX_SIZE];
1547         u16 eeprom_id;
1548
1549         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1550                 rtl_efuse_shadow_map_update(hw);
1551
1552                 memcpy((void *)hwinfo,
1553                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1554                        HWSET_MAX_SIZE);
1555         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1556                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1557                          "RTL819X Not boot from eeprom, check it !!");
1558         }
1559
1560         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1561                       hwinfo, HWSET_MAX_SIZE);
1562
1563         eeprom_id = *((u16 *)&hwinfo[0]);
1564         if (eeprom_id != RTL8190_EEPROM_ID) {
1565                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1566                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1567                 rtlefuse->autoload_failflag = true;
1568         } else {
1569                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1570                 rtlefuse->autoload_failflag = false;
1571         }
1572
1573         if (rtlefuse->autoload_failflag)
1574                 return;
1575
1576         for (i = 0; i < 6; i += 2) {
1577                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1578                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1579         }
1580
1581         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1582
1583         _rtl92ce_read_txpower_info_from_hwpg(hw,
1584                                              rtlefuse->autoload_failflag,
1585                                              hwinfo);
1586
1587         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1588                                                  rtlefuse->autoload_failflag,
1589                                                  hwinfo);
1590
1591         rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN];
1592         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1593         rtlefuse->txpwr_fromeprom = true;
1594         rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID];
1595
1596         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1597                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1598
1599         /* set channel paln to world wide 13 */
1600         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1601
1602         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1603                 switch (rtlefuse->eeprom_oemid) {
1604                 case EEPROM_CID_DEFAULT:
1605                         if (rtlefuse->eeprom_did == 0x8176) {
1606                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1607                                      rtlefuse->eeprom_smid == 0x1629))
1608                                         rtlhal->oem_id = RT_CID_819x_HP;
1609                                 else
1610                                         rtlhal->oem_id = RT_CID_DEFAULT;
1611                         } else {
1612                                 rtlhal->oem_id = RT_CID_DEFAULT;
1613                         }
1614                         break;
1615                 case EEPROM_CID_TOSHIBA:
1616                         rtlhal->oem_id = RT_CID_TOSHIBA;
1617                         break;
1618                 case EEPROM_CID_QMI:
1619                         rtlhal->oem_id = RT_CID_819x_QMI;
1620                         break;
1621                 case EEPROM_CID_WHQL:
1622                 default:
1623                         rtlhal->oem_id = RT_CID_DEFAULT;
1624                         break;
1625
1626                 }
1627         }
1628
1629 }
1630
1631 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1632 {
1633         struct rtl_priv *rtlpriv = rtl_priv(hw);
1634         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1635         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1636
1637         switch (rtlhal->oem_id) {
1638         case RT_CID_819x_HP:
1639                 pcipriv->ledctl.led_opendrain = true;
1640                 break;
1641         case RT_CID_819x_Lenovo:
1642         case RT_CID_DEFAULT:
1643         case RT_CID_TOSHIBA:
1644         case RT_CID_CCX:
1645         case RT_CID_819x_Acer:
1646         case RT_CID_WHQL:
1647         default:
1648                 break;
1649         }
1650         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1651                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1652 }
1653
1654 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1655 {
1656         struct rtl_priv *rtlpriv = rtl_priv(hw);
1657         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1658         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1659         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1660         u8 tmp_u1b;
1661
1662         rtlhal->version = _rtl92ce_read_chip_version(hw);
1663         if (get_rf_type(rtlphy) == RF_1T1R)
1664                 rtlpriv->dm.rfpath_rxenable[0] = true;
1665         else
1666                 rtlpriv->dm.rfpath_rxenable[0] =
1667                     rtlpriv->dm.rfpath_rxenable[1] = true;
1668         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1669                  rtlhal->version);
1670         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1671         if (tmp_u1b & BIT(4)) {
1672                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1673                 rtlefuse->epromtype = EEPROM_93C46;
1674         } else {
1675                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1676                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1677         }
1678         if (tmp_u1b & BIT(5)) {
1679                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1680                 rtlefuse->autoload_failflag = false;
1681                 _rtl92ce_read_adapter_info(hw);
1682         } else {
1683                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1684         }
1685         _rtl92ce_hal_customized_behavior(hw);
1686 }
1687
1688 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1689                 struct ieee80211_sta *sta)
1690 {
1691         struct rtl_priv *rtlpriv = rtl_priv(hw);
1692         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1693         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1694         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1695         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1696         u32 ratr_value;
1697         u8 ratr_index = 0;
1698         u8 nmode = mac->ht_enable;
1699         u8 mimo_ps = IEEE80211_SMPS_OFF;
1700         u16 shortgi_rate;
1701         u32 tmp_ratr_value;
1702         u8 curtxbw_40mhz = mac->bw_40;
1703         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1704                                1 : 0;
1705         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1706                                1 : 0;
1707         enum wireless_mode wirelessmode = mac->mode;
1708
1709         if (rtlhal->current_bandtype == BAND_ON_5G)
1710                 ratr_value = sta->supp_rates[1] << 4;
1711         else
1712                 ratr_value = sta->supp_rates[0];
1713         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1714                         sta->ht_cap.mcs.rx_mask[0] << 12);
1715         switch (wirelessmode) {
1716         case WIRELESS_MODE_B:
1717                 if (ratr_value & 0x0000000c)
1718                         ratr_value &= 0x0000000d;
1719                 else
1720                         ratr_value &= 0x0000000f;
1721                 break;
1722         case WIRELESS_MODE_G:
1723                 ratr_value &= 0x00000FF5;
1724                 break;
1725         case WIRELESS_MODE_N_24G:
1726         case WIRELESS_MODE_N_5G:
1727                 nmode = 1;
1728                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1729                         ratr_value &= 0x0007F005;
1730                 } else {
1731                         u32 ratr_mask;
1732
1733                         if (get_rf_type(rtlphy) == RF_1T2R ||
1734                             get_rf_type(rtlphy) == RF_1T1R)
1735                                 ratr_mask = 0x000ff005;
1736                         else
1737                                 ratr_mask = 0x0f0ff005;
1738
1739                         ratr_value &= ratr_mask;
1740                 }
1741                 break;
1742         default:
1743                 if (rtlphy->rf_type == RF_1T2R)
1744                         ratr_value &= 0x000ff0ff;
1745                 else
1746                         ratr_value &= 0x0f0ff0ff;
1747
1748                 break;
1749         }
1750
1751         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1752             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1753             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1754             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1755             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1756             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1757                 ratr_value &= 0x0fffcfc0;
1758         else
1759                 ratr_value &= 0x0FFFFFFF;
1760
1761         if (nmode && ((curtxbw_40mhz &&
1762                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1763                                                curshortgi_20mhz))) {
1764
1765                 ratr_value |= 0x10000000;
1766                 tmp_ratr_value = (ratr_value >> 12);
1767
1768                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1769                         if ((1 << shortgi_rate) & tmp_ratr_value)
1770                                 break;
1771                 }
1772
1773                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1774                     (shortgi_rate << 4) | (shortgi_rate);
1775         }
1776
1777         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1778
1779         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1780                  rtl_read_dword(rtlpriv, REG_ARFR0));
1781 }
1782
1783 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1784                 struct ieee80211_sta *sta, u8 rssi_level)
1785 {
1786         struct rtl_priv *rtlpriv = rtl_priv(hw);
1787         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1788         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1789         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1790         struct rtl_sta_info *sta_entry = NULL;
1791         u32 ratr_bitmap;
1792         u8 ratr_index;
1793         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1794                                 ? 1 : 0;
1795         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1796                                 1 : 0;
1797         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1798                                 1 : 0;
1799         enum wireless_mode wirelessmode = 0;
1800         bool shortgi = false;
1801         u8 rate_mask[5];
1802         u8 macid = 0;
1803         u8 mimo_ps = IEEE80211_SMPS_OFF;
1804
1805         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1806         wirelessmode = sta_entry->wireless_mode;
1807         if (mac->opmode == NL80211_IFTYPE_STATION)
1808                 curtxbw_40mhz = mac->bw_40;
1809         else if (mac->opmode == NL80211_IFTYPE_AP ||
1810                 mac->opmode == NL80211_IFTYPE_ADHOC)
1811                 macid = sta->aid + 1;
1812
1813         if (rtlhal->current_bandtype == BAND_ON_5G)
1814                 ratr_bitmap = sta->supp_rates[1] << 4;
1815         else
1816                 ratr_bitmap = sta->supp_rates[0];
1817         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1818                         sta->ht_cap.mcs.rx_mask[0] << 12);
1819         switch (wirelessmode) {
1820         case WIRELESS_MODE_B:
1821                 ratr_index = RATR_INX_WIRELESS_B;
1822                 if (ratr_bitmap & 0x0000000c)
1823                         ratr_bitmap &= 0x0000000d;
1824                 else
1825                         ratr_bitmap &= 0x0000000f;
1826                 break;
1827         case WIRELESS_MODE_G:
1828                 ratr_index = RATR_INX_WIRELESS_GB;
1829
1830                 if (rssi_level == 1)
1831                         ratr_bitmap &= 0x00000f00;
1832                 else if (rssi_level == 2)
1833                         ratr_bitmap &= 0x00000ff0;
1834                 else
1835                         ratr_bitmap &= 0x00000ff5;
1836                 break;
1837         case WIRELESS_MODE_A:
1838                 ratr_index = RATR_INX_WIRELESS_A;
1839                 ratr_bitmap &= 0x00000ff0;
1840                 break;
1841         case WIRELESS_MODE_N_24G:
1842         case WIRELESS_MODE_N_5G:
1843                 ratr_index = RATR_INX_WIRELESS_NGB;
1844
1845                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1846                         if (rssi_level == 1)
1847                                 ratr_bitmap &= 0x00070000;
1848                         else if (rssi_level == 2)
1849                                 ratr_bitmap &= 0x0007f000;
1850                         else
1851                                 ratr_bitmap &= 0x0007f005;
1852                 } else {
1853                         if (rtlphy->rf_type == RF_1T2R ||
1854                             rtlphy->rf_type == RF_1T1R) {
1855                                 if (curtxbw_40mhz) {
1856                                         if (rssi_level == 1)
1857                                                 ratr_bitmap &= 0x000f0000;
1858                                         else if (rssi_level == 2)
1859                                                 ratr_bitmap &= 0x000ff000;
1860                                         else
1861                                                 ratr_bitmap &= 0x000ff015;
1862                                 } else {
1863                                         if (rssi_level == 1)
1864                                                 ratr_bitmap &= 0x000f0000;
1865                                         else if (rssi_level == 2)
1866                                                 ratr_bitmap &= 0x000ff000;
1867                                         else
1868                                                 ratr_bitmap &= 0x000ff005;
1869                                 }
1870                         } else {
1871                                 if (curtxbw_40mhz) {
1872                                         if (rssi_level == 1)
1873                                                 ratr_bitmap &= 0x0f0f0000;
1874                                         else if (rssi_level == 2)
1875                                                 ratr_bitmap &= 0x0f0ff000;
1876                                         else
1877                                                 ratr_bitmap &= 0x0f0ff015;
1878                                 } else {
1879                                         if (rssi_level == 1)
1880                                                 ratr_bitmap &= 0x0f0f0000;
1881                                         else if (rssi_level == 2)
1882                                                 ratr_bitmap &= 0x0f0ff000;
1883                                         else
1884                                                 ratr_bitmap &= 0x0f0ff005;
1885                                 }
1886                         }
1887                 }
1888
1889                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1890                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1891
1892                         if (macid == 0)
1893                                 shortgi = true;
1894                         else if (macid == 1)
1895                                 shortgi = false;
1896                 }
1897                 break;
1898         default:
1899                 ratr_index = RATR_INX_WIRELESS_NGB;
1900
1901                 if (rtlphy->rf_type == RF_1T2R)
1902                         ratr_bitmap &= 0x000ff0ff;
1903                 else
1904                         ratr_bitmap &= 0x0f0ff0ff;
1905                 break;
1906         }
1907         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1908                  "ratr_bitmap :%x\n", ratr_bitmap);
1909         *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1910                                      (ratr_index << 28));
1911         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1912         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1913                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
1914                  ratr_index, ratr_bitmap,
1915                  rate_mask[0], rate_mask[1], rate_mask[2], rate_mask[3],
1916                  rate_mask[4]);
1917         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1918
1919         if (macid != 0)
1920                 sta_entry->ratr_index = ratr_index;
1921 }
1922
1923 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1924                 struct ieee80211_sta *sta, u8 rssi_level)
1925 {
1926         struct rtl_priv *rtlpriv = rtl_priv(hw);
1927
1928         if (rtlpriv->dm.useramask)
1929                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1930         else
1931                 rtl92ce_update_hal_rate_table(hw, sta);
1932 }
1933
1934 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1935 {
1936         struct rtl_priv *rtlpriv = rtl_priv(hw);
1937         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1938         u16 sifs_timer;
1939
1940         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1941                                       &mac->slot_time);
1942         if (!mac->ht_enable)
1943                 sifs_timer = 0x0a0a;
1944         else
1945                 sifs_timer = 0x1010;
1946         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1947 }
1948
1949 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1950 {
1951         struct rtl_priv *rtlpriv = rtl_priv(hw);
1952         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1953         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1954         enum rf_pwrstate e_rfpowerstate_toset;
1955         u8 u1tmp;
1956         bool actuallyset = false;
1957         unsigned long flag;
1958
1959         if (rtlpci->being_init_adapter)
1960                 return false;
1961
1962         if (ppsc->swrf_processing)
1963                 return false;
1964
1965         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1966         if (ppsc->rfchange_inprogress) {
1967                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1968                 return false;
1969         } else {
1970                 ppsc->rfchange_inprogress = true;
1971                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1972         }
1973
1974         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1975                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
1976
1977         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1978         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1979
1980         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
1981                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1982                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
1983
1984                 e_rfpowerstate_toset = ERFON;
1985                 ppsc->hwradiooff = false;
1986                 actuallyset = true;
1987         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
1988                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1989                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
1990
1991                 e_rfpowerstate_toset = ERFOFF;
1992                 ppsc->hwradiooff = true;
1993                 actuallyset = true;
1994         }
1995
1996         if (actuallyset) {
1997                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1998                 ppsc->rfchange_inprogress = false;
1999                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2000         } else {
2001                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2002                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2003
2004                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2005                 ppsc->rfchange_inprogress = false;
2006                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2007         }
2008
2009         *valid = 1;
2010         return !ppsc->hwradiooff;
2011
2012 }
2013
2014 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2015                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2016                      bool is_wepkey, bool clear_all)
2017 {
2018         struct rtl_priv *rtlpriv = rtl_priv(hw);
2019         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2020         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2021         u8 *macaddr = p_macaddr;
2022         u32 entry_id = 0;
2023         bool is_pairwise = false;
2024
2025         static u8 cam_const_addr[4][6] = {
2026                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2027                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2028                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2029                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2030         };
2031         static u8 cam_const_broad[] = {
2032                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2033         };
2034
2035         if (clear_all) {
2036                 u8 idx = 0;
2037                 u8 cam_offset = 0;
2038                 u8 clear_number = 5;
2039
2040                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2041
2042                 for (idx = 0; idx < clear_number; idx++) {
2043                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2044                         rtl_cam_empty_entry(hw, cam_offset + idx);
2045
2046                         if (idx < 5) {
2047                                 memset(rtlpriv->sec.key_buf[idx], 0,
2048                                        MAX_KEY_LEN);
2049                                 rtlpriv->sec.key_len[idx] = 0;
2050                         }
2051                 }
2052
2053         } else {
2054                 switch (enc_algo) {
2055                 case WEP40_ENCRYPTION:
2056                         enc_algo = CAM_WEP40;
2057                         break;
2058                 case WEP104_ENCRYPTION:
2059                         enc_algo = CAM_WEP104;
2060                         break;
2061                 case TKIP_ENCRYPTION:
2062                         enc_algo = CAM_TKIP;
2063                         break;
2064                 case AESCCMP_ENCRYPTION:
2065                         enc_algo = CAM_AES;
2066                         break;
2067                 default:
2068                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2069                                  "switch case not processed\n");
2070                         enc_algo = CAM_TKIP;
2071                         break;
2072                 }
2073
2074                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2075                         macaddr = cam_const_addr[key_index];
2076                         entry_id = key_index;
2077                 } else {
2078                         if (is_group) {
2079                                 macaddr = cam_const_broad;
2080                                 entry_id = key_index;
2081                         } else {
2082                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2083                                         entry_id = rtl_cam_get_free_entry(hw,
2084                                                                  p_macaddr);
2085                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2086                                                 RT_TRACE(rtlpriv, COMP_SEC,
2087                                                          DBG_EMERG,
2088                                                          "Can not find free hw security cam entry\n");
2089                                                 return;
2090                                         }
2091                                 } else {
2092                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2093                                 }
2094
2095                                 key_index = PAIRWISE_KEYIDX;
2096                                 is_pairwise = true;
2097                         }
2098                 }
2099
2100                 if (rtlpriv->sec.key_len[key_index] == 0) {
2101                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2102                                  "delete one entry, entry_id is %d\n",
2103                                  entry_id);
2104                         if (mac->opmode == NL80211_IFTYPE_AP)
2105                                 rtl_cam_del_entry(hw, p_macaddr);
2106                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2107                 } else {
2108                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2109                                  "The insert KEY length is %d\n",
2110                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2111                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2112                                  "The insert KEY is %x %x\n",
2113                                  rtlpriv->sec.key_buf[0][0],
2114                                  rtlpriv->sec.key_buf[0][1]);
2115
2116                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2117                                  "add one entry\n");
2118                         if (is_pairwise) {
2119                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2120                                               "Pairwise Key content",
2121                                               rtlpriv->sec.pairwise_key,
2122                                               rtlpriv->sec.
2123                                               key_len[PAIRWISE_KEYIDX]);
2124
2125                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2126                                          "set Pairwise key\n");
2127
2128                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2129                                                       entry_id, enc_algo,
2130                                                       CAM_CONFIG_NO_USEDK,
2131                                                       rtlpriv->sec.
2132                                                       key_buf[key_index]);
2133                         } else {
2134                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2135                                          "set group key\n");
2136
2137                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2138                                         rtl_cam_add_one_entry(hw,
2139                                                 rtlefuse->dev_addr,
2140                                                 PAIRWISE_KEYIDX,
2141                                                 CAM_PAIRWISE_KEY_POSITION,
2142                                                 enc_algo,
2143                                                 CAM_CONFIG_NO_USEDK,
2144                                                 rtlpriv->sec.key_buf
2145                                                 [entry_id]);
2146                                 }
2147
2148                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2149                                                 entry_id, enc_algo,
2150                                                 CAM_CONFIG_NO_USEDK,
2151                                                 rtlpriv->sec.key_buf[entry_id]);
2152                         }
2153
2154                 }
2155         }
2156 }
2157
2158 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2159 {
2160         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2161
2162         rtlpcipriv->bt_coexist.bt_coexistence =
2163                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2164         rtlpcipriv->bt_coexist.bt_ant_num =
2165                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2166         rtlpcipriv->bt_coexist.bt_coexist_type =
2167                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2168
2169         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2170                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2171                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2172         else
2173                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2174                         rtlpcipriv->bt_coexist.reg_bt_iso;
2175
2176         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2177                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2178
2179         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2180
2181                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2182                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2183                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2184                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2185                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2186                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2187                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2188                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2189                 else
2190                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2191
2192                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2193                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2194                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2195         }
2196 }
2197
2198 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2199                                               bool auto_load_fail, u8 *hwinfo)
2200 {
2201         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2202         u8 value;
2203
2204         if (!auto_load_fail) {
2205                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2206                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2207                 value = hwinfo[RF_OPTION4];
2208                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2209                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2210                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2211                                                          ((value & 0x10) >> 4);
2212                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2213                                                          ((value & 0x20) >> 5);
2214         } else {
2215                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2216                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2217                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2218                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2219                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2220         }
2221
2222         rtl8192ce_bt_var_init(hw);
2223 }
2224
2225 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2226 {
2227         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2228
2229         /* 0:Low, 1:High, 2:From Efuse. */
2230         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2231         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2232         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2233         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2234         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2235 }
2236
2237
2238 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2239 {
2240         struct rtl_priv *rtlpriv = rtl_priv(hw);
2241         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2242         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2243
2244         u8 u1_tmp;
2245
2246         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2247             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2248               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2249
2250                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2251                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2252
2253                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2254                          BIT_OFFSET_LEN_MASK_32(0, 1);
2255                 u1_tmp = u1_tmp |
2256                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2257                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2258                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2259                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2260                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2261
2262                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2263                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2264                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2265
2266                 /* Config to 1T1R. */
2267                 if (rtlphy->rf_type == RF_1T1R) {
2268                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2269                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2270                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2271
2272                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2273                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2274                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2275                 }
2276         }
2277 }
2278
2279 void rtl92ce_suspend(struct ieee80211_hw *hw)
2280 {
2281 }
2282
2283 void rtl92ce_resume(struct ieee80211_hw *hw)
2284 {
2285 }