drivers/net/wireless/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include "../wifi.h"
  33 #include "../efuse.h"
  34 #include "../base.h"
  35 #include "../cam.h"
  36 #include "../ps.h"
  37 #include "../usb.h"
  38 #include "reg.h"
  39 #include "def.h"
  40 #include "phy.h"
  41 #include "mac.h"
  42 #include "dm.h"
  43 #include "hw.h"
  44 #include "../rtl8192ce/hw.h"
  45 #include "trx.h"
  46 #include "led.h"
  47 #include "table.h"
  48
  49 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  53         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  54
  55         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  56         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  57         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  58                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  59                         RTL8192CUPHY_REG_Array_PG_HPLength;
  60                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  61                         RTL8192CUPHY_REG_Array_PG_HP;
  62         } else {
  63                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  64                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  65                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  66                         RTL8192CUPHY_REG_ARRAY_PG;
  67         }
  68         /* 2T */
  69         rtlphy->hwparam_tables[PHY_REG_2T].length =
  70                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  71         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  72                         RTL8192CUPHY_REG_2TARRAY;
  73         rtlphy->hwparam_tables[RADIOA_2T].length =
  74                         RTL8192CURADIOA_2TARRAYLENGTH;
  75         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  76                         RTL8192CURADIOA_2TARRAY;
  77         rtlphy->hwparam_tables[RADIOB_2T].length =
  78                         RTL8192CURADIOB_2TARRAYLENGTH;
  79         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  80                         RTL8192CU_RADIOB_2TARRAY;
  81         rtlphy->hwparam_tables[AGCTAB_2T].length =
  82                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  83         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  84                         RTL8192CUAGCTAB_2TARRAY;
  85         /* 1T */
  86         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  87                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  88                         RTL8192CUPHY_REG_1T_HPArrayLength;
  89                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  90                         RTL8192CUPHY_REG_1T_HPArray;
  91                 rtlphy->hwparam_tables[RADIOA_1T].length =
  92                         RTL8192CURadioA_1T_HPArrayLength;
  93                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  94                         RTL8192CURadioA_1T_HPArray;
  95                 rtlphy->hwparam_tables[RADIOB_1T].length =
  96                         RTL8192CURADIOB_1TARRAYLENGTH;
  97                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  98                         RTL8192CU_RADIOB_1TARRAY;
  99                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 100                         RTL8192CUAGCTAB_1T_HPArrayLength;
 101                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 102                         Rtl8192CUAGCTAB_1T_HPArray;
 103         } else {
 104                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 105                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 106                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 107                         RTL8192CUPHY_REG_1TARRAY;
 108                 rtlphy->hwparam_tables[RADIOA_1T].length =
 109                         RTL8192CURADIOA_1TARRAYLENGTH;
 110                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 111                         RTL8192CU_RADIOA_1TARRAY;
 112                 rtlphy->hwparam_tables[RADIOB_1T].length =
 113                         RTL8192CURADIOB_1TARRAYLENGTH;
 114                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 115                         RTL8192CU_RADIOB_1TARRAY;
 116                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 117                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 118                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 119                         RTL8192CUAGCTAB_1TARRAY;
 120         }
 121 }
 122
 123 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 124                                                  bool autoload_fail,
 125                                                  u8 *hwinfo)
 126 {
 127         struct rtl_priv *rtlpriv = rtl_priv(hw);
 128         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 129         u8 rf_path, index, tempval;
 130         u16 i;
 131
 132         for (rf_path = 0; rf_path < 2; rf_path++) {
 133                 for (i = 0; i < 3; i++) {
 134                         if (!autoload_fail) {
 135                                 rtlefuse->
 136                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 137                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 138                                 rtlefuse->
 139                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 140                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 141                                            i];
 142                         } else {
 143                                 rtlefuse->
 144                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 145                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 146                                 rtlefuse->
 147                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 148                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 149                         }
 150                 }
 151         }
 152         for (i = 0; i < 3; i++) {
 153                 if (!autoload_fail)
 154                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 155                 else
 156                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 157                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
 158                     (tempval & 0xf);
 159                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
 160                     ((tempval & 0xf0) >> 4);
 161         }
 162         for (rf_path = 0; rf_path < 2; rf_path++)
 163                 for (i = 0; i < 3; i++)
 164                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 165                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
 166                                 rf_path, i,
 167                                 rtlefuse->
 168                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
 169         for (rf_path = 0; rf_path < 2; rf_path++)
 170                 for (i = 0; i < 3; i++)
 171                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 172                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 173                                 rf_path, i,
 174                                 rtlefuse->
 175                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
 176         for (rf_path = 0; rf_path < 2; rf_path++)
 177                 for (i = 0; i < 3; i++)
 178                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 179                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 180                                 rf_path, i,
 181                                 rtlefuse->
 182                                 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]);
 183         for (rf_path = 0; rf_path < 2; rf_path++) {
 184                 for (i = 0; i < 14; i++) {
 185                         index = _rtl92c_get_chnl_group((u8) i);
 186                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 187                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 188                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 189                             rtlefuse->
 190                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 191                         if ((rtlefuse->
 192                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 193                              rtlefuse->
 194                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
 195                             > 0) {
 196                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 197                                     rtlefuse->
 198                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 199                                     [index] - rtlefuse->
 200                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 201                                     [index];
 202                         } else {
 203                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 204                         }
 205                 }
 206                 for (i = 0; i < 14; i++) {
 207                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 208                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
 209                                 rtlefuse->txpwrlevel_cck[rf_path][i],
 210                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 211                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
 212                 }
 213         }
 214         for (i = 0; i < 3; i++) {
 215                 if (!autoload_fail) {
 216                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 217                             hwinfo[EEPROM_TXPWR_GROUP + i];
 218                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 219                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 220                 } else {
 221                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 222                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 223                 }
 224         }
 225         for (rf_path = 0; rf_path < 2; rf_path++) {
 226                 for (i = 0; i < 14; i++) {
 227                         index = _rtl92c_get_chnl_group((u8) i);
 228                         if (rf_path == RF90_PATH_A) {
 229                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 230                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 231                                      & 0xf);
 232                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 233                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 234                                      & 0xf);
 235                         } else if (rf_path == RF90_PATH_B) {
 236                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 237                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 238                                       & 0xf0) >> 4);
 239                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 240                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 241                                       & 0xf0) >> 4);
 242                         }
 243                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 244                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 245                                 rf_path, i,
 246                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
 247                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 248                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 249                                 rf_path, i,
 250                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
 251                 }
 252         }
 253         for (i = 0; i < 14; i++) {
 254                 index = _rtl92c_get_chnl_group((u8) i);
 255                 if (!autoload_fail)
 256                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 257                 else
 258                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 259                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 260                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 261                     ((tempval >> 4) & 0xF);
 262                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 263                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 264                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 265                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 266                 index = _rtl92c_get_chnl_group((u8) i);
 267                 if (!autoload_fail)
 268                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 269                 else
 270                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 271                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 272                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 273                     ((tempval >> 4) & 0xF);
 274         }
 275         rtlefuse->legacy_ht_txpowerdiff =
 276             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 277         for (i = 0; i < 14; i++)
 278                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 279                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
 280                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
 281         for (i = 0; i < 14; i++)
 282                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 283                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
 284                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
 285         for (i = 0; i < 14; i++)
 286                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 287                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
 288                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
 289         for (i = 0; i < 14; i++)
 290                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 291                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
 292                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
 293         if (!autoload_fail)
 294                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 295         else
 296                 rtlefuse->eeprom_regulatory = 0;
 297         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 298                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
 299         if (!autoload_fail) {
 300                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 301                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 302         } else {
 303                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 304                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 305         }
 306         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 307                 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 308                 rtlefuse->eeprom_tssi[RF90_PATH_A],
 309                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
 310         if (!autoload_fail)
 311                 tempval = hwinfo[EEPROM_THERMAL_METER];
 312         else
 313                 tempval = EEPROM_DEFAULT_THERMALMETER;
 314         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 315         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 316             rtlefuse->eeprom_thermalmeter > 0x1c)
 317                 rtlefuse->eeprom_thermalmeter = 0x12;
 318         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 319                 rtlefuse->apk_thermalmeterignore = true;
 320         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 321         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 322                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
 323 }
 324
 325 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 326 {
 327         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 328         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 329         u8 boardType;
 330
 331         if (IS_NORMAL_CHIP(rtlhal->version)) {
 332                 boardType = ((contents[EEPROM_RF_OPT1]) &
 333                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 334         } else {
 335                 boardType = contents[EEPROM_RF_OPT4];
 336                 boardType &= BOARD_TYPE_TEST_MASK;
 337         }
 338         rtlefuse->board_type = boardType;
 339         if (IS_HIGHT_PA(rtlefuse->board_type))
 340                 rtlefuse->external_pa = 1;
 341         pr_info("Board Type %x\n", rtlefuse->board_type);
 342
 343 #ifdef CONFIG_ANTENNA_DIVERSITY
 344         /* Antenna Diversity setting. */
 345         if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
 346                 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
 347         else
 348                 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
 349
 350         pr_info("Antenna Config %x\n", rtl_efuse->antenna_cfg);
 351 #endif
 352 }
 353
 354 #ifdef CONFIG_BT_COEXIST
 355 static void _update_bt_param(_adapter *padapter)
 356 {
 357         struct btcoexist_priv    *pbtpriv = &(padapter->halpriv.bt_coexist);
 358         struct registry_priv    *registry_par = &padapter->registrypriv;
 359         if (2 != registry_par->bt_iso) {
 360                 /* 0:Low, 1:High, 2:From Efuse */
 361                 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
 362         }
 363         if (registry_par->bt_sco == 1) {
 364                 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
 365                  * 5.OtherBusy */
 366                 pbtpriv->BT_Service = BT_OtherAction;
 367         } else if (registry_par->bt_sco == 2) {
 368                 pbtpriv->BT_Service = BT_SCO;
 369         } else if (registry_par->bt_sco == 4) {
 370                 pbtpriv->BT_Service = BT_Busy;
 371         } else if (registry_par->bt_sco == 5) {
 372                 pbtpriv->BT_Service = BT_OtherBusy;
 373         } else {
 374                 pbtpriv->BT_Service = BT_Idle;
 375         }
 376         pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
 377         pbtpriv->bCOBT = _TRUE;
 378         pbtpriv->BtEdcaUL = 0;
 379         pbtpriv->BtEdcaDL = 0;
 380         pbtpriv->BtRssiState = 0xff;
 381         pbtpriv->bInitSet = _FALSE;
 382         pbtpriv->bBTBusyTraffic = _FALSE;
 383         pbtpriv->bBTTrafficModeSet = _FALSE;
 384         pbtpriv->bBTNonTrafficModeSet = _FALSE;
 385         pbtpriv->CurrentState = 0;
 386         pbtpriv->PreviousState = 0;
 387         pr_info("BT Coexistance = %s\n",
 388                 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
 389         if (pbtpriv->BT_Coexist) {
 390                 if (pbtpriv->BT_Ant_Num == Ant_x2)
 391                         pr_info("BlueTooth BT_Ant_Num = Antx2\n");
 392                 else if (pbtpriv->BT_Ant_Num == Ant_x1)
 393                         pr_info("BlueTooth BT_Ant_Num = Antx1\n");
 394                 switch (pbtpriv->BT_CoexistType) {
 395                 case BT_2Wire:
 396                         pr_info("BlueTooth BT_CoexistType = BT_2Wire\n");
 397                         break;
 398                 case BT_ISSC_3Wire:
 399                         pr_info("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
 400                         break;
 401                 case BT_Accel:
 402                         pr_info("BlueTooth BT_CoexistType = BT_Accel\n");
 403                         break;
 404                 case BT_CSR_BC4:
 405                         pr_info("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
 406                         break;
 407                 case BT_CSR_BC8:
 408                         pr_info("BlueTooth BT_CoexistType = BT_CSR_BC8\n");
 409                         break;
 410                 case BT_RTL8756:
 411                         pr_info("BlueTooth BT_CoexistType = BT_RTL8756\n");
 412                         break;
 413                 default:
 414                         pr_info("BlueTooth BT_CoexistType = Unknown\n");
 415                         break;
 416                 }
 417                 pr_info("BlueTooth BT_Ant_isolation = %d\n",
 418                         pbtpriv->BT_Ant_isolation);
 419                 switch (pbtpriv->BT_Service) {
 420                 case BT_OtherAction:
 421                         pr_info("BlueTooth BT_Service = BT_OtherAction\n");
 422                         break;
 423                 case BT_SCO:
 424                         pr_info("BlueTooth BT_Service = BT_SCO\n");
 425                         break;
 426                 case BT_Busy:
 427                         pr_info("BlueTooth BT_Service = BT_Busy\n");
 428                         break;
 429                 case BT_OtherBusy:
 430                         pr_info("BlueTooth BT_Service = BT_OtherBusy\n");
 431                         break;
 432                 default:
 433                         pr_info("BlueTooth BT_Service = BT_Idle\n");
 434                         break;
 435                 }
 436                 pr_info("BT_RadioSharedType = 0x%x\n",
 437                         pbtpriv->BT_RadioSharedType);
 438         }
 439 }
 440
 441 #define GET_BT_COEXIST(priv) (&priv->bt_coexist)
 442
 443 static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
 444                                                 u8 *contents,
 445                                                 bool bautoloadfailed);
 446 {
 447         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 448         bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
 449         struct btcoexist_priv    *pbtpriv = &pHalData->bt_coexist;
 450         u8      rf_opt4;
 451
 452         _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
 453         if (AutoloadFail) {
 454                 pbtpriv->BT_Coexist = _FALSE;
 455                 pbtpriv->BT_CoexistType = BT_2Wire;
 456                 pbtpriv->BT_Ant_Num = Ant_x2;
 457                 pbtpriv->BT_Ant_isolation = 0;
 458                 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
 459                 return;
 460         }
 461         if (isNormal) {
 462                 if (pHalData->BoardType == BOARD_USB_COMBO)
 463                         pbtpriv->BT_Coexist = _TRUE;
 464                 else
 465                         pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
 466                                               0x20) >> 5); /* bit[5] */
 467                 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
 468                 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
 469                 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
 470                 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
 471                 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
 472         } else {
 473                 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
 474                                        _TRUE : _FALSE;
 475         }
 476         _update_bt_param(Adapter);
 477 }
 478 #endif
 479
 480 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 481 {
 482         struct rtl_priv *rtlpriv = rtl_priv(hw);
 483         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 484         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 485         u16 i, usvalue;
 486         u8 hwinfo[HWSET_MAX_SIZE] = {0};
 487         u16 eeprom_id;
 488
 489         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 490                 rtl_efuse_shadow_map_update(hw);
 491                 memcpy((void *)hwinfo,
 492                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
 493                        HWSET_MAX_SIZE);
 494         } else if (rtlefuse->epromtype == EEPROM_93C46) {
 495                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 496                          "RTL819X Not boot from eeprom, check it !!\n");
 497         }
 498         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
 499                       hwinfo, HWSET_MAX_SIZE);
 500         eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
 501         if (eeprom_id != RTL8190_EEPROM_ID) {
 502                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 503                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
 504                 rtlefuse->autoload_failflag = true;
 505         } else {
 506                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
 507                 rtlefuse->autoload_failflag = false;
 508         }
 509         if (rtlefuse->autoload_failflag)
 510                 return;
 511         for (i = 0; i < 6; i += 2) {
 512                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
 513                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
 514         }
 515         pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
 516         _rtl92cu_read_txpower_info_from_hwpg(hw,
 517                                            rtlefuse->autoload_failflag, hwinfo);
 518         rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
 519         rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
 520         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
 521                  rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
 522         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
 523         rtlefuse->eeprom_version =
 524                          le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
 525         rtlefuse->txpwr_fromeprom = true;
 526         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
 527         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
 528                  rtlefuse->eeprom_oemid);
 529         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 530                 switch (rtlefuse->eeprom_oemid) {
 531                 case EEPROM_CID_DEFAULT:
 532                         if (rtlefuse->eeprom_did == 0x8176) {
 533                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 534                                      rtlefuse->eeprom_smid == 0x1629))
 535                                         rtlhal->oem_id = RT_CID_819x_HP;
 536                                 else
 537                                         rtlhal->oem_id = RT_CID_DEFAULT;
 538                         } else {
 539                                 rtlhal->oem_id = RT_CID_DEFAULT;
 540                         }
 541                         break;
 542                 case EEPROM_CID_TOSHIBA:
 543                         rtlhal->oem_id = RT_CID_TOSHIBA;
 544                         break;
 545                 case EEPROM_CID_QMI:
 546                         rtlhal->oem_id = RT_CID_819x_QMI;
 547                         break;
 548                 case EEPROM_CID_WHQL:
 549                 default:
 550                         rtlhal->oem_id = RT_CID_DEFAULT;
 551                         break;
 552                 }
 553         }
 554         _rtl92cu_read_board_type(hw, hwinfo);
 555 #ifdef CONFIG_BT_COEXIST
 556         _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
 557                                             rtlefuse->autoload_failflag);
 558 #endif
 559 }
 560
 561 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 562 {
 563         struct rtl_priv *rtlpriv = rtl_priv(hw);
 564         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 565         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 566
 567         switch (rtlhal->oem_id) {
 568         case RT_CID_819x_HP:
 569                 usb_priv->ledctl.led_opendrain = true;
 570                 break;
 571         case RT_CID_819x_Lenovo:
 572         case RT_CID_DEFAULT:
 573         case RT_CID_TOSHIBA:
 574         case RT_CID_CCX:
 575         case RT_CID_819x_Acer:
 576         case RT_CID_WHQL:
 577         default:
 578                 break;
 579         }
 580         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
 581                  rtlhal->oem_id);
 582 }
 583
 584 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 585 {
 586
 587         struct rtl_priv *rtlpriv = rtl_priv(hw);
 588         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 589         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 590         u8 tmp_u1b;
 591
 592         if (!IS_NORMAL_CHIP(rtlhal->version))
 593                 return;
 594         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 595         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
 596                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 597         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
 598                  tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
 599         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 600         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
 601                  tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
 602         _rtl92cu_read_adapter_info(hw);
 603         _rtl92cu_hal_customized_behavior(hw);
 604         return;
 605 }
 606
 607 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 608 {
 609         struct rtl_priv *rtlpriv = rtl_priv(hw);
 610         int             status = 0;
 611         u16             value16;
 612         u8              value8;
 613         /*  polling autoload done. */
 614         u32     pollingCount = 0;
 615
 616         do {
 617                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 618                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 619                                  "Autoload Done!\n");
 620                         break;
 621                 }
 622                 if (pollingCount++ > 100) {
 623                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 624                                  "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
 625                         return -ENODEV;
 626                 }
 627         } while (true);
 628         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 629         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 630         /* Power on when re-enter from IPS/Radio off/card disable */
 631         /* enable SPS into PWM mode */
 632         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 633         udelay(100);
 634         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 635         if (0 == (value8 & LDV12_EN)) {
 636                 value8 |= LDV12_EN;
 637                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 638                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 639                          " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
 640                          value8);
 641                 udelay(100);
 642                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 643                 value8 &= ~ISO_MD2PP;
 644                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 645         }
 646         /*  auto enable WLAN */
 647         pollingCount = 0;
 648         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 649         value16 |= APFM_ONMAC;
 650         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 651         do {
 652                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 653                         pr_info("MAC auto ON okay!\n");
 654                         break;
 655                 }
 656                 if (pollingCount++ > 100) {
 657                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 658                                  "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
 659                         return -ENODEV;
 660                 }
 661         } while (true);
 662         /* Enable Radio ,GPIO ,and LED function */
 663         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 664         /* release RF digital isolation */
 665         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 666         value16 &= ~ISO_DIOR;
 667         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 668         /* Reconsider when to do this operation after asking HWSD. */
 669         pollingCount = 0;
 670         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 671                                                 REG_APSD_CTRL) & ~BIT(6)));
 672         do {
 673                 pollingCount++;
 674         } while ((pollingCount < 200) &&
 675                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 676         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 677         value16 = rtl_read_word(rtlpriv,  REG_CR);
 678         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 679                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 680         rtl_write_word(rtlpriv, REG_CR, value16);
 681         return status;
 682 }
 683
 684 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 685                                               bool wmm_enable,
 686                                               u8 out_ep_num,
 687                                               u8 queue_sel)
 688 {
 689         struct rtl_priv *rtlpriv = rtl_priv(hw);
 690         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 691         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 692         u32 outEPNum = (u32)out_ep_num;
 693         u32 numHQ = 0;
 694         u32 numLQ = 0;
 695         u32 numNQ = 0;
 696         u32 numPubQ;
 697         u32 value32;
 698         u8 value8;
 699         u32 txQPageNum, txQPageUnit, txQRemainPage;
 700
 701         if (!wmm_enable) {
 702                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 703                           CHIP_A_PAGE_NUM_PUBQ;
 704                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 705
 706                 txQPageUnit = txQPageNum/outEPNum;
 707                 txQRemainPage = txQPageNum % outEPNum;
 708                 if (queue_sel & TX_SELE_HQ)
 709                         numHQ = txQPageUnit;
 710                 if (queue_sel & TX_SELE_LQ)
 711                         numLQ = txQPageUnit;
 712                 /* HIGH priority queue always present in the configuration of
 713                  * 2 out-ep. Remainder pages have assigned to High queue */
 714                 if ((outEPNum > 1) && (txQRemainPage))
 715                         numHQ += txQRemainPage;
 716                 /* NOTE: This step done before writting REG_RQPN. */
 717                 if (isChipN) {
 718                         if (queue_sel & TX_SELE_NQ)
 719                                 numNQ = txQPageUnit;
 720                         value8 = (u8)_NPQ(numNQ);
 721                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 722                 }
 723         } else {
 724                 /* for WMM ,number of out-ep must more than or equal to 2! */
 725                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 726                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 727                 if (queue_sel & TX_SELE_HQ) {
 728                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 729                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 730                 }
 731                 if (queue_sel & TX_SELE_LQ) {
 732                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 733                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 734                 }
 735                 /* NOTE: This step done before writting REG_RQPN. */
 736                 if (isChipN) {
 737                         if (queue_sel & TX_SELE_NQ)
 738                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 739                         value8 = (u8)_NPQ(numNQ);
 740                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 741                 }
 742         }
 743         /* TX DMA */
 744         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 745         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 746 }
 747
 748 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 749 {
 750         struct rtl_priv *rtlpriv = rtl_priv(hw);
 751         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 752         u8      txpktbuf_bndy;
 753         u8      value8;
 754
 755         if (!wmm_enable)
 756                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 757         else /* for WMM */
 758                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 759                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 760                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 761         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 762         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 763         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 764         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 765         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 766         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 767         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 768         rtl_write_byte(rtlpriv, REG_PBP, value8);
 769 }
 770
 771 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 772                                             u16 bkQ, u16 viQ, u16 voQ,
 773                                             u16 mgtQ, u16 hiQ)
 774 {
 775         struct rtl_priv *rtlpriv = rtl_priv(hw);
 776         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 777
 778         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 779                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 780                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 781         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 782 }
 783
 784 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 785                                                     bool wmm_enable,
 786                                                     u8 queue_sel)
 787 {
 788         u16 uninitialized_var(value);
 789
 790         switch (queue_sel) {
 791         case TX_SELE_HQ:
 792                 value = QUEUE_HIGH;
 793                 break;
 794         case TX_SELE_LQ:
 795                 value = QUEUE_LOW;
 796                 break;
 797         case TX_SELE_NQ:
 798                 value = QUEUE_NORMAL;
 799                 break;
 800         default:
 801                 WARN_ON(1); /* Shall not reach here! */
 802                 break;
 803         }
 804         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 805                                         value, value);
 806         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 807 }
 808
 809 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 810                                                                 bool wmm_enable,
 811                                                                 u8 queue_sel)
 812 {
 813         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 814         u16 uninitialized_var(valueHi);
 815         u16 uninitialized_var(valueLow);
 816
 817         switch (queue_sel) {
 818         case (TX_SELE_HQ | TX_SELE_LQ):
 819                 valueHi = QUEUE_HIGH;
 820                 valueLow = QUEUE_LOW;
 821                 break;
 822         case (TX_SELE_NQ | TX_SELE_LQ):
 823                 valueHi = QUEUE_NORMAL;
 824                 valueLow = QUEUE_LOW;
 825                 break;
 826         case (TX_SELE_HQ | TX_SELE_NQ):
 827                 valueHi = QUEUE_HIGH;
 828                 valueLow = QUEUE_NORMAL;
 829                 break;
 830         default:
 831                 WARN_ON(1);
 832                 break;
 833         }
 834         if (!wmm_enable) {
 835                 beQ = valueLow;
 836                 bkQ = valueLow;
 837                 viQ = valueHi;
 838                 voQ = valueHi;
 839                 mgtQ = valueHi;
 840                 hiQ = valueHi;
 841         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 842                 beQ = valueHi;
 843                 bkQ = valueLow;
 844                 viQ = valueLow;
 845                 voQ = valueHi;
 846                 mgtQ = valueHi;
 847                 hiQ = valueHi;
 848         }
 849         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 850         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 851 }
 852
 853 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 854                                                       bool wmm_enable,
 855                                                       u8 queue_sel)
 856 {
 857         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 858         struct rtl_priv *rtlpriv = rtl_priv(hw);
 859
 860         if (!wmm_enable) { /* typical setting */
 861                 beQ     = QUEUE_LOW;
 862                 bkQ     = QUEUE_LOW;
 863                 viQ     = QUEUE_NORMAL;
 864                 voQ     = QUEUE_HIGH;
 865                 mgtQ    = QUEUE_HIGH;
 866                 hiQ     = QUEUE_HIGH;
 867         } else { /* for WMM */
 868                 beQ     = QUEUE_LOW;
 869                 bkQ     = QUEUE_NORMAL;
 870                 viQ     = QUEUE_NORMAL;
 871                 voQ     = QUEUE_HIGH;
 872                 mgtQ    = QUEUE_HIGH;
 873                 hiQ     = QUEUE_HIGH;
 874         }
 875         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 876         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 877                  queue_sel);
 878 }
 879
 880 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 881                                                bool wmm_enable,
 882                                                u8 out_ep_num,
 883                                                u8 queue_sel)
 884 {
 885         switch (out_ep_num) {
 886         case 1:
 887                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 888                                                         queue_sel);
 889                 break;
 890         case 2:
 891                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 892                                                         queue_sel);
 893                 break;
 894         case 3:
 895                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 896                                                           queue_sel);
 897                 break;
 898         default:
 899                 WARN_ON(1); /* Shall not reach here! */
 900                 break;
 901         }
 902 }
 903
 904 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 905                                                bool wmm_enable,
 906                                                u8 out_ep_num,
 907                                                u8 queue_sel)
 908 {
 909         u8 hq_sele = 0;
 910         struct rtl_priv *rtlpriv = rtl_priv(hw);
 911
 912         switch (out_ep_num) {
 913         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 914                 if (!wmm_enable) /* typical setting */
 915                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 916                                    HQSEL_HIQ;
 917                 else    /* for WMM */
 918                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 919                                   HQSEL_HIQ;
 920                 break;
 921         case 1:
 922                 if (TX_SELE_LQ == queue_sel) {
 923                         /* map all endpoint to Low queue */
 924                         hq_sele = 0;
 925                 } else if (TX_SELE_HQ == queue_sel) {
 926                         /* map all endpoint to High queue */
 927                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 928                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 929                 }
 930                 break;
 931         default:
 932                 WARN_ON(1); /* Shall not reach here! */
 933                 break;
 934         }
 935         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 936         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
 937                  hq_sele);
 938 }
 939
 940 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 941                                                 bool wmm_enable,
 942                                                 u8 out_ep_num,
 943                                                 u8 queue_sel)
 944 {
 945         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 946         if (IS_NORMAL_CHIP(rtlhal->version))
 947                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 948                                                    queue_sel);
 949         else
 950                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 951                                                    queue_sel);
 952 }
 953
 954 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
 955 {
 956 }
 957
 958 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 959 {
 960         u16                     value16;
 961
 962         struct rtl_priv *rtlpriv = rtl_priv(hw);
 963         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 964
 965         mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
 966                       RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 967                       RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 968         rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
 969         /* Accept all multicast address */
 970         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 971         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 972         /* Accept all management frames */
 973         value16 = 0xFFFF;
 974         rtl92c_set_mgt_filter(hw, value16);
 975         /* Reject all control frame - default value is 0 */
 976         rtl92c_set_ctrl_filter(hw, 0x0);
 977         /* Accept all data frames */
 978         value16 = 0xFFFF;
 979         rtl92c_set_data_filter(hw, value16);
 980 }
 981
 982 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 983 {
 984         struct rtl_priv *rtlpriv = rtl_priv(hw);
 985         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 986         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 987         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
 988         int err = 0;
 989         u32     boundary = 0;
 990         u8 wmm_enable = false; /* TODO */
 991         u8 out_ep_nums = rtlusb->out_ep_nums;
 992         u8 queue_sel = rtlusb->out_queue_sel;
 993         err = _rtl92cu_init_power_on(hw);
 994
 995         if (err) {
 996                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 997                          "Failed to init power on!\n");
 998                 return err;
 999         }
1000         if (!wmm_enable) {
1001                 boundary = TX_PAGE_BOUNDARY;
1002         } else { /* for WMM */
1003                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1004                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1005                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1006         }
1007         if (false == rtl92c_init_llt_table(hw, boundary)) {
1008                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1009                          "Failed to init LLT Table!\n");
1010                 return -EINVAL;
1011         }
1012         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1013                                           queue_sel);
1014         _rtl92c_init_trx_buffer(hw, wmm_enable);
1015         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1016                                      queue_sel);
1017         /* Get Rx PHY status in order to report RSSI and others. */
1018         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1019         rtl92c_init_interrupt(hw);
1020         rtl92c_init_network_type(hw);
1021         _rtl92cu_init_wmac_setting(hw);
1022         rtl92c_init_adaptive_ctrl(hw);
1023         rtl92c_init_edca(hw);
1024         rtl92c_init_rate_fallback(hw);
1025         rtl92c_init_retry_function(hw);
1026         _rtl92cu_init_usb_aggregation(hw);
1027         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1028         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1029         rtl92c_init_beacon_parameters(hw, rtlhal->version);
1030         rtl92c_init_ampdu_aggregation(hw);
1031         rtl92c_init_beacon_max_error(hw, true);
1032         return err;
1033 }
1034
1035 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1036 {
1037         struct rtl_priv *rtlpriv = rtl_priv(hw);
1038         u8 sec_reg_value = 0x0;
1039         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1040
1041         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1042                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1043                  rtlpriv->sec.pairwise_enc_algorithm,
1044                  rtlpriv->sec.group_enc_algorithm);
1045         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1046                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1047                          "not open sw encryption\n");
1048                 return;
1049         }
1050         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1051         if (rtlpriv->sec.use_defaultkey) {
1052                 sec_reg_value |= SCR_TxUseDK;
1053                 sec_reg_value |= SCR_RxUseDK;
1054         }
1055         if (IS_NORMAL_CHIP(rtlhal->version))
1056                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1057         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1058         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
1059                  sec_reg_value);
1060         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1061 }
1062
1063 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1064 {
1065         struct rtl_priv *rtlpriv = rtl_priv(hw);
1066         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1067
1068         /* To Fix MAC loopback mode fail. */
1069         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1070         rtl_write_byte(rtlpriv, 0x15, 0xe9);
1071         /* HW SEQ CTRL */
1072         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1073         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1074         /* fixed USB interface interference issue */
1075         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1076         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1077         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1078         rtlusb->reg_bcn_ctrl_val = 0x18;
1079         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1080 }
1081
1082 static void _InitPABias(struct ieee80211_hw *hw)
1083 {
1084         struct rtl_priv *rtlpriv = rtl_priv(hw);
1085         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1086         u8 pa_setting;
1087
1088         /* FIXED PA current issue */
1089         pa_setting = efuse_read_1byte(hw, 0x1FA);
1090         if (!(pa_setting & BIT(0))) {
1091                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1092                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1093                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1094                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1095         }
1096         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1097             IS_92C_SERIAL(rtlhal->version)) {
1098                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1099                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1100                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1101                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1102         }
1103         if (!(pa_setting & BIT(4))) {
1104                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1105                 pa_setting &= 0x0F;
1106                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1107         }
1108 }
1109
1110 static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1111 {
1112 #ifdef CONFIG_ANTENNA_DIVERSITY
1113         struct rtl_priv *rtlpriv = rtl_priv(hw);
1114         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1115         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1116
1117         if (pHalData->AntDivCfg == 0)
1118                 return;
1119
1120         if (rtlphy->rf_type == RF_1T1R) {
1121                 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1122                                 rtl_read_dword(rtlpriv,
1123                                 REG_LEDCFG0)|BIT(23));
1124                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1125                 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1126                     Antenna_A)
1127                         pHalData->CurAntenna = Antenna_A;
1128                 else
1129                         pHalData->CurAntenna = Antenna_B;
1130         }
1131 #endif
1132 }
1133
1134 static void _dump_registers(struct ieee80211_hw *hw)
1135 {
1136 }
1137
1138 static void _update_mac_setting(struct ieee80211_hw *hw)
1139 {
1140         struct rtl_priv *rtlpriv = rtl_priv(hw);
1141         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1142
1143         mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1144         mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1145         mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1146         mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1147 }
1148
1149 int rtl92cu_hw_init(struct ieee80211_hw *hw)
1150 {
1151         struct rtl_priv *rtlpriv = rtl_priv(hw);
1152         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1153         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1154         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1155         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1156         int err = 0;
1157         static bool iqk_initialized;
1158
1159         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1160         err = _rtl92cu_init_mac(hw);
1161         if (err) {
1162                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1163                 return err;
1164         }
1165         err = rtl92c_download_fw(hw);
1166         if (err) {
1167                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1168                          "Failed to download FW. Init HW without FW now..\n");
1169                 err = 1;
1170                 rtlhal->fw_ready = false;
1171                 return err;
1172         } else {
1173                 rtlhal->fw_ready = true;
1174         }
1175         rtlhal->last_hmeboxnum = 0; /* h2c */
1176         _rtl92cu_phy_param_tab_init(hw);
1177         rtl92cu_phy_mac_config(hw);
1178         rtl92cu_phy_bb_config(hw);
1179         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1180         rtl92c_phy_rf_config(hw);
1181         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1182             !IS_92C_SERIAL(rtlhal->version)) {
1183                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1184                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1185         }
1186         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1187                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1188         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1189                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1190         rtl92cu_bb_block_on(hw);
1191         rtl_cam_reset_all_entry(hw);
1192         rtl92cu_enable_hw_security_config(hw);
1193         ppsc->rfpwr_state = ERFON;
1194         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1195         if (ppsc->rfpwr_state == ERFON) {
1196                 rtl92c_phy_set_rfpath_switch(hw, 1);
1197                 if (iqk_initialized) {
1198                         rtl92c_phy_iq_calibrate(hw, false);
1199                 } else {
1200                         rtl92c_phy_iq_calibrate(hw, false);
1201                         iqk_initialized = true;
1202                 }
1203                 rtl92c_dm_check_txpower_tracking(hw);
1204                 rtl92c_phy_lc_calibrate(hw);
1205         }
1206         _rtl92cu_hw_configure(hw);
1207         _InitPABias(hw);
1208         _InitAntenna_Selection(hw);
1209         _update_mac_setting(hw);
1210         rtl92c_dm_init(hw);
1211         _dump_registers(hw);
1212         return err;
1213 }
1214
1215 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1216 {
1217         struct rtl_priv *rtlpriv = rtl_priv(hw);
1218 /**************************************
1219 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1220 b.      RF path 0 offset 0x00 = 0x00    disable RF
1221 c.      APSD_CTRL 0x600[7:0] = 0x40
1222 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1223 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1224 ***************************************/
1225         u8 eRFPath = 0, value8 = 0;
1226         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1227         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1228
1229         value8 |= APSDOFF;
1230         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1231         value8 = 0;
1232         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1233         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1234         value8 &= (~FEN_BB_GLB_RSTn);
1235         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1236 }
1237
1238 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1239 {
1240         struct rtl_priv *rtlpriv = rtl_priv(hw);
1241         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1242
1243         if (rtlhal->fw_version <=  0x20) {
1244                 /*****************************
1245                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1246                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1247                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1248                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1249                 ******************************/
1250                 u16 valu16 = 0;
1251
1252                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1253                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1254                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1255                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1256                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1257                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1258                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1259                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1260                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1261                                FEN_CPUEN)); /* enable MCU ,8051 */
1262         } else {
1263                 u8 retry_cnts = 0;
1264
1265                 /* IF fw in RAM code, do reset */
1266                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1267                         /* reset MCU ready status */
1268                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1269                         if (rtlhal->fw_ready) {
1270                                 /* 8051 reset by self */
1271                                 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1272                                 while ((retry_cnts++ < 100) &&
1273                                        (FEN_CPUEN & rtl_read_word(rtlpriv,
1274                                        REG_SYS_FUNC_EN))) {
1275                                         udelay(50);
1276                                 }
1277                                 if (retry_cnts >= 100) {
1278                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1279                                                  "#####=> 8051 reset failed!.........................\n");
1280                                         /* if 8051 reset fail, reset MAC. */
1281                                         rtl_write_byte(rtlpriv,
1282                                                        REG_SYS_FUNC_EN + 1,
1283                                                        0x50);
1284                                         udelay(100);
1285                                 }
1286                         }
1287                 }
1288                 /* Reset MAC and Enable 8051 */
1289                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1290                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1291         }
1292         if (bWithoutHWSM) {
1293                 /*****************************
1294                   Without HW auto state machine
1295                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1296                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1297                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1298                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1299                 ******************************/
1300                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1301                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1302                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1303                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1304         }
1305 }
1306
1307 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1308 {
1309         struct rtl_priv *rtlpriv = rtl_priv(hw);
1310 /*****************************
1311 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1312 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1313 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1314 ******************************/
1315         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1316         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1317 }
1318
1319 static void _DisableGPIO(struct ieee80211_hw *hw)
1320 {
1321         struct rtl_priv *rtlpriv = rtl_priv(hw);
1322 /***************************************
1323 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1324 k. Value = GPIO_PIN_CTRL[7:0]
1325 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1326 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1327 n. LEDCFG 0x4C[15:0] = 0x8080
1328 ***************************************/
1329         u8      value8;
1330         u16     value16;
1331         u32     value32;
1332
1333         /* 1. Disable GPIO[7:0] */
1334         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1335         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1336         value8 = (u8) (value32&0x000000FF);
1337         value32 |= ((value8<<8) | 0x00FF0000);
1338         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1339         /* 2. Disable GPIO[10:8] */
1340         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1341         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1342         value8 = (u8) (value16&0x000F);
1343         value16 |= ((value8<<4) | 0x0780);
1344         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1345         /* 3. Disable LED0 & 1 */
1346         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1347 }
1348
1349 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1350 {
1351         struct rtl_priv *rtlpriv = rtl_priv(hw);
1352         u16 value16 = 0;
1353         u8 value8 = 0;
1354
1355         if (bWithoutHWSM) {
1356                 /*****************************
1357                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1358                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1359                 r. When driver call disable, the ASIC will turn off remaining
1360                    clock automatically
1361                 ******************************/
1362                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1363                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1364                 value8 &= (~LDV12_EN);
1365                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1366         }
1367
1368 /*****************************
1369 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1370 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1371 ******************************/
1372         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1373         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1374         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1375         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1376 }
1377
1378 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1379 {
1380         /* ==== RF Off Sequence ==== */
1381         _DisableRFAFEAndResetBB(hw);
1382         /* ==== Reset digital sequence   ====== */
1383         _ResetDigitalProcedure1(hw, false);
1384         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1385         _DisableGPIO(hw);
1386         /* ==== Disable analog sequence === */
1387         _DisableAnalog(hw, false);
1388 }
1389
1390 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1391 {
1392         /*==== RF Off Sequence ==== */
1393         _DisableRFAFEAndResetBB(hw);
1394         /*  ==== Reset digital sequence   ====== */
1395         _ResetDigitalProcedure1(hw, true);
1396         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1397         _DisableGPIO(hw);
1398         /*  ==== Reset digital sequence   ====== */
1399         _ResetDigitalProcedure2(hw);
1400         /*  ==== Disable analog sequence === */
1401         _DisableAnalog(hw, true);
1402 }
1403
1404 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1405                                       u8 set_bits, u8 clear_bits)
1406 {
1407         struct rtl_priv *rtlpriv = rtl_priv(hw);
1408         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1409
1410         rtlusb->reg_bcn_ctrl_val |= set_bits;
1411         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1412         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1413 }
1414
1415 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1416 {
1417         struct rtl_priv *rtlpriv = rtl_priv(hw);
1418         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1419         u8 tmp1byte = 0;
1420         if (IS_NORMAL_CHIP(rtlhal->version)) {
1421                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1422                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1423                                tmp1byte & (~BIT(6)));
1424                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1425                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1426                 tmp1byte &= ~(BIT(0));
1427                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1428         } else {
1429                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1430                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1431         }
1432 }
1433
1434 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1435 {
1436         struct rtl_priv *rtlpriv = rtl_priv(hw);
1437         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1438         u8 tmp1byte = 0;
1439
1440         if (IS_NORMAL_CHIP(rtlhal->version)) {
1441                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1442                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1443                                tmp1byte | BIT(6));
1444                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1445                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1446                 tmp1byte |= BIT(0);
1447                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1448         } else {
1449                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1450                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1451         }
1452 }
1453
1454 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1455 {
1456         struct rtl_priv *rtlpriv = rtl_priv(hw);
1457         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1458
1459         if (IS_NORMAL_CHIP(rtlhal->version))
1460                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1461         else
1462                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1463 }
1464
1465 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1466 {
1467         struct rtl_priv *rtlpriv = rtl_priv(hw);
1468         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1469
1470         if (IS_NORMAL_CHIP(rtlhal->version))
1471                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1472         else
1473                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1474 }
1475
1476 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1477                                      enum nl80211_iftype type)
1478 {
1479         struct rtl_priv *rtlpriv = rtl_priv(hw);
1480         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1481         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1482
1483         bt_msr &= 0xfc;
1484         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1485         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1486             NL80211_IFTYPE_STATION) {
1487                 _rtl92cu_stop_tx_beacon(hw);
1488                 _rtl92cu_enable_bcn_sub_func(hw);
1489         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1490                 _rtl92cu_resume_tx_beacon(hw);
1491                 _rtl92cu_disable_bcn_sub_func(hw);
1492         } else {
1493                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1494                          "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1495                          type);
1496         }
1497         switch (type) {
1498         case NL80211_IFTYPE_UNSPECIFIED:
1499                 bt_msr |= MSR_NOLINK;
1500                 ledaction = LED_CTL_LINK;
1501                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1502                          "Set Network type to NO LINK!\n");
1503                 break;
1504         case NL80211_IFTYPE_ADHOC:
1505                 bt_msr |= MSR_ADHOC;
1506                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1507                          "Set Network type to Ad Hoc!\n");
1508                 break;
1509         case NL80211_IFTYPE_STATION:
1510                 bt_msr |= MSR_INFRA;
1511                 ledaction = LED_CTL_LINK;
1512                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1513                          "Set Network type to STA!\n");
1514                 break;
1515         case NL80211_IFTYPE_AP:
1516                 bt_msr |= MSR_AP;
1517                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1518                          "Set Network type to AP!\n");
1519                 break;
1520         default:
1521                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1522                          "Network type %d not supported!\n", type);
1523                 goto error_out;
1524         }
1525         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1526         rtlpriv->cfg->ops->led_control(hw, ledaction);
1527         if ((bt_msr & 0xfc) == MSR_AP)
1528                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1529         else
1530                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1531         return 0;
1532 error_out:
1533         return 1;
1534 }
1535
1536 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1537 {
1538         struct rtl_priv *rtlpriv = rtl_priv(hw);
1539         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1540         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1541         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1542         enum nl80211_iftype opmode;
1543
1544         mac->link_state = MAC80211_NOLINK;
1545         opmode = NL80211_IFTYPE_UNSPECIFIED;
1546         _rtl92cu_set_media_status(hw, opmode);
1547         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1548         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1549         if (rtlusb->disableHWSM)
1550                 _CardDisableHWSM(hw);
1551         else
1552                 _CardDisableWithoutHWSM(hw);
1553 }
1554
1555 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1556 {
1557         /* dummy routine needed for callback from rtl_op_configure_filter() */
1558 }
1559
1560 /*========================================================================== */
1561
1562 static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1563                               enum nl80211_iftype type)
1564 {
1565         struct rtl_priv *rtlpriv = rtl_priv(hw);
1566         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1567         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1568         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1569         u8 filterout_non_associated_bssid = false;
1570
1571         switch (type) {
1572         case NL80211_IFTYPE_ADHOC:
1573         case NL80211_IFTYPE_STATION:
1574                 filterout_non_associated_bssid = true;
1575                 break;
1576         case NL80211_IFTYPE_UNSPECIFIED:
1577         case NL80211_IFTYPE_AP:
1578         default:
1579                 break;
1580         }
1581         if (filterout_non_associated_bssid) {
1582                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1583                         switch (rtlphy->current_io_type) {
1584                         case IO_CMD_RESUME_DM_BY_SCAN:
1585                                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1586                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1587                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1588                                 /* enable update TSF */
1589                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1590                                 break;
1591                         case IO_CMD_PAUSE_DM_BY_SCAN:
1592                                 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1593                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1594                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1595                                 /* disable update TSF */
1596                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1597                                 break;
1598                         }
1599                 } else {
1600                         reg_rcr |= (RCR_CBSSID);
1601                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1602                                                       (u8 *)(&reg_rcr));
1603                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1604                 }
1605         } else if (filterout_non_associated_bssid == false) {
1606                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1607                         reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1608                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1609                                                       (u8 *)(&reg_rcr));
1610                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1611                 } else {
1612                         reg_rcr &= (~RCR_CBSSID);
1613                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1614                                                       (u8 *)(&reg_rcr));
1615                         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1616                 }
1617         }
1618 }
1619
1620 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1621 {
1622         if (_rtl92cu_set_media_status(hw, type))
1623                 return -EOPNOTSUPP;
1624         _rtl92cu_set_check_bssid(hw, type);
1625         return 0;
1626 }
1627
1628 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1629 {
1630         struct rtl_priv *rtlpriv = rtl_priv(hw);
1631         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1632
1633         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1634
1635         /* TODO: Remove these magic number */
1636         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1637         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1638         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1639         /* Change beacon AIFS to the largest number
1640          * beacause test chip does not contension before sending beacon. */
1641         if (IS_NORMAL_CHIP(rtlhal->version))
1642                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1643         else
1644                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1645 }
1646
1647 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1648                                     bool Linked)
1649 {
1650         struct rtl_priv *rtlpriv = rtl_priv(hw);
1651
1652         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1653         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1654 }
1655
1656 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1657 {
1658
1659         struct rtl_priv *rtlpriv = rtl_priv(hw);
1660         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1661         u16 bcn_interval, atim_window;
1662         u32 value32;
1663
1664         bcn_interval = mac->beacon_interval;
1665         atim_window = 2;        /*FIX MERGE */
1666         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1667         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1668         _InitBeaconParameters(hw);
1669         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1670         /*
1671          * Force beacon frame transmission even after receiving beacon frame
1672          * from other ad hoc STA
1673          *
1674          *
1675          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1676          */
1677         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1678         value32 &= ~TSFRST;
1679         rtl_write_dword(rtlpriv, REG_TCR, value32);
1680         value32 |= TSFRST;
1681         rtl_write_dword(rtlpriv, REG_TCR, value32);
1682         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1683                  "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1684                  value32);
1685         /* TODO: Modify later (Find the right parameters)
1686          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1687         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1688             (mac->opmode == NL80211_IFTYPE_AP)) {
1689                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1690                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1691         }
1692         _beacon_function_enable(hw, true, true);
1693 }
1694
1695 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1696 {
1697         struct rtl_priv *rtlpriv = rtl_priv(hw);
1698         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1699         u16 bcn_interval = mac->beacon_interval;
1700
1701         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1702                  bcn_interval);
1703         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1704 }
1705
1706 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1707                                    u32 add_msr, u32 rm_msr)
1708 {
1709 }
1710
1711 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1712 {
1713         struct rtl_priv *rtlpriv = rtl_priv(hw);
1714         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1715         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1716
1717         switch (variable) {
1718         case HW_VAR_RCR:
1719                 *((u32 *)(val)) = mac->rx_conf;
1720                 break;
1721         case HW_VAR_RF_STATE:
1722                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1723                 break;
1724         case HW_VAR_FWLPS_RF_ON:{
1725                         enum rf_pwrstate rfState;
1726                         u32 val_rcr;
1727
1728                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1729                                                       (u8 *)(&rfState));
1730                         if (rfState == ERFOFF) {
1731                                 *((bool *) (val)) = true;
1732                         } else {
1733                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1734                                 val_rcr &= 0x00070000;
1735                                 if (val_rcr)
1736                                         *((bool *) (val)) = false;
1737                                 else
1738                                         *((bool *) (val)) = true;
1739                         }
1740                         break;
1741                 }
1742         case HW_VAR_FW_PSMODE_STATUS:
1743                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1744                 break;
1745         case HW_VAR_CORRECT_TSF:{
1746                         u64 tsf;
1747                         u32 *ptsf_low = (u32 *)&tsf;
1748                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1749
1750                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1751                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1752                         *((u64 *)(val)) = tsf;
1753                         break;
1754                 }
1755         case HW_VAR_MGT_FILTER:
1756                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1757                 break;
1758         case HW_VAR_CTRL_FILTER:
1759                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1760                 break;
1761         case HW_VAR_DATA_FILTER:
1762                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1763                 break;
1764         default:
1765                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1766                          "switch case not processed\n");
1767                 break;
1768         }
1769 }
1770
1771 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1772 {
1773         struct rtl_priv *rtlpriv = rtl_priv(hw);
1774         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1775         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1776         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1777         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1778         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1779         enum wireless_mode wirelessmode = mac->mode;
1780         u8 idx = 0;
1781
1782         switch (variable) {
1783         case HW_VAR_ETHER_ADDR:{
1784                         for (idx = 0; idx < ETH_ALEN; idx++) {
1785                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1786                                                val[idx]);
1787                         }
1788                         break;
1789                 }
1790         case HW_VAR_BASIC_RATE:{
1791                         u16 rate_cfg = ((u16 *) val)[0];
1792                         u8 rate_index = 0;
1793
1794                         rate_cfg &= 0x15f;
1795                         /* TODO */
1796                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1797                          *     && ((rate_cfg & 0x150) == 0)) {
1798                          *        rate_cfg |= 0x010;
1799                          * } */
1800                         rate_cfg |= 0x01;
1801                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1802                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1803                                        (rate_cfg >> 8) & 0xff);
1804                         while (rate_cfg > 0x1) {
1805                                 rate_cfg >>= 1;
1806                                 rate_index++;
1807                         }
1808                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1809                                        rate_index);
1810                         break;
1811                 }
1812         case HW_VAR_BSSID:{
1813                         for (idx = 0; idx < ETH_ALEN; idx++) {
1814                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1815                                                val[idx]);
1816                         }
1817                         break;
1818                 }
1819         case HW_VAR_SIFS:{
1820                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1821                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1822                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1823                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1824                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1825                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1826                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1827                         break;
1828                 }
1829         case HW_VAR_SLOT_TIME:{
1830                         u8 e_aci;
1831                         u8 QOS_MODE = 1;
1832
1833                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1834                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1835                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
1836                         if (QOS_MODE) {
1837                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1838                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1839                                                                 HW_VAR_AC_PARAM,
1840                                                                 (u8 *)(&e_aci));
1841                         } else {
1842                                 u8 sifstime = 0;
1843                                 u8      u1bAIFS;
1844
1845                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1846                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1847                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1848                                         sifstime = 16;
1849                                 else
1850                                         sifstime = 10;
1851                                 u1bAIFS = sifstime + (2 *  val[0]);
1852                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1853                                                u1bAIFS);
1854                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1855                                                u1bAIFS);
1856                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1857                                                u1bAIFS);
1858                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1859                                                u1bAIFS);
1860                         }
1861                         break;
1862                 }
1863         case HW_VAR_ACK_PREAMBLE:{
1864                         u8 reg_tmp;
1865                         u8 short_preamble = (bool) (*(u8 *) val);
1866                         reg_tmp = 0;
1867                         if (short_preamble)
1868                                 reg_tmp |= 0x80;
1869                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1870                         break;
1871                 }
1872         case HW_VAR_AMPDU_MIN_SPACE:{
1873                         u8 min_spacing_to_set;
1874                         u8 sec_min_space;
1875
1876                         min_spacing_to_set = *((u8 *) val);
1877                         if (min_spacing_to_set <= 7) {
1878                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1879                                 case NO_ENCRYPTION:
1880                                 case AESCCMP_ENCRYPTION:
1881                                         sec_min_space = 0;
1882                                         break;
1883                                 case WEP40_ENCRYPTION:
1884                                 case WEP104_ENCRYPTION:
1885                                 case TKIP_ENCRYPTION:
1886                                         sec_min_space = 6;
1887                                         break;
1888                                 default:
1889                                         sec_min_space = 7;
1890                                         break;
1891                                 }
1892                                 if (min_spacing_to_set < sec_min_space)
1893                                         min_spacing_to_set = sec_min_space;
1894                                 mac->min_space_cfg = ((mac->min_space_cfg &
1895                                                      0xf8) |
1896                                                      min_spacing_to_set);
1897                                 *val = min_spacing_to_set;
1898                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1899                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1900                                          mac->min_space_cfg);
1901                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1902                                                mac->min_space_cfg);
1903                         }
1904                         break;
1905                 }
1906         case HW_VAR_SHORTGI_DENSITY:{
1907                         u8 density_to_set;
1908
1909                         density_to_set = *((u8 *) val);
1910                         density_to_set &= 0x1f;
1911                         mac->min_space_cfg &= 0x07;
1912                         mac->min_space_cfg |= (density_to_set << 3);
1913                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1914                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1915                                  mac->min_space_cfg);
1916                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1917                                        mac->min_space_cfg);
1918                         break;
1919                 }
1920         case HW_VAR_AMPDU_FACTOR:{
1921                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1922                         u8 factor_toset;
1923                         u8 *p_regtoset = NULL;
1924                         u8 index = 0;
1925
1926                         p_regtoset = regtoset_normal;
1927                         factor_toset = *((u8 *) val);
1928                         if (factor_toset <= 3) {
1929                                 factor_toset = (1 << (factor_toset + 2));
1930                                 if (factor_toset > 0xf)
1931                                         factor_toset = 0xf;
1932                                 for (index = 0; index < 4; index++) {
1933                                         if ((p_regtoset[index] & 0xf0) >
1934                                             (factor_toset << 4))
1935                                                 p_regtoset[index] =
1936                                                      (p_regtoset[index] & 0x0f)
1937                                                      | (factor_toset << 4);
1938                                         if ((p_regtoset[index] & 0x0f) >
1939                                              factor_toset)
1940                                                 p_regtoset[index] =
1941                                                      (p_regtoset[index] & 0xf0)
1942                                                      | (factor_toset);
1943                                         rtl_write_byte(rtlpriv,
1944                                                        (REG_AGGLEN_LMT + index),
1945                                                        p_regtoset[index]);
1946                                 }
1947                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1948                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1949                                          factor_toset);
1950                         }
1951                         break;
1952                 }
1953         case HW_VAR_AC_PARAM:{
1954                         u8 e_aci = *((u8 *) val);
1955                         u32 u4b_ac_param;
1956                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1957                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1958                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1959
1960                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1961                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1962                                          AC_PARAM_ECW_MIN_OFFSET);
1963                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1964                                          AC_PARAM_ECW_MAX_OFFSET);
1965                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1966                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1967                                  "queue:%x, ac_param:%x\n",
1968                                  e_aci, u4b_ac_param);
1969                         switch (e_aci) {
1970                         case AC1_BK:
1971                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1972                                                 u4b_ac_param);
1973                                 break;
1974                         case AC0_BE:
1975                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1976                                                 u4b_ac_param);
1977                                 break;
1978                         case AC2_VI:
1979                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1980                                                 u4b_ac_param);
1981                                 break;
1982                         case AC3_VO:
1983                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1984                                                 u4b_ac_param);
1985                                 break;
1986                         default:
1987                                 RT_ASSERT(false, ("SetHwReg8185(): invalid"
1988                                           " aci: %d !\n", e_aci));
1989                                 break;
1990                         }
1991                         if (rtlusb->acm_method != eAcmWay2_SW)
1992                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1993                                          HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
1994                         break;
1995                 }
1996         case HW_VAR_ACM_CTRL:{
1997                         u8 e_aci = *((u8 *) val);
1998                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
1999                                                         (&(mac->ac[0].aifs));
2000                         u8 acm = p_aci_aifsn->f.acm;
2001                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2002
2003                         acm_ctrl =
2004                             acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2005                         if (acm) {
2006                                 switch (e_aci) {
2007                                 case AC0_BE:
2008                                         acm_ctrl |= AcmHw_BeqEn;
2009                                         break;
2010                                 case AC2_VI:
2011                                         acm_ctrl |= AcmHw_ViqEn;
2012                                         break;
2013                                 case AC3_VO:
2014                                         acm_ctrl |= AcmHw_VoqEn;
2015                                         break;
2016                                 default:
2017                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2018                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
2019                                                  acm);
2020                                         break;
2021                                 }
2022                         } else {
2023                                 switch (e_aci) {
2024                                 case AC0_BE:
2025                                         acm_ctrl &= (~AcmHw_BeqEn);
2026                                         break;
2027                                 case AC2_VI:
2028                                         acm_ctrl &= (~AcmHw_ViqEn);
2029                                         break;
2030                                 case AC3_VO:
2031                                         acm_ctrl &= (~AcmHw_BeqEn);
2032                                         break;
2033                                 default:
2034                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2035                                                  "switch case not processed\n");
2036                                         break;
2037                                 }
2038                         }
2039                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2040                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
2041                                  acm_ctrl);
2042                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2043                         break;
2044                 }
2045         case HW_VAR_RCR:{
2046                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2047                         mac->rx_conf = ((u32 *) (val))[0];
2048                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2049                                  "### Set RCR(0x%08x) ###\n", mac->rx_conf);
2050                         break;
2051                 }
2052         case HW_VAR_RETRY_LIMIT:{
2053                         u8 retry_limit = ((u8 *) (val))[0];
2054
2055                         rtl_write_word(rtlpriv, REG_RL,
2056                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2057                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
2058                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
2059                                  "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
2060                                  retry_limit);
2061                         break;
2062                 }
2063         case HW_VAR_DUAL_TSF_RST:
2064                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2065                 break;
2066         case HW_VAR_EFUSE_BYTES:
2067                 rtlefuse->efuse_usedbytes = *((u16 *) val);
2068                 break;
2069         case HW_VAR_EFUSE_USAGE:
2070                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2071                 break;
2072         case HW_VAR_IO_CMD:
2073                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2074                 break;
2075         case HW_VAR_WPA_CONFIG:
2076                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2077                 break;
2078         case HW_VAR_SET_RPWM:{
2079                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2080
2081                         if (rpwm_val & BIT(7))
2082                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2083                                                (*(u8 *)val));
2084                         else
2085                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2086                                                ((*(u8 *)val) | BIT(7)));
2087                         break;
2088                 }
2089         case HW_VAR_H2C_FW_PWRMODE:{
2090                         u8 psmode = (*(u8 *) val);
2091
2092                         if ((psmode != FW_PS_ACTIVE_MODE) &&
2093                            (!IS_92C_SERIAL(rtlhal->version)))
2094                                 rtl92c_dm_rf_saving(hw, true);
2095                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2096                         break;
2097                 }
2098         case HW_VAR_FW_PSMODE_STATUS:
2099                 ppsc->fw_current_inpsmode = *((bool *) val);
2100                 break;
2101         case HW_VAR_H2C_FW_JOINBSSRPT:{
2102                         u8 mstatus = (*(u8 *) val);
2103                         u8 tmp_reg422;
2104                         bool recover = false;
2105
2106                         if (mstatus == RT_MEDIA_CONNECT) {
2107                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2108                                                          HW_VAR_AID, NULL);
2109                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2110                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2111                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2112                                 tmp_reg422 = rtl_read_byte(rtlpriv,
2113                                                         REG_FWHW_TXQ_CTRL + 2);
2114                                 if (tmp_reg422 & BIT(6))
2115                                         recover = true;
2116                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2117                                                tmp_reg422 & (~BIT(6)));
2118                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2119                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2120                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2121                                 if (recover)
2122                                         rtl_write_byte(rtlpriv,
2123                                                  REG_FWHW_TXQ_CTRL + 2,
2124                                                 tmp_reg422 | BIT(6));
2125                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2126                         }
2127                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2128                         break;
2129                 }
2130         case HW_VAR_AID:{
2131                         u16 u2btmp;
2132
2133                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2134                         u2btmp &= 0xC000;
2135                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2136                                        (u2btmp | mac->assoc_id));
2137                         break;
2138                 }
2139         case HW_VAR_CORRECT_TSF:{
2140                         u8 btype_ibss = ((u8 *) (val))[0];
2141
2142                         if (btype_ibss)
2143                                 _rtl92cu_stop_tx_beacon(hw);
2144                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2145                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2146                                         0xffffffff));
2147                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2148                                         (u32)((mac->tsf >> 32) & 0xffffffff));
2149                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2150                         if (btype_ibss)
2151                                 _rtl92cu_resume_tx_beacon(hw);
2152                         break;
2153                 }
2154         case HW_VAR_MGT_FILTER:
2155                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2156                 break;
2157         case HW_VAR_CTRL_FILTER:
2158                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2159                 break;
2160         case HW_VAR_DATA_FILTER:
2161                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2162                 break;
2163         default:
2164                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2165                          "switch case not processed\n");
2166                 break;
2167         }
2168 }
2169
2170 void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2171                                    struct ieee80211_sta *sta,
2172                                    u8 rssi_level)
2173 {
2174         struct rtl_priv *rtlpriv = rtl_priv(hw);
2175         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2176         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2177         u32 ratr_value = (u32) mac->basic_rates;
2178         u8 *mcsrate = mac->mcs;
2179         u8 ratr_index = 0;
2180         u8 nmode = mac->ht_enable;
2181         u8 mimo_ps = 1;
2182         u16 shortgi_rate = 0;
2183         u32 tmp_ratr_value = 0;
2184         u8 curtxbw_40mhz = mac->bw_40;
2185         u8 curshortgi_40mhz = mac->sgi_40;
2186         u8 curshortgi_20mhz = mac->sgi_20;
2187         enum wireless_mode wirelessmode = mac->mode;
2188
2189         ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2190         switch (wirelessmode) {
2191         case WIRELESS_MODE_B:
2192                 if (ratr_value & 0x0000000c)
2193                         ratr_value &= 0x0000000d;
2194                 else
2195                         ratr_value &= 0x0000000f;
2196                 break;
2197         case WIRELESS_MODE_G:
2198                 ratr_value &= 0x00000FF5;
2199                 break;
2200         case WIRELESS_MODE_N_24G:
2201         case WIRELESS_MODE_N_5G:
2202                 nmode = 1;
2203                 if (mimo_ps == 0) {
2204                         ratr_value &= 0x0007F005;
2205                 } else {
2206                         u32 ratr_mask;
2207
2208                         if (get_rf_type(rtlphy) == RF_1T2R ||
2209                             get_rf_type(rtlphy) == RF_1T1R)
2210                                 ratr_mask = 0x000ff005;
2211                         else
2212                                 ratr_mask = 0x0f0ff005;
2213                         if (curtxbw_40mhz)
2214                                 ratr_mask |= 0x00000010;
2215                         ratr_value &= ratr_mask;
2216                 }
2217                 break;
2218         default:
2219                 if (rtlphy->rf_type == RF_1T2R)
2220                         ratr_value &= 0x000ff0ff;
2221                 else
2222                         ratr_value &= 0x0f0ff0ff;
2223                 break;
2224         }
2225         ratr_value &= 0x0FFFFFFF;
2226         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2227             (!curtxbw_40mhz && curshortgi_20mhz))) {
2228                 ratr_value |= 0x10000000;
2229                 tmp_ratr_value = (ratr_value >> 12);
2230                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2231                         if ((1 << shortgi_rate) & tmp_ratr_value)
2232                                 break;
2233                 }
2234                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2235                                (shortgi_rate << 4) | (shortgi_rate);
2236         }
2237         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2238         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2239                  rtl_read_dword(rtlpriv, REG_ARFR0));
2240 }
2241
2242 void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2243 {
2244         struct rtl_priv *rtlpriv = rtl_priv(hw);
2245         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2246         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2247         u32 ratr_bitmap = (u32) mac->basic_rates;
2248         u8 *p_mcsrate = mac->mcs;
2249         u8 ratr_index = 0;
2250         u8 curtxbw_40mhz = mac->bw_40;
2251         u8 curshortgi_40mhz = mac->sgi_40;
2252         u8 curshortgi_20mhz = mac->sgi_20;
2253         enum wireless_mode wirelessmode = mac->mode;
2254         bool shortgi = false;
2255         u8 rate_mask[5];
2256         u8 macid = 0;
2257         u8 mimops = 1;
2258
2259         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2260         switch (wirelessmode) {
2261         case WIRELESS_MODE_B:
2262                 ratr_index = RATR_INX_WIRELESS_B;
2263                 if (ratr_bitmap & 0x0000000c)
2264                         ratr_bitmap &= 0x0000000d;
2265                 else
2266                         ratr_bitmap &= 0x0000000f;
2267                 break;
2268         case WIRELESS_MODE_G:
2269                 ratr_index = RATR_INX_WIRELESS_GB;
2270                 if (rssi_level == 1)
2271                         ratr_bitmap &= 0x00000f00;
2272                 else if (rssi_level == 2)
2273                         ratr_bitmap &= 0x00000ff0;
2274                 else
2275                         ratr_bitmap &= 0x00000ff5;
2276                 break;
2277         case WIRELESS_MODE_A:
2278                 ratr_index = RATR_INX_WIRELESS_A;
2279                 ratr_bitmap &= 0x00000ff0;
2280                 break;
2281         case WIRELESS_MODE_N_24G:
2282         case WIRELESS_MODE_N_5G:
2283                 ratr_index = RATR_INX_WIRELESS_NGB;
2284                 if (mimops == 0) {
2285                         if (rssi_level == 1)
2286                                 ratr_bitmap &= 0x00070000;
2287                         else if (rssi_level == 2)
2288                                 ratr_bitmap &= 0x0007f000;
2289                         else
2290                                 ratr_bitmap &= 0x0007f005;
2291                 } else {
2292                         if (rtlphy->rf_type == RF_1T2R ||
2293                             rtlphy->rf_type == RF_1T1R) {
2294                                 if (curtxbw_40mhz) {
2295                                         if (rssi_level == 1)
2296                                                 ratr_bitmap &= 0x000f0000;
2297                                         else if (rssi_level == 2)
2298                                                 ratr_bitmap &= 0x000ff000;
2299                                         else
2300                                                 ratr_bitmap &= 0x000ff015;
2301                                 } else {
2302                                         if (rssi_level == 1)
2303                                                 ratr_bitmap &= 0x000f0000;
2304                                         else if (rssi_level == 2)
2305                                                 ratr_bitmap &= 0x000ff000;
2306                                         else
2307                                                 ratr_bitmap &= 0x000ff005;
2308                                 }
2309                         } else {
2310                                 if (curtxbw_40mhz) {
2311                                         if (rssi_level == 1)
2312                                                 ratr_bitmap &= 0x0f0f0000;
2313                                         else if (rssi_level == 2)
2314                                                 ratr_bitmap &= 0x0f0ff000;
2315                                         else
2316                                                 ratr_bitmap &= 0x0f0ff015;
2317                                 } else {
2318                                         if (rssi_level == 1)
2319                                                 ratr_bitmap &= 0x0f0f0000;
2320                                         else if (rssi_level == 2)
2321                                                 ratr_bitmap &= 0x0f0ff000;
2322                                         else
2323                                                 ratr_bitmap &= 0x0f0ff005;
2324                                 }
2325                         }
2326                 }
2327                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2328                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2329                         if (macid == 0)
2330                                 shortgi = true;
2331                         else if (macid == 1)
2332                                 shortgi = false;
2333                 }
2334                 break;
2335         default:
2336                 ratr_index = RATR_INX_WIRELESS_NGB;
2337                 if (rtlphy->rf_type == RF_1T2R)
2338                         ratr_bitmap &= 0x000ff0ff;
2339                 else
2340                         ratr_bitmap &= 0x0f0ff0ff;
2341                 break;
2342         }
2343         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "ratr_bitmap :%x\n",
2344                  ratr_bitmap);
2345         *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2346                                       ratr_index << 28);
2347         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2348         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2349                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2350                  ratr_index, ratr_bitmap,
2351                  rate_mask[0], rate_mask[1], rate_mask[2], rate_mask[3],
2352                  rate_mask[4]);
2353         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2354 }
2355
2356 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2357 {
2358         struct rtl_priv *rtlpriv = rtl_priv(hw);
2359         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2360         u16 sifs_timer;
2361
2362         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2363                                       (u8 *)&mac->slot_time);
2364         if (!mac->ht_enable)
2365                 sifs_timer = 0x0a0a;
2366         else
2367                 sifs_timer = 0x0e0e;
2368         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2369 }
2370
2371 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2372 {
2373         struct rtl_priv *rtlpriv = rtl_priv(hw);
2374         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2375         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2376         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2377         u8 u1tmp = 0;
2378         bool actuallyset = false;
2379         unsigned long flag = 0;
2380         /* to do - usb autosuspend */
2381         u8 usb_autosuspend = 0;
2382
2383         if (ppsc->swrf_processing)
2384                 return false;
2385         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2386         if (ppsc->rfchange_inprogress) {
2387                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2388                 return false;
2389         } else {
2390                 ppsc->rfchange_inprogress = true;
2391                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2392         }
2393         cur_rfstate = ppsc->rfpwr_state;
2394         if (usb_autosuspend) {
2395                 /* to do................... */
2396         } else {
2397                 if (ppsc->pwrdown_mode) {
2398                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2399                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2400                                                ERFOFF : ERFON;
2401                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2402                                  "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2403                 } else {
2404                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2405                                        rtl_read_byte(rtlpriv,
2406                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2407                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2408                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2409                                                  ERFON : ERFOFF;
2410                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2411                                  "GPIO_IN=%02x\n", u1tmp);
2412                 }
2413                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2414                          e_rfpowerstate_toset);
2415         }
2416         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2417                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2418                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2419                 ppsc->hwradiooff = false;
2420                 actuallyset = true;
2421         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2422                     ERFOFF)) {
2423                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2424                          "GPIOChangeRF  - HW Radio OFF\n");
2425                 ppsc->hwradiooff = true;
2426                 actuallyset = true;
2427         } else {
2428                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2429                          "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2430                          ppsc->hwradiooff, e_rfpowerstate_toset);
2431         }
2432         if (actuallyset) {
2433                 ppsc->hwradiooff = true;
2434                 if (e_rfpowerstate_toset == ERFON) {
2435                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2436                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2437                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2438                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2439                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2440                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2441                 }
2442                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2443                 ppsc->rfchange_inprogress = false;
2444                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2445                 /* For power down module, we need to enable register block
2446                  * contrl reg at 0x1c. Then enable power down control bit
2447                  * of register 0x04 BIT4 and BIT15 as 1.
2448                  */
2449                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2450                         /* Enable register area 0x0-0xc. */
2451                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2452                         if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2453                                 /*
2454                                  * We should configure HW PDn source for WiFi
2455                                  * ONLY, and then our HW will be set in
2456                                  * power-down mode if PDn source from all
2457                                  * functions are configured.
2458                                  */
2459                                 u1tmp = rtl_read_byte(rtlpriv,
2460                                                       REG_MULTI_FUNC_CTRL);
2461                                 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2462                                                (u1tmp|WL_HWPDN_EN));
2463                         } else {
2464                                 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2465                         }
2466                 }
2467                 if (e_rfpowerstate_toset == ERFOFF) {
2468                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2469                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2470                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2471                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2472                 }
2473         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2474                 /* Enter D3 or ASPM after GPIO had been done. */
2475                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2476                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2477                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2478                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2479                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2480                 ppsc->rfchange_inprogress = false;
2481                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2482         } else {
2483                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2484                 ppsc->rfchange_inprogress = false;
2485                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2486         }
2487         *valid = 1;
2488         return !ppsc->hwradiooff;
2489 }