drivers/net/wireless/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include "../wifi.h"
  33 #include "../efuse.h"
  34 #include "../base.h"
  35 #include "../cam.h"
  36 #include "../ps.h"
  37 #include "../usb.h"
  38 #include "reg.h"
  39 #include "def.h"
  40 #include "phy.h"
  41 #include "mac.h"
  42 #include "dm.h"
  43 #include "hw.h"
  44 #include "../rtl8192ce/hw.h"
  45 #include "trx.h"
  46 #include "led.h"
  47 #include "table.h"
  48
  49 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  53         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  54
  55         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  56         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  57         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  58                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  59                         RTL8192CUPHY_REG_Array_PG_HPLength;
  60                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  61                         RTL8192CUPHY_REG_Array_PG_HP;
  62         } else {
  63                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  64                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  65                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  66                         RTL8192CUPHY_REG_ARRAY_PG;
  67         }
  68         /* 2T */
  69         rtlphy->hwparam_tables[PHY_REG_2T].length =
  70                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  71         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  72                         RTL8192CUPHY_REG_2TARRAY;
  73         rtlphy->hwparam_tables[RADIOA_2T].length =
  74                         RTL8192CURADIOA_2TARRAYLENGTH;
  75         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  76                         RTL8192CURADIOA_2TARRAY;
  77         rtlphy->hwparam_tables[RADIOB_2T].length =
  78                         RTL8192CURADIOB_2TARRAYLENGTH;
  79         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  80                         RTL8192CU_RADIOB_2TARRAY;
  81         rtlphy->hwparam_tables[AGCTAB_2T].length =
  82                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  83         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  84                         RTL8192CUAGCTAB_2TARRAY;
  85         /* 1T */
  86         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  87                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  88                         RTL8192CUPHY_REG_1T_HPArrayLength;
  89                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  90                         RTL8192CUPHY_REG_1T_HPArray;
  91                 rtlphy->hwparam_tables[RADIOA_1T].length =
  92                         RTL8192CURadioA_1T_HPArrayLength;
  93                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  94                         RTL8192CURadioA_1T_HPArray;
  95                 rtlphy->hwparam_tables[RADIOB_1T].length =
  96                         RTL8192CURADIOB_1TARRAYLENGTH;
  97                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  98                         RTL8192CU_RADIOB_1TARRAY;
  99                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 100                         RTL8192CUAGCTAB_1T_HPArrayLength;
 101                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 102                         Rtl8192CUAGCTAB_1T_HPArray;
 103         } else {
 104                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 105                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 106                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 107                         RTL8192CUPHY_REG_1TARRAY;
 108                 rtlphy->hwparam_tables[RADIOA_1T].length =
 109                         RTL8192CURADIOA_1TARRAYLENGTH;
 110                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 111                         RTL8192CU_RADIOA_1TARRAY;
 112                 rtlphy->hwparam_tables[RADIOB_1T].length =
 113                         RTL8192CURADIOB_1TARRAYLENGTH;
 114                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 115                         RTL8192CU_RADIOB_1TARRAY;
 116                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 117                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 118                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 119                         RTL8192CUAGCTAB_1TARRAY;
 120         }
 121 }
 122
 123 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 124                                                  bool autoload_fail,
 125                                                  u8 *hwinfo)
 126 {
 127         struct rtl_priv *rtlpriv = rtl_priv(hw);
 128         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 129         u8 rf_path, index, tempval;
 130         u16 i;
 131
 132         for (rf_path = 0; rf_path < 2; rf_path++) {
 133                 for (i = 0; i < 3; i++) {
 134                         if (!autoload_fail) {
 135                                 rtlefuse->
 136                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 137                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 138                                 rtlefuse->
 139                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 140                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 141                                            i];
 142                         } else {
 143                                 rtlefuse->
 144                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 145                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 146                                 rtlefuse->
 147                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 148                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 149                         }
 150                 }
 151         }
 152         for (i = 0; i < 3; i++) {
 153                 if (!autoload_fail)
 154                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 155                 else
 156                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 157                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
 158                     (tempval & 0xf);
 159                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
 160                     ((tempval & 0xf0) >> 4);
 161         }
 162         for (rf_path = 0; rf_path < 2; rf_path++)
 163                 for (i = 0; i < 3; i++)
 164                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 165                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
 166                                  i, rtlefuse->
 167                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
 168         for (rf_path = 0; rf_path < 2; rf_path++)
 169                 for (i = 0; i < 3; i++)
 170                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 171                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 172                                  rf_path, i,
 173                                  rtlefuse->
 174                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
 175         for (rf_path = 0; rf_path < 2; rf_path++)
 176                 for (i = 0; i < 3; i++)
 177                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 178                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 179                                  rf_path, i,
 180                                  rtlefuse->
 181                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 182                                  [i]));
 183         for (rf_path = 0; rf_path < 2; rf_path++) {
 184                 for (i = 0; i < 14; i++) {
 185                         index = _rtl92c_get_chnl_group((u8) i);
 186                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 187                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 188                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 189                             rtlefuse->
 190                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 191                         if ((rtlefuse->
 192                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 193                              rtlefuse->
 194                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
 195                             > 0) {
 196                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 197                                     rtlefuse->
 198                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 199                                     [index] - rtlefuse->
 200                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 201                                     [index];
 202                         } else {
 203                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 204                         }
 205                 }
 206                 for (i = 0; i < 14; i++) {
 207                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 208                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
 209                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
 210                                  rtlefuse->txpwrlevel_cck[rf_path][i],
 211                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 212                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
 213                 }
 214         }
 215         for (i = 0; i < 3; i++) {
 216                 if (!autoload_fail) {
 217                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 218                             hwinfo[EEPROM_TXPWR_GROUP + i];
 219                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 220                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 221                 } else {
 222                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 223                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 224                 }
 225         }
 226         for (rf_path = 0; rf_path < 2; rf_path++) {
 227                 for (i = 0; i < 14; i++) {
 228                         index = _rtl92c_get_chnl_group((u8) i);
 229                         if (rf_path == RF90_PATH_A) {
 230                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 231                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 232                                      & 0xf);
 233                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 234                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 235                                      & 0xf);
 236                         } else if (rf_path == RF90_PATH_B) {
 237                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 238                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 239                                       & 0xf0) >> 4);
 240                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 241                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 242                                       & 0xf0) >> 4);
 243                         }
 244                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 245                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 246                                  rf_path, i,
 247                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
 248                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 249                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 250                                  rf_path, i,
 251                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
 252                 }
 253         }
 254         for (i = 0; i < 14; i++) {
 255                 index = _rtl92c_get_chnl_group((u8) i);
 256                 if (!autoload_fail)
 257                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 258                 else
 259                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 260                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 261                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 262                     ((tempval >> 4) & 0xF);
 263                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 264                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 265                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 266                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 267                 index = _rtl92c_get_chnl_group((u8) i);
 268                 if (!autoload_fail)
 269                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 270                 else
 271                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 272                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 273                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 274                     ((tempval >> 4) & 0xF);
 275         }
 276         rtlefuse->legacy_ht_txpowerdiff =
 277             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 278         for (i = 0; i < 14; i++)
 279                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 280                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 281                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
 282         for (i = 0; i < 14; i++)
 283                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 284                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
 285                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
 286         for (i = 0; i < 14; i++)
 287                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 288                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 289                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
 290         for (i = 0; i < 14; i++)
 291                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 292                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
 293                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
 294         if (!autoload_fail)
 295                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 296         else
 297                 rtlefuse->eeprom_regulatory = 0;
 298         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 299                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
 300         if (!autoload_fail) {
 301                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 302                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 303         } else {
 304                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 305                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 306         }
 307         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 308                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 309                  rtlefuse->eeprom_tssi[RF90_PATH_A],
 310                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
 311         if (!autoload_fail)
 312                 tempval = hwinfo[EEPROM_THERMAL_METER];
 313         else
 314                 tempval = EEPROM_DEFAULT_THERMALMETER;
 315         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 316         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 317             rtlefuse->eeprom_thermalmeter > 0x1c)
 318                 rtlefuse->eeprom_thermalmeter = 0x12;
 319         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 320                 rtlefuse->apk_thermalmeterignore = true;
 321         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 322         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 323                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
 324 }
 325
 326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 327 {
 328         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 329         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 330         u8 boardType;
 331
 332         if (IS_NORMAL_CHIP(rtlhal->version)) {
 333                 boardType = ((contents[EEPROM_RF_OPT1]) &
 334                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 335         } else {
 336                 boardType = contents[EEPROM_RF_OPT4];
 337                 boardType &= BOARD_TYPE_TEST_MASK;
 338         }
 339         rtlefuse->board_type = boardType;
 340         if (IS_HIGHT_PA(rtlefuse->board_type))
 341                 rtlefuse->external_pa = 1;
 342         pr_info("Board Type %x\n", rtlefuse->board_type);
 343
 344 #ifdef CONFIG_ANTENNA_DIVERSITY
 345         /* Antenna Diversity setting. */
 346         if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
 347                 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
 348         else
 349                 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
 350
 351         pr_info("Antenna Config %x\n", rtl_efuse->antenna_cfg);
 352 #endif
 353 }
 354
 355 #ifdef CONFIG_BT_COEXIST
 356 static void _update_bt_param(_adapter *padapter)
 357 {
 358         struct btcoexist_priv    *pbtpriv = &(padapter->halpriv.bt_coexist);
 359         struct registry_priv    *registry_par = &padapter->registrypriv;
 360         if (2 != registry_par->bt_iso) {
 361                 /* 0:Low, 1:High, 2:From Efuse */
 362                 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
 363         }
 364         if (registry_par->bt_sco == 1) {
 365                 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
 366                  * 5.OtherBusy */
 367                 pbtpriv->BT_Service = BT_OtherAction;
 368         } else if (registry_par->bt_sco == 2) {
 369                 pbtpriv->BT_Service = BT_SCO;
 370         } else if (registry_par->bt_sco == 4) {
 371                 pbtpriv->BT_Service = BT_Busy;
 372         } else if (registry_par->bt_sco == 5) {
 373                 pbtpriv->BT_Service = BT_OtherBusy;
 374         } else {
 375                 pbtpriv->BT_Service = BT_Idle;
 376         }
 377         pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
 378         pbtpriv->bCOBT = _TRUE;
 379         pbtpriv->BtEdcaUL = 0;
 380         pbtpriv->BtEdcaDL = 0;
 381         pbtpriv->BtRssiState = 0xff;
 382         pbtpriv->bInitSet = _FALSE;
 383         pbtpriv->bBTBusyTraffic = _FALSE;
 384         pbtpriv->bBTTrafficModeSet = _FALSE;
 385         pbtpriv->bBTNonTrafficModeSet = _FALSE;
 386         pbtpriv->CurrentState = 0;
 387         pbtpriv->PreviousState = 0;
 388         pr_info("BT Coexistance = %s\n",
 389                 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
 390         if (pbtpriv->BT_Coexist) {
 391                 if (pbtpriv->BT_Ant_Num == Ant_x2)
 392                         pr_info("BlueTooth BT_Ant_Num = Antx2\n");
 393                 else if (pbtpriv->BT_Ant_Num == Ant_x1)
 394                         pr_info("BlueTooth BT_Ant_Num = Antx1\n");
 395                 switch (pbtpriv->BT_CoexistType) {
 396                 case BT_2Wire:
 397                         pr_info("BlueTooth BT_CoexistType = BT_2Wire\n");
 398                         break;
 399                 case BT_ISSC_3Wire:
 400                         pr_info("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
 401                         break;
 402                 case BT_Accel:
 403                         pr_info("BlueTooth BT_CoexistType = BT_Accel\n");
 404                         break;
 405                 case BT_CSR_BC4:
 406                         pr_info("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
 407                         break;
 408                 case BT_CSR_BC8:
 409                         pr_info("BlueTooth BT_CoexistType = BT_CSR_BC8\n");
 410                         break;
 411                 case BT_RTL8756:
 412                         pr_info("BlueTooth BT_CoexistType = BT_RTL8756\n");
 413                         break;
 414                 default:
 415                         pr_info("BlueTooth BT_CoexistType = Unknown\n");
 416                         break;
 417                 }
 418                 pr_info("BlueTooth BT_Ant_isolation = %d\n",
 419                         pbtpriv->BT_Ant_isolation);
 420                 switch (pbtpriv->BT_Service) {
 421                 case BT_OtherAction:
 422                         pr_info("BlueTooth BT_Service = BT_OtherAction\n");
 423                         break;
 424                 case BT_SCO:
 425                         pr_info("BlueTooth BT_Service = BT_SCO\n");
 426                         break;
 427                 case BT_Busy:
 428                         pr_info("BlueTooth BT_Service = BT_Busy\n");
 429                         break;
 430                 case BT_OtherBusy:
 431                         pr_info("BlueTooth BT_Service = BT_OtherBusy\n");
 432                         break;
 433                 default:
 434                         pr_info("BlueTooth BT_Service = BT_Idle\n");
 435                         break;
 436                 }
 437                 pr_info("BT_RadioSharedType = 0x%x\n",
 438                         pbtpriv->BT_RadioSharedType);
 439         }
 440 }
 441
 442 #define GET_BT_COEXIST(priv) (&priv->bt_coexist)
 443
 444 static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
 445                                                 u8 *contents,
 446                                                 bool bautoloadfailed);
 447 {
 448         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 449         bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
 450         struct btcoexist_priv    *pbtpriv = &pHalData->bt_coexist;
 451         u8      rf_opt4;
 452
 453         _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
 454         if (AutoloadFail) {
 455                 pbtpriv->BT_Coexist = _FALSE;
 456                 pbtpriv->BT_CoexistType = BT_2Wire;
 457                 pbtpriv->BT_Ant_Num = Ant_x2;
 458                 pbtpriv->BT_Ant_isolation = 0;
 459                 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
 460                 return;
 461         }
 462         if (isNormal) {
 463                 if (pHalData->BoardType == BOARD_USB_COMBO)
 464                         pbtpriv->BT_Coexist = _TRUE;
 465                 else
 466                         pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
 467                                               0x20) >> 5); /* bit[5] */
 468                 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
 469                 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
 470                 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
 471                 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
 472                 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
 473         } else {
 474                 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
 475                                        _TRUE : _FALSE;
 476         }
 477         _update_bt_param(Adapter);
 478 }
 479 #endif
 480
 481 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 482 {
 483         struct rtl_priv *rtlpriv = rtl_priv(hw);
 484         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 485         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 486         u16 i, usvalue;
 487         u8 hwinfo[HWSET_MAX_SIZE] = {0};
 488         u16 eeprom_id;
 489
 490         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 491                 rtl_efuse_shadow_map_update(hw);
 492                 memcpy((void *)hwinfo,
 493                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
 494                        HWSET_MAX_SIZE);
 495         } else if (rtlefuse->epromtype == EEPROM_93C46) {
 496                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 497                          ("RTL819X Not boot from eeprom, check it !!"));
 498         }
 499         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
 500                       hwinfo, HWSET_MAX_SIZE);
 501         eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
 502         if (eeprom_id != RTL8190_EEPROM_ID) {
 503                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 504                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
 505                 rtlefuse->autoload_failflag = true;
 506         } else {
 507                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
 508                 rtlefuse->autoload_failflag = false;
 509         }
 510         if (rtlefuse->autoload_failflag)
 511                 return;
 512         for (i = 0; i < 6; i += 2) {
 513                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
 514                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
 515         }
 516         pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
 517         _rtl92cu_read_txpower_info_from_hwpg(hw,
 518                                            rtlefuse->autoload_failflag, hwinfo);
 519         rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
 520         rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
 521         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 522                  (" VID = 0x%02x PID = 0x%02x\n",
 523                  rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
 524         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
 525         rtlefuse->eeprom_version =
 526                          le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
 527         rtlefuse->txpwr_fromeprom = true;
 528         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
 529         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 530                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
 531         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 532                 switch (rtlefuse->eeprom_oemid) {
 533                 case EEPROM_CID_DEFAULT:
 534                         if (rtlefuse->eeprom_did == 0x8176) {
 535                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 536                                      rtlefuse->eeprom_smid == 0x1629))
 537                                         rtlhal->oem_id = RT_CID_819x_HP;
 538                                 else
 539                                         rtlhal->oem_id = RT_CID_DEFAULT;
 540                         } else {
 541                                 rtlhal->oem_id = RT_CID_DEFAULT;
 542                         }
 543                         break;
 544                 case EEPROM_CID_TOSHIBA:
 545                         rtlhal->oem_id = RT_CID_TOSHIBA;
 546                         break;
 547                 case EEPROM_CID_QMI:
 548                         rtlhal->oem_id = RT_CID_819x_QMI;
 549                         break;
 550                 case EEPROM_CID_WHQL:
 551                 default:
 552                         rtlhal->oem_id = RT_CID_DEFAULT;
 553                         break;
 554                 }
 555         }
 556         _rtl92cu_read_board_type(hw, hwinfo);
 557 #ifdef CONFIG_BT_COEXIST
 558         _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
 559                                             rtlefuse->autoload_failflag);
 560 #endif
 561 }
 562
 563 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 564 {
 565         struct rtl_priv *rtlpriv = rtl_priv(hw);
 566         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 567         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 568
 569         switch (rtlhal->oem_id) {
 570         case RT_CID_819x_HP:
 571                 usb_priv->ledctl.led_opendrain = true;
 572                 break;
 573         case RT_CID_819x_Lenovo:
 574         case RT_CID_DEFAULT:
 575         case RT_CID_TOSHIBA:
 576         case RT_CID_CCX:
 577         case RT_CID_819x_Acer:
 578         case RT_CID_WHQL:
 579         default:
 580                 break;
 581         }
 582         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 583                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
 584 }
 585
 586 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 587 {
 588
 589         struct rtl_priv *rtlpriv = rtl_priv(hw);
 590         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 591         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 592         u8 tmp_u1b;
 593
 594         if (!IS_NORMAL_CHIP(rtlhal->version))
 595                 return;
 596         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 597         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
 598                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 599         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
 600                  (tmp_u1b & BOOT_FROM_EEPROM) ? "EERROM" : "EFUSE"));
 601         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 602         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
 603                  (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
 604         _rtl92cu_read_adapter_info(hw);
 605         _rtl92cu_hal_customized_behavior(hw);
 606         return;
 607 }
 608
 609 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 610 {
 611         struct rtl_priv *rtlpriv = rtl_priv(hw);
 612         int             status = 0;
 613         u16             value16;
 614         u8              value8;
 615         /*  polling autoload done. */
 616         u32     pollingCount = 0;
 617
 618         do {
 619                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 620                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 621                                  ("Autoload Done!\n"));
 622                         break;
 623                 }
 624                 if (pollingCount++ > 100) {
 625                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 626                                  ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
 627                                  " done!\n"));
 628                         return -ENODEV;
 629                 }
 630         } while (true);
 631         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 632         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 633         /* Power on when re-enter from IPS/Radio off/card disable */
 634         /* enable SPS into PWM mode */
 635         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 636         udelay(100);
 637         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 638         if (0 == (value8 & LDV12_EN)) {
 639                 value8 |= LDV12_EN;
 640                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 641                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 642                          (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
 643                          value8));
 644                 udelay(100);
 645                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 646                 value8 &= ~ISO_MD2PP;
 647                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 648         }
 649         /*  auto enable WLAN */
 650         pollingCount = 0;
 651         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 652         value16 |= APFM_ONMAC;
 653         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 654         do {
 655                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 656                         pr_info("MAC auto ON okay!\n");
 657                         break;
 658                 }
 659                 if (pollingCount++ > 100) {
 660                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 661                                  ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
 662                                  " done!\n"));
 663                         return -ENODEV;
 664                 }
 665         } while (true);
 666         /* Enable Radio ,GPIO ,and LED function */
 667         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 668         /* release RF digital isolation */
 669         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 670         value16 &= ~ISO_DIOR;
 671         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 672         /* Reconsider when to do this operation after asking HWSD. */
 673         pollingCount = 0;
 674         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 675                                                 REG_APSD_CTRL) & ~BIT(6)));
 676         do {
 677                 pollingCount++;
 678         } while ((pollingCount < 200) &&
 679                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 680         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 681         value16 = rtl_read_word(rtlpriv,  REG_CR);
 682         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 683                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 684         rtl_write_word(rtlpriv, REG_CR, value16);
 685         return status;
 686 }
 687
 688 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 689                                               bool wmm_enable,
 690                                               u8 out_ep_num,
 691                                               u8 queue_sel)
 692 {
 693         struct rtl_priv *rtlpriv = rtl_priv(hw);
 694         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 695         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 696         u32 outEPNum = (u32)out_ep_num;
 697         u32 numHQ = 0;
 698         u32 numLQ = 0;
 699         u32 numNQ = 0;
 700         u32 numPubQ;
 701         u32 value32;
 702         u8 value8;
 703         u32 txQPageNum, txQPageUnit, txQRemainPage;
 704
 705         if (!wmm_enable) {
 706                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 707                           CHIP_A_PAGE_NUM_PUBQ;
 708                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 709
 710                 txQPageUnit = txQPageNum/outEPNum;
 711                 txQRemainPage = txQPageNum % outEPNum;
 712                 if (queue_sel & TX_SELE_HQ)
 713                         numHQ = txQPageUnit;
 714                 if (queue_sel & TX_SELE_LQ)
 715                         numLQ = txQPageUnit;
 716                 /* HIGH priority queue always present in the configuration of
 717                  * 2 out-ep. Remainder pages have assigned to High queue */
 718                 if ((outEPNum > 1) && (txQRemainPage))
 719                         numHQ += txQRemainPage;
 720                 /* NOTE: This step done before writting REG_RQPN. */
 721                 if (isChipN) {
 722                         if (queue_sel & TX_SELE_NQ)
 723                                 numNQ = txQPageUnit;
 724                         value8 = (u8)_NPQ(numNQ);
 725                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 726                 }
 727         } else {
 728                 /* for WMM ,number of out-ep must more than or equal to 2! */
 729                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 730                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 731                 if (queue_sel & TX_SELE_HQ) {
 732                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 733                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 734                 }
 735                 if (queue_sel & TX_SELE_LQ) {
 736                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 737                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 738                 }
 739                 /* NOTE: This step done before writting REG_RQPN. */
 740                 if (isChipN) {
 741                         if (queue_sel & TX_SELE_NQ)
 742                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 743                         value8 = (u8)_NPQ(numNQ);
 744                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 745                 }
 746         }
 747         /* TX DMA */
 748         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 749         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 750 }
 751
 752 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 753 {
 754         struct rtl_priv *rtlpriv = rtl_priv(hw);
 755         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 756         u8      txpktbuf_bndy;
 757         u8      value8;
 758
 759         if (!wmm_enable)
 760                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 761         else /* for WMM */
 762                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 763                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 764                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 765         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 766         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 767         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 768         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 769         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 770         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 771         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 772         rtl_write_byte(rtlpriv, REG_PBP, value8);
 773 }
 774
 775 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 776                                             u16 bkQ, u16 viQ, u16 voQ,
 777                                             u16 mgtQ, u16 hiQ)
 778 {
 779         struct rtl_priv *rtlpriv = rtl_priv(hw);
 780         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 781
 782         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 783                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 784                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 785         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 786 }
 787
 788 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 789                                                     bool wmm_enable,
 790                                                     u8 queue_sel)
 791 {
 792         u16 uninitialized_var(value);
 793
 794         switch (queue_sel) {
 795         case TX_SELE_HQ:
 796                 value = QUEUE_HIGH;
 797                 break;
 798         case TX_SELE_LQ:
 799                 value = QUEUE_LOW;
 800                 break;
 801         case TX_SELE_NQ:
 802                 value = QUEUE_NORMAL;
 803                 break;
 804         default:
 805                 WARN_ON(1); /* Shall not reach here! */
 806                 break;
 807         }
 808         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 809                                         value, value);
 810         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 811 }
 812
 813 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 814                                                                 bool wmm_enable,
 815                                                                 u8 queue_sel)
 816 {
 817         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 818         u16 uninitialized_var(valueHi);
 819         u16 uninitialized_var(valueLow);
 820
 821         switch (queue_sel) {
 822         case (TX_SELE_HQ | TX_SELE_LQ):
 823                 valueHi = QUEUE_HIGH;
 824                 valueLow = QUEUE_LOW;
 825                 break;
 826         case (TX_SELE_NQ | TX_SELE_LQ):
 827                 valueHi = QUEUE_NORMAL;
 828                 valueLow = QUEUE_LOW;
 829                 break;
 830         case (TX_SELE_HQ | TX_SELE_NQ):
 831                 valueHi = QUEUE_HIGH;
 832                 valueLow = QUEUE_NORMAL;
 833                 break;
 834         default:
 835                 WARN_ON(1);
 836                 break;
 837         }
 838         if (!wmm_enable) {
 839                 beQ = valueLow;
 840                 bkQ = valueLow;
 841                 viQ = valueHi;
 842                 voQ = valueHi;
 843                 mgtQ = valueHi;
 844                 hiQ = valueHi;
 845         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 846                 beQ = valueHi;
 847                 bkQ = valueLow;
 848                 viQ = valueLow;
 849                 voQ = valueHi;
 850                 mgtQ = valueHi;
 851                 hiQ = valueHi;
 852         }
 853         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 854         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 855 }
 856
 857 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 858                                                       bool wmm_enable,
 859                                                       u8 queue_sel)
 860 {
 861         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 862         struct rtl_priv *rtlpriv = rtl_priv(hw);
 863
 864         if (!wmm_enable) { /* typical setting */
 865                 beQ     = QUEUE_LOW;
 866                 bkQ     = QUEUE_LOW;
 867                 viQ     = QUEUE_NORMAL;
 868                 voQ     = QUEUE_HIGH;
 869                 mgtQ    = QUEUE_HIGH;
 870                 hiQ     = QUEUE_HIGH;
 871         } else { /* for WMM */
 872                 beQ     = QUEUE_LOW;
 873                 bkQ     = QUEUE_NORMAL;
 874                 viQ     = QUEUE_NORMAL;
 875                 voQ     = QUEUE_HIGH;
 876                 mgtQ    = QUEUE_HIGH;
 877                 hiQ     = QUEUE_HIGH;
 878         }
 879         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 880         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 881                  ("Tx queue select :0x%02x..\n", queue_sel));
 882 }
 883
 884 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 885                                                bool wmm_enable,
 886                                                u8 out_ep_num,
 887                                                u8 queue_sel)
 888 {
 889         switch (out_ep_num) {
 890         case 1:
 891                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 892                                                         queue_sel);
 893                 break;
 894         case 2:
 895                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 896                                                         queue_sel);
 897                 break;
 898         case 3:
 899                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 900                                                           queue_sel);
 901                 break;
 902         default:
 903                 WARN_ON(1); /* Shall not reach here! */
 904                 break;
 905         }
 906 }
 907
 908 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 909                                                bool wmm_enable,
 910                                                u8 out_ep_num,
 911                                                u8 queue_sel)
 912 {
 913         u8 hq_sele = 0;
 914         struct rtl_priv *rtlpriv = rtl_priv(hw);
 915
 916         switch (out_ep_num) {
 917         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 918                 if (!wmm_enable) /* typical setting */
 919                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 920                                    HQSEL_HIQ;
 921                 else    /* for WMM */
 922                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 923                                   HQSEL_HIQ;
 924                 break;
 925         case 1:
 926                 if (TX_SELE_LQ == queue_sel) {
 927                         /* map all endpoint to Low queue */
 928                         hq_sele = 0;
 929                 } else if (TX_SELE_HQ == queue_sel) {
 930                         /* map all endpoint to High queue */
 931                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 932                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 933                 }
 934                 break;
 935         default:
 936                 WARN_ON(1); /* Shall not reach here! */
 937                 break;
 938         }
 939         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 940         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 941                  ("Tx queue select :0x%02x..\n", hq_sele));
 942 }
 943
 944 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 945                                                 bool wmm_enable,
 946                                                 u8 out_ep_num,
 947                                                 u8 queue_sel)
 948 {
 949         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 950         if (IS_NORMAL_CHIP(rtlhal->version))
 951                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 952                                                    queue_sel);
 953         else
 954                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 955                                                    queue_sel);
 956 }
 957
 958 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
 959 {
 960 }
 961
 962 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 963 {
 964         u16                     value16;
 965
 966         struct rtl_priv *rtlpriv = rtl_priv(hw);
 967         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 968
 969         mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
 970                       RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 971                       RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 972         rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
 973         /* Accept all multicast address */
 974         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 975         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 976         /* Accept all management frames */
 977         value16 = 0xFFFF;
 978         rtl92c_set_mgt_filter(hw, value16);
 979         /* Reject all control frame - default value is 0 */
 980         rtl92c_set_ctrl_filter(hw, 0x0);
 981         /* Accept all data frames */
 982         value16 = 0xFFFF;
 983         rtl92c_set_data_filter(hw, value16);
 984 }
 985
 986 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 987 {
 988         struct rtl_priv *rtlpriv = rtl_priv(hw);
 989         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 990         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 991         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
 992         int err = 0;
 993         u32     boundary = 0;
 994         u8 wmm_enable = false; /* TODO */
 995         u8 out_ep_nums = rtlusb->out_ep_nums;
 996         u8 queue_sel = rtlusb->out_queue_sel;
 997         err = _rtl92cu_init_power_on(hw);
 998
 999         if (err) {
1000                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1001                         ("Failed to init power on!\n"));
1002                 return err;
1003         }
1004         if (!wmm_enable) {
1005                 boundary = TX_PAGE_BOUNDARY;
1006         } else { /* for WMM */
1007                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1008                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1009                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1010         }
1011         if (false == rtl92c_init_llt_table(hw, boundary)) {
1012                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1013                         ("Failed to init LLT Table!\n"));
1014                 return -EINVAL;
1015         }
1016         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1017                                           queue_sel);
1018         _rtl92c_init_trx_buffer(hw, wmm_enable);
1019         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1020                                      queue_sel);
1021         /* Get Rx PHY status in order to report RSSI and others. */
1022         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1023         rtl92c_init_interrupt(hw);
1024         rtl92c_init_network_type(hw);
1025         _rtl92cu_init_wmac_setting(hw);
1026         rtl92c_init_adaptive_ctrl(hw);
1027         rtl92c_init_edca(hw);
1028         rtl92c_init_rate_fallback(hw);
1029         rtl92c_init_retry_function(hw);
1030         _rtl92cu_init_usb_aggregation(hw);
1031         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1032         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1033         rtl92c_init_beacon_parameters(hw, rtlhal->version);
1034         rtl92c_init_ampdu_aggregation(hw);
1035         rtl92c_init_beacon_max_error(hw, true);
1036         return err;
1037 }
1038
1039 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1040 {
1041         struct rtl_priv *rtlpriv = rtl_priv(hw);
1042         u8 sec_reg_value = 0x0;
1043         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1044
1045         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1046                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1047                   rtlpriv->sec.pairwise_enc_algorithm,
1048                   rtlpriv->sec.group_enc_algorithm));
1049         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1050                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1051                          ("not open sw encryption\n"));
1052                 return;
1053         }
1054         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1055         if (rtlpriv->sec.use_defaultkey) {
1056                 sec_reg_value |= SCR_TxUseDK;
1057                 sec_reg_value |= SCR_RxUseDK;
1058         }
1059         if (IS_NORMAL_CHIP(rtlhal->version))
1060                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1061         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1062         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1063                  ("The SECR-value %x\n", sec_reg_value));
1064         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1065 }
1066
1067 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1068 {
1069         struct rtl_priv *rtlpriv = rtl_priv(hw);
1070         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1071
1072         /* To Fix MAC loopback mode fail. */
1073         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1074         rtl_write_byte(rtlpriv, 0x15, 0xe9);
1075         /* HW SEQ CTRL */
1076         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1077         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1078         /* fixed USB interface interference issue */
1079         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1080         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1081         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1082         rtlusb->reg_bcn_ctrl_val = 0x18;
1083         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1084 }
1085
1086 static void _InitPABias(struct ieee80211_hw *hw)
1087 {
1088         struct rtl_priv *rtlpriv = rtl_priv(hw);
1089         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1090         u8 pa_setting;
1091
1092         /* FIXED PA current issue */
1093         pa_setting = efuse_read_1byte(hw, 0x1FA);
1094         if (!(pa_setting & BIT(0))) {
1095                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1096                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1097                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1098                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1099         }
1100         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1101             IS_92C_SERIAL(rtlhal->version)) {
1102                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1103                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1104                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1105                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1106         }
1107         if (!(pa_setting & BIT(4))) {
1108                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1109                 pa_setting &= 0x0F;
1110                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1111         }
1112 }
1113
1114 static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1115 {
1116 #ifdef CONFIG_ANTENNA_DIVERSITY
1117         struct rtl_priv *rtlpriv = rtl_priv(hw);
1118         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1119         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1120
1121         if (pHalData->AntDivCfg == 0)
1122                 return;
1123
1124         if (rtlphy->rf_type == RF_1T1R) {
1125                 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1126                                 rtl_read_dword(rtlpriv,
1127                                 REG_LEDCFG0)|BIT(23));
1128                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1129                 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1130                     Antenna_A)
1131                         pHalData->CurAntenna = Antenna_A;
1132                 else
1133                         pHalData->CurAntenna = Antenna_B;
1134         }
1135 #endif
1136 }
1137
1138 static void _dump_registers(struct ieee80211_hw *hw)
1139 {
1140 }
1141
1142 static void _update_mac_setting(struct ieee80211_hw *hw)
1143 {
1144         struct rtl_priv *rtlpriv = rtl_priv(hw);
1145         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1146
1147         mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1148         mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1149         mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1150         mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1151 }
1152
1153 int rtl92cu_hw_init(struct ieee80211_hw *hw)
1154 {
1155         struct rtl_priv *rtlpriv = rtl_priv(hw);
1156         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1157         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1158         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1159         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1160         int err = 0;
1161         static bool iqk_initialized;
1162
1163         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1164         err = _rtl92cu_init_mac(hw);
1165         if (err) {
1166                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1167                 return err;
1168         }
1169         err = rtl92c_download_fw(hw);
1170         if (err) {
1171                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1172                          ("Failed to download FW. Init HW without FW now..\n"));
1173                 err = 1;
1174                 rtlhal->fw_ready = false;
1175                 return err;
1176         } else {
1177                 rtlhal->fw_ready = true;
1178         }
1179         rtlhal->last_hmeboxnum = 0; /* h2c */
1180         _rtl92cu_phy_param_tab_init(hw);
1181         rtl92cu_phy_mac_config(hw);
1182         rtl92cu_phy_bb_config(hw);
1183         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1184         rtl92c_phy_rf_config(hw);
1185         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1186             !IS_92C_SERIAL(rtlhal->version)) {
1187                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1188                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1189         }
1190         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1191                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1192         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1193                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1194         rtl92cu_bb_block_on(hw);
1195         rtl_cam_reset_all_entry(hw);
1196         rtl92cu_enable_hw_security_config(hw);
1197         ppsc->rfpwr_state = ERFON;
1198         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1199         if (ppsc->rfpwr_state == ERFON) {
1200                 rtl92c_phy_set_rfpath_switch(hw, 1);
1201                 if (iqk_initialized) {
1202                         rtl92c_phy_iq_calibrate(hw, false);
1203                 } else {
1204                         rtl92c_phy_iq_calibrate(hw, false);
1205                         iqk_initialized = true;
1206                 }
1207                 rtl92c_dm_check_txpower_tracking(hw);
1208                 rtl92c_phy_lc_calibrate(hw);
1209         }
1210         _rtl92cu_hw_configure(hw);
1211         _InitPABias(hw);
1212         _InitAntenna_Selection(hw);
1213         _update_mac_setting(hw);
1214         rtl92c_dm_init(hw);
1215         _dump_registers(hw);
1216         return err;
1217 }
1218
1219 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1220 {
1221         struct rtl_priv *rtlpriv = rtl_priv(hw);
1222 /**************************************
1223 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1224 b.      RF path 0 offset 0x00 = 0x00    disable RF
1225 c.      APSD_CTRL 0x600[7:0] = 0x40
1226 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1227 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1228 ***************************************/
1229         u8 eRFPath = 0, value8 = 0;
1230         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1231         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1232
1233         value8 |= APSDOFF;
1234         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1235         value8 = 0;
1236         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1237         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1238         value8 &= (~FEN_BB_GLB_RSTn);
1239         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1240 }
1241
1242 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1243 {
1244         struct rtl_priv *rtlpriv = rtl_priv(hw);
1245         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1246
1247         if (rtlhal->fw_version <=  0x20) {
1248                 /*****************************
1249                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1250                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1251                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1252                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1253                 ******************************/
1254                 u16 valu16 = 0;
1255
1256                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1257                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1258                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1259                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1260                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1261                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1262                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1263                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1264                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1265                                FEN_CPUEN)); /* enable MCU ,8051 */
1266         } else {
1267                 u8 retry_cnts = 0;
1268
1269                 /* IF fw in RAM code, do reset */
1270                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1271                         /* reset MCU ready status */
1272                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1273                         if (rtlhal->fw_ready) {
1274                                 /* 8051 reset by self */
1275                                 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1276                                 while ((retry_cnts++ < 100) &&
1277                                        (FEN_CPUEN & rtl_read_word(rtlpriv,
1278                                        REG_SYS_FUNC_EN))) {
1279                                         udelay(50);
1280                                 }
1281                                 if (retry_cnts >= 100) {
1282                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1283                                                 ("#####=> 8051 reset failed!.."
1284                                                 ".......................\n"););
1285                                         /* if 8051 reset fail, reset MAC. */
1286                                         rtl_write_byte(rtlpriv,
1287                                                        REG_SYS_FUNC_EN + 1,
1288                                                        0x50);
1289                                         udelay(100);
1290                                 }
1291                         }
1292                 }
1293                 /* Reset MAC and Enable 8051 */
1294                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1295                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1296         }
1297         if (bWithoutHWSM) {
1298                 /*****************************
1299                   Without HW auto state machine
1300                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1301                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1302                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1303                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1304                 ******************************/
1305                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1306                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1307                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1308                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1309         }
1310 }
1311
1312 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1313 {
1314         struct rtl_priv *rtlpriv = rtl_priv(hw);
1315 /*****************************
1316 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1317 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1318 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1319 ******************************/
1320         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1321         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1322 }
1323
1324 static void _DisableGPIO(struct ieee80211_hw *hw)
1325 {
1326         struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 /***************************************
1328 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1329 k. Value = GPIO_PIN_CTRL[7:0]
1330 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1331 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1332 n. LEDCFG 0x4C[15:0] = 0x8080
1333 ***************************************/
1334         u8      value8;
1335         u16     value16;
1336         u32     value32;
1337
1338         /* 1. Disable GPIO[7:0] */
1339         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1340         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1341         value8 = (u8) (value32&0x000000FF);
1342         value32 |= ((value8<<8) | 0x00FF0000);
1343         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1344         /* 2. Disable GPIO[10:8] */
1345         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1346         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1347         value8 = (u8) (value16&0x000F);
1348         value16 |= ((value8<<4) | 0x0780);
1349         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1350         /* 3. Disable LED0 & 1 */
1351         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1352 }
1353
1354 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1355 {
1356         struct rtl_priv *rtlpriv = rtl_priv(hw);
1357         u16 value16 = 0;
1358         u8 value8 = 0;
1359
1360         if (bWithoutHWSM) {
1361                 /*****************************
1362                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1363                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1364                 r. When driver call disable, the ASIC will turn off remaining
1365                    clock automatically
1366                 ******************************/
1367                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1368                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1369                 value8 &= (~LDV12_EN);
1370                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1371         }
1372
1373 /*****************************
1374 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1375 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1376 ******************************/
1377         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1378         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1379         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1380         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1381 }
1382
1383 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1384 {
1385         /* ==== RF Off Sequence ==== */
1386         _DisableRFAFEAndResetBB(hw);
1387         /* ==== Reset digital sequence   ====== */
1388         _ResetDigitalProcedure1(hw, false);
1389         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1390         _DisableGPIO(hw);
1391         /* ==== Disable analog sequence === */
1392         _DisableAnalog(hw, false);
1393 }
1394
1395 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1396 {
1397         /*==== RF Off Sequence ==== */
1398         _DisableRFAFEAndResetBB(hw);
1399         /*  ==== Reset digital sequence   ====== */
1400         _ResetDigitalProcedure1(hw, true);
1401         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1402         _DisableGPIO(hw);
1403         /*  ==== Reset digital sequence   ====== */
1404         _ResetDigitalProcedure2(hw);
1405         /*  ==== Disable analog sequence === */
1406         _DisableAnalog(hw, true);
1407 }
1408
1409 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1410                                       u8 set_bits, u8 clear_bits)
1411 {
1412         struct rtl_priv *rtlpriv = rtl_priv(hw);
1413         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1414
1415         rtlusb->reg_bcn_ctrl_val |= set_bits;
1416         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1417         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1418 }
1419
1420 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1421 {
1422         struct rtl_priv *rtlpriv = rtl_priv(hw);
1423         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1424         u8 tmp1byte = 0;
1425         if (IS_NORMAL_CHIP(rtlhal->version)) {
1426                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1427                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1428                                tmp1byte & (~BIT(6)));
1429                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1430                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1431                 tmp1byte &= ~(BIT(0));
1432                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1433         } else {
1434                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1435                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1436         }
1437 }
1438
1439 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1440 {
1441         struct rtl_priv *rtlpriv = rtl_priv(hw);
1442         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1443         u8 tmp1byte = 0;
1444
1445         if (IS_NORMAL_CHIP(rtlhal->version)) {
1446                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1447                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1448                                tmp1byte | BIT(6));
1449                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1450                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1451                 tmp1byte |= BIT(0);
1452                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1453         } else {
1454                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1455                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1456         }
1457 }
1458
1459 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1460 {
1461         struct rtl_priv *rtlpriv = rtl_priv(hw);
1462         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1463
1464         if (IS_NORMAL_CHIP(rtlhal->version))
1465                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1466         else
1467                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1468 }
1469
1470 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1471 {
1472         struct rtl_priv *rtlpriv = rtl_priv(hw);
1473         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1474
1475         if (IS_NORMAL_CHIP(rtlhal->version))
1476                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1477         else
1478                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1479 }
1480
1481 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1482                                      enum nl80211_iftype type)
1483 {
1484         struct rtl_priv *rtlpriv = rtl_priv(hw);
1485         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1486         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1487
1488         bt_msr &= 0xfc;
1489         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1490         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1491             NL80211_IFTYPE_STATION) {
1492                 _rtl92cu_stop_tx_beacon(hw);
1493                 _rtl92cu_enable_bcn_sub_func(hw);
1494         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1495                 _rtl92cu_resume_tx_beacon(hw);
1496                 _rtl92cu_disable_bcn_sub_func(hw);
1497         } else {
1498                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1499                          "STATUS:No such media status(%x).\n", type));
1500         }
1501         switch (type) {
1502         case NL80211_IFTYPE_UNSPECIFIED:
1503                 bt_msr |= MSR_NOLINK;
1504                 ledaction = LED_CTL_LINK;
1505                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1506                          ("Set Network type to NO LINK!\n"));
1507                 break;
1508         case NL80211_IFTYPE_ADHOC:
1509                 bt_msr |= MSR_ADHOC;
1510                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1511                          ("Set Network type to Ad Hoc!\n"));
1512                 break;
1513         case NL80211_IFTYPE_STATION:
1514                 bt_msr |= MSR_INFRA;
1515                 ledaction = LED_CTL_LINK;
1516                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1517                          ("Set Network type to STA!\n"));
1518                 break;
1519         case NL80211_IFTYPE_AP:
1520                 bt_msr |= MSR_AP;
1521                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1522                          ("Set Network type to AP!\n"));
1523                 break;
1524         default:
1525                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1526                          ("Network type %d not support!\n", type));
1527                 goto error_out;
1528         }
1529         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1530         rtlpriv->cfg->ops->led_control(hw, ledaction);
1531         if ((bt_msr & 0xfc) == MSR_AP)
1532                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1533         else
1534                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1535         return 0;
1536 error_out:
1537         return 1;
1538 }
1539
1540 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1541 {
1542         struct rtl_priv *rtlpriv = rtl_priv(hw);
1543         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1544         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1545         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1546         enum nl80211_iftype opmode;
1547
1548         mac->link_state = MAC80211_NOLINK;
1549         opmode = NL80211_IFTYPE_UNSPECIFIED;
1550         _rtl92cu_set_media_status(hw, opmode);
1551         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1552         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1553         if (rtlusb->disableHWSM)
1554                 _CardDisableHWSM(hw);
1555         else
1556                 _CardDisableWithoutHWSM(hw);
1557 }
1558
1559 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1560 {
1561         /* dummy routine needed for callback from rtl_op_configure_filter() */
1562 }
1563
1564 /*========================================================================== */
1565
1566 static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1567                               enum nl80211_iftype type)
1568 {
1569         struct rtl_priv *rtlpriv = rtl_priv(hw);
1570         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1571         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1572         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1573         u8 filterout_non_associated_bssid = false;
1574
1575         switch (type) {
1576         case NL80211_IFTYPE_ADHOC:
1577         case NL80211_IFTYPE_STATION:
1578                 filterout_non_associated_bssid = true;
1579                 break;
1580         case NL80211_IFTYPE_UNSPECIFIED:
1581         case NL80211_IFTYPE_AP:
1582         default:
1583                 break;
1584         }
1585         if (filterout_non_associated_bssid) {
1586                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1587                         switch (rtlphy->current_io_type) {
1588                         case IO_CMD_RESUME_DM_BY_SCAN:
1589                                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1590                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1591                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1592                                 /* enable update TSF */
1593                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1594                                 break;
1595                         case IO_CMD_PAUSE_DM_BY_SCAN:
1596                                 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1597                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1598                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1599                                 /* disable update TSF */
1600                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1601                                 break;
1602                         }
1603                 } else {
1604                         reg_rcr |= (RCR_CBSSID);
1605                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1606                                                       (u8 *)(&reg_rcr));
1607                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1608                 }
1609         } else if (filterout_non_associated_bssid == false) {
1610                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1611                         reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1612                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1613                                                       (u8 *)(&reg_rcr));
1614                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1615                 } else {
1616                         reg_rcr &= (~RCR_CBSSID);
1617                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1618                                                       (u8 *)(&reg_rcr));
1619                         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1620                 }
1621         }
1622 }
1623
1624 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1625 {
1626         if (_rtl92cu_set_media_status(hw, type))
1627                 return -EOPNOTSUPP;
1628         _rtl92cu_set_check_bssid(hw, type);
1629         return 0;
1630 }
1631
1632 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1633 {
1634         struct rtl_priv *rtlpriv = rtl_priv(hw);
1635         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1636
1637         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1638
1639         /* TODO: Remove these magic number */
1640         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1641         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1642         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1643         /* Change beacon AIFS to the largest number
1644          * beacause test chip does not contension before sending beacon. */
1645         if (IS_NORMAL_CHIP(rtlhal->version))
1646                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1647         else
1648                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1649 }
1650
1651 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1652                                     bool Linked)
1653 {
1654         struct rtl_priv *rtlpriv = rtl_priv(hw);
1655
1656         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1657         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1658 }
1659
1660 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1661 {
1662
1663         struct rtl_priv *rtlpriv = rtl_priv(hw);
1664         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1665         u16 bcn_interval, atim_window;
1666         u32 value32;
1667
1668         bcn_interval = mac->beacon_interval;
1669         atim_window = 2;        /*FIX MERGE */
1670         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1671         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1672         _InitBeaconParameters(hw);
1673         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1674         /*
1675          * Force beacon frame transmission even after receiving beacon frame
1676          * from other ad hoc STA
1677          *
1678          *
1679          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1680          */
1681         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1682         value32 &= ~TSFRST;
1683         rtl_write_dword(rtlpriv, REG_TCR, value32);
1684         value32 |= TSFRST;
1685         rtl_write_dword(rtlpriv, REG_TCR, value32);
1686         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1687                  ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1688                  value32));
1689         /* TODO: Modify later (Find the right parameters)
1690          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1691         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1692             (mac->opmode == NL80211_IFTYPE_AP)) {
1693                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1694                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1695         }
1696         _beacon_function_enable(hw, true, true);
1697 }
1698
1699 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1700 {
1701         struct rtl_priv *rtlpriv = rtl_priv(hw);
1702         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1703         u16 bcn_interval = mac->beacon_interval;
1704
1705         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1706                  ("beacon_interval:%d\n", bcn_interval));
1707         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1708 }
1709
1710 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1711                                    u32 add_msr, u32 rm_msr)
1712 {
1713 }
1714
1715 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1716 {
1717         struct rtl_priv *rtlpriv = rtl_priv(hw);
1718         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1719         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1720
1721         switch (variable) {
1722         case HW_VAR_RCR:
1723                 *((u32 *)(val)) = mac->rx_conf;
1724                 break;
1725         case HW_VAR_RF_STATE:
1726                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1727                 break;
1728         case HW_VAR_FWLPS_RF_ON:{
1729                         enum rf_pwrstate rfState;
1730                         u32 val_rcr;
1731
1732                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1733                                                       (u8 *)(&rfState));
1734                         if (rfState == ERFOFF) {
1735                                 *((bool *) (val)) = true;
1736                         } else {
1737                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1738                                 val_rcr &= 0x00070000;
1739                                 if (val_rcr)
1740                                         *((bool *) (val)) = false;
1741                                 else
1742                                         *((bool *) (val)) = true;
1743                         }
1744                         break;
1745                 }
1746         case HW_VAR_FW_PSMODE_STATUS:
1747                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1748                 break;
1749         case HW_VAR_CORRECT_TSF:{
1750                         u64 tsf;
1751                         u32 *ptsf_low = (u32 *)&tsf;
1752                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1753
1754                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1755                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1756                         *((u64 *)(val)) = tsf;
1757                         break;
1758                 }
1759         case HW_VAR_MGT_FILTER:
1760                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1761                 break;
1762         case HW_VAR_CTRL_FILTER:
1763                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1764                 break;
1765         case HW_VAR_DATA_FILTER:
1766                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1767                 break;
1768         default:
1769                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1770                          ("switch case not process\n"));
1771                 break;
1772         }
1773 }
1774
1775 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1776 {
1777         struct rtl_priv *rtlpriv = rtl_priv(hw);
1778         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1779         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1780         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1781         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1782         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1783         enum wireless_mode wirelessmode = mac->mode;
1784         u8 idx = 0;
1785
1786         switch (variable) {
1787         case HW_VAR_ETHER_ADDR:{
1788                         for (idx = 0; idx < ETH_ALEN; idx++) {
1789                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1790                                                val[idx]);
1791                         }
1792                         break;
1793                 }
1794         case HW_VAR_BASIC_RATE:{
1795                         u16 rate_cfg = ((u16 *) val)[0];
1796                         u8 rate_index = 0;
1797
1798                         rate_cfg &= 0x15f;
1799                         /* TODO */
1800                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1801                          *     && ((rate_cfg & 0x150) == 0)) {
1802                          *        rate_cfg |= 0x010;
1803                          * } */
1804                         rate_cfg |= 0x01;
1805                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1806                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1807                                        (rate_cfg >> 8) & 0xff);
1808                         while (rate_cfg > 0x1) {
1809                                 rate_cfg >>= 1;
1810                                 rate_index++;
1811                         }
1812                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1813                                        rate_index);
1814                         break;
1815                 }
1816         case HW_VAR_BSSID:{
1817                         for (idx = 0; idx < ETH_ALEN; idx++) {
1818                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1819                                                val[idx]);
1820                         }
1821                         break;
1822                 }
1823         case HW_VAR_SIFS:{
1824                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1825                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1826                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1827                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1828                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1829                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1830                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1831                                  ("HW_VAR_SIFS\n"));
1832                         break;
1833                 }
1834         case HW_VAR_SLOT_TIME:{
1835                         u8 e_aci;
1836                         u8 QOS_MODE = 1;
1837
1838                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1839                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1840                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
1841                         if (QOS_MODE) {
1842                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1843                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1844                                                                 HW_VAR_AC_PARAM,
1845                                                                 (u8 *)(&e_aci));
1846                         } else {
1847                                 u8 sifstime = 0;
1848                                 u8      u1bAIFS;
1849
1850                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1851                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1852                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1853                                         sifstime = 16;
1854                                 else
1855                                         sifstime = 10;
1856                                 u1bAIFS = sifstime + (2 *  val[0]);
1857                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1858                                                u1bAIFS);
1859                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1860                                                u1bAIFS);
1861                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1862                                                u1bAIFS);
1863                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1864                                                u1bAIFS);
1865                         }
1866                         break;
1867                 }
1868         case HW_VAR_ACK_PREAMBLE:{
1869                         u8 reg_tmp;
1870                         u8 short_preamble = (bool) (*(u8 *) val);
1871                         reg_tmp = 0;
1872                         if (short_preamble)
1873                                 reg_tmp |= 0x80;
1874                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1875                         break;
1876                 }
1877         case HW_VAR_AMPDU_MIN_SPACE:{
1878                         u8 min_spacing_to_set;
1879                         u8 sec_min_space;
1880
1881                         min_spacing_to_set = *((u8 *) val);
1882                         if (min_spacing_to_set <= 7) {
1883                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1884                                 case NO_ENCRYPTION:
1885                                 case AESCCMP_ENCRYPTION:
1886                                         sec_min_space = 0;
1887                                         break;
1888                                 case WEP40_ENCRYPTION:
1889                                 case WEP104_ENCRYPTION:
1890                                 case TKIP_ENCRYPTION:
1891                                         sec_min_space = 6;
1892                                         break;
1893                                 default:
1894                                         sec_min_space = 7;
1895                                         break;
1896                                 }
1897                                 if (min_spacing_to_set < sec_min_space)
1898                                         min_spacing_to_set = sec_min_space;
1899                                 mac->min_space_cfg = ((mac->min_space_cfg &
1900                                                      0xf8) |
1901                                                      min_spacing_to_set);
1902                                 *val = min_spacing_to_set;
1903                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1904                                         ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1905                                         mac->min_space_cfg));
1906                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1907                                                mac->min_space_cfg);
1908                         }
1909                         break;
1910                 }
1911         case HW_VAR_SHORTGI_DENSITY:{
1912                         u8 density_to_set;
1913
1914                         density_to_set = *((u8 *) val);
1915                         density_to_set &= 0x1f;
1916                         mac->min_space_cfg &= 0x07;
1917                         mac->min_space_cfg |= (density_to_set << 3);
1918                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1919                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1920                                   mac->min_space_cfg));
1921                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1922                                        mac->min_space_cfg);
1923                         break;
1924                 }
1925         case HW_VAR_AMPDU_FACTOR:{
1926                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1927                         u8 factor_toset;
1928                         u8 *p_regtoset = NULL;
1929                         u8 index = 0;
1930
1931                         p_regtoset = regtoset_normal;
1932                         factor_toset = *((u8 *) val);
1933                         if (factor_toset <= 3) {
1934                                 factor_toset = (1 << (factor_toset + 2));
1935                                 if (factor_toset > 0xf)
1936                                         factor_toset = 0xf;
1937                                 for (index = 0; index < 4; index++) {
1938                                         if ((p_regtoset[index] & 0xf0) >
1939                                             (factor_toset << 4))
1940                                                 p_regtoset[index] =
1941                                                      (p_regtoset[index] & 0x0f)
1942                                                      | (factor_toset << 4);
1943                                         if ((p_regtoset[index] & 0x0f) >
1944                                              factor_toset)
1945                                                 p_regtoset[index] =
1946                                                      (p_regtoset[index] & 0xf0)
1947                                                      | (factor_toset);
1948                                         rtl_write_byte(rtlpriv,
1949                                                        (REG_AGGLEN_LMT + index),
1950                                                        p_regtoset[index]);
1951                                 }
1952                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1953                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1954                                           factor_toset));
1955                         }
1956                         break;
1957                 }
1958         case HW_VAR_AC_PARAM:{
1959                         u8 e_aci = *((u8 *) val);
1960                         u32 u4b_ac_param;
1961                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1962                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1963                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1964
1965                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1966                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1967                                          AC_PARAM_ECW_MIN_OFFSET);
1968                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1969                                          AC_PARAM_ECW_MAX_OFFSET);
1970                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1971                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1972                                  ("queue:%x, ac_param:%x\n", e_aci,
1973                                   u4b_ac_param));
1974                         switch (e_aci) {
1975                         case AC1_BK:
1976                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1977                                                 u4b_ac_param);
1978                                 break;
1979                         case AC0_BE:
1980                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1981                                                 u4b_ac_param);
1982                                 break;
1983                         case AC2_VI:
1984                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1985                                                 u4b_ac_param);
1986                                 break;
1987                         case AC3_VO:
1988                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1989                                                 u4b_ac_param);
1990                                 break;
1991                         default:
1992                                 RT_ASSERT(false, ("SetHwReg8185(): invalid"
1993                                           " aci: %d !\n", e_aci));
1994                                 break;
1995                         }
1996                         if (rtlusb->acm_method != eAcmWay2_SW)
1997                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1998                                          HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
1999                         break;
2000                 }
2001         case HW_VAR_ACM_CTRL:{
2002                         u8 e_aci = *((u8 *) val);
2003                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2004                                                         (&(mac->ac[0].aifs));
2005                         u8 acm = p_aci_aifsn->f.acm;
2006                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2007
2008                         acm_ctrl =
2009                             acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2010                         if (acm) {
2011                                 switch (e_aci) {
2012                                 case AC0_BE:
2013                                         acm_ctrl |= AcmHw_BeqEn;
2014                                         break;
2015                                 case AC2_VI:
2016                                         acm_ctrl |= AcmHw_ViqEn;
2017                                         break;
2018                                 case AC3_VO:
2019                                         acm_ctrl |= AcmHw_VoqEn;
2020                                         break;
2021                                 default:
2022                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2023                                                  ("HW_VAR_ACM_CTRL acm set "
2024                                                   "failed: eACI is %d\n", acm));
2025                                         break;
2026                                 }
2027                         } else {
2028                                 switch (e_aci) {
2029                                 case AC0_BE:
2030                                         acm_ctrl &= (~AcmHw_BeqEn);
2031                                         break;
2032                                 case AC2_VI:
2033                                         acm_ctrl &= (~AcmHw_ViqEn);
2034                                         break;
2035                                 case AC3_VO:
2036                                         acm_ctrl &= (~AcmHw_BeqEn);
2037                                         break;
2038                                 default:
2039                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2040                                                  ("switch case not process\n"));
2041                                         break;
2042                                 }
2043                         }
2044                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2045                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2046                                   "Write 0x%X\n", acm_ctrl));
2047                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2048                         break;
2049                 }
2050         case HW_VAR_RCR:{
2051                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2052                         mac->rx_conf = ((u32 *) (val))[0];
2053                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2054                                  ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2055                         break;
2056                 }
2057         case HW_VAR_RETRY_LIMIT:{
2058                         u8 retry_limit = ((u8 *) (val))[0];
2059
2060                         rtl_write_word(rtlpriv, REG_RL,
2061                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2062                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
2063                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2064                                  "ETRY_LIMIT(0x%08x)\n", retry_limit));
2065                         break;
2066                 }
2067         case HW_VAR_DUAL_TSF_RST:
2068                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2069                 break;
2070         case HW_VAR_EFUSE_BYTES:
2071                 rtlefuse->efuse_usedbytes = *((u16 *) val);
2072                 break;
2073         case HW_VAR_EFUSE_USAGE:
2074                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2075                 break;
2076         case HW_VAR_IO_CMD:
2077                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2078                 break;
2079         case HW_VAR_WPA_CONFIG:
2080                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2081                 break;
2082         case HW_VAR_SET_RPWM:{
2083                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2084
2085                         if (rpwm_val & BIT(7))
2086                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2087                                                (*(u8 *)val));
2088                         else
2089                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2090                                                ((*(u8 *)val) | BIT(7)));
2091                         break;
2092                 }
2093         case HW_VAR_H2C_FW_PWRMODE:{
2094                         u8 psmode = (*(u8 *) val);
2095
2096                         if ((psmode != FW_PS_ACTIVE_MODE) &&
2097                            (!IS_92C_SERIAL(rtlhal->version)))
2098                                 rtl92c_dm_rf_saving(hw, true);
2099                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2100                         break;
2101                 }
2102         case HW_VAR_FW_PSMODE_STATUS:
2103                 ppsc->fw_current_inpsmode = *((bool *) val);
2104                 break;
2105         case HW_VAR_H2C_FW_JOINBSSRPT:{
2106                         u8 mstatus = (*(u8 *) val);
2107                         u8 tmp_reg422;
2108                         bool recover = false;
2109
2110                         if (mstatus == RT_MEDIA_CONNECT) {
2111                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2112                                                          HW_VAR_AID, NULL);
2113                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2114                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2115                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2116                                 tmp_reg422 = rtl_read_byte(rtlpriv,
2117                                                         REG_FWHW_TXQ_CTRL + 2);
2118                                 if (tmp_reg422 & BIT(6))
2119                                         recover = true;
2120                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2121                                                tmp_reg422 & (~BIT(6)));
2122                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2123                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2124                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2125                                 if (recover)
2126                                         rtl_write_byte(rtlpriv,
2127                                                  REG_FWHW_TXQ_CTRL + 2,
2128                                                 tmp_reg422 | BIT(6));
2129                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2130                         }
2131                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2132                         break;
2133                 }
2134         case HW_VAR_AID:{
2135                         u16 u2btmp;
2136
2137                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2138                         u2btmp &= 0xC000;
2139                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2140                                        (u2btmp | mac->assoc_id));
2141                         break;
2142                 }
2143         case HW_VAR_CORRECT_TSF:{
2144                         u8 btype_ibss = ((u8 *) (val))[0];
2145
2146                         if (btype_ibss)
2147                                 _rtl92cu_stop_tx_beacon(hw);
2148                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2149                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2150                                         0xffffffff));
2151                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2152                                         (u32)((mac->tsf >> 32) & 0xffffffff));
2153                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2154                         if (btype_ibss)
2155                                 _rtl92cu_resume_tx_beacon(hw);
2156                         break;
2157                 }
2158         case HW_VAR_MGT_FILTER:
2159                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2160                 break;
2161         case HW_VAR_CTRL_FILTER:
2162                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2163                 break;
2164         case HW_VAR_DATA_FILTER:
2165                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2166                 break;
2167         default:
2168                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2169                                                         "not process\n"));
2170                 break;
2171         }
2172 }
2173
2174 void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2175                                    struct ieee80211_sta *sta,
2176                                    u8 rssi_level)
2177 {
2178         struct rtl_priv *rtlpriv = rtl_priv(hw);
2179         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2180         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2181         u32 ratr_value = (u32) mac->basic_rates;
2182         u8 *mcsrate = mac->mcs;
2183         u8 ratr_index = 0;
2184         u8 nmode = mac->ht_enable;
2185         u8 mimo_ps = 1;
2186         u16 shortgi_rate = 0;
2187         u32 tmp_ratr_value = 0;
2188         u8 curtxbw_40mhz = mac->bw_40;
2189         u8 curshortgi_40mhz = mac->sgi_40;
2190         u8 curshortgi_20mhz = mac->sgi_20;
2191         enum wireless_mode wirelessmode = mac->mode;
2192
2193         ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2194         switch (wirelessmode) {
2195         case WIRELESS_MODE_B:
2196                 if (ratr_value & 0x0000000c)
2197                         ratr_value &= 0x0000000d;
2198                 else
2199                         ratr_value &= 0x0000000f;
2200                 break;
2201         case WIRELESS_MODE_G:
2202                 ratr_value &= 0x00000FF5;
2203                 break;
2204         case WIRELESS_MODE_N_24G:
2205         case WIRELESS_MODE_N_5G:
2206                 nmode = 1;
2207                 if (mimo_ps == 0) {
2208                         ratr_value &= 0x0007F005;
2209                 } else {
2210                         u32 ratr_mask;
2211
2212                         if (get_rf_type(rtlphy) == RF_1T2R ||
2213                             get_rf_type(rtlphy) == RF_1T1R)
2214                                 ratr_mask = 0x000ff005;
2215                         else
2216                                 ratr_mask = 0x0f0ff005;
2217                         if (curtxbw_40mhz)
2218                                 ratr_mask |= 0x00000010;
2219                         ratr_value &= ratr_mask;
2220                 }
2221                 break;
2222         default:
2223                 if (rtlphy->rf_type == RF_1T2R)
2224                         ratr_value &= 0x000ff0ff;
2225                 else
2226                         ratr_value &= 0x0f0ff0ff;
2227                 break;
2228         }
2229         ratr_value &= 0x0FFFFFFF;
2230         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2231             (!curtxbw_40mhz && curshortgi_20mhz))) {
2232                 ratr_value |= 0x10000000;
2233                 tmp_ratr_value = (ratr_value >> 12);
2234                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2235                         if ((1 << shortgi_rate) & tmp_ratr_value)
2236                                 break;
2237                 }
2238                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2239                                (shortgi_rate << 4) | (shortgi_rate);
2240         }
2241         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2242         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2243                  REG_ARFR0)));
2244 }
2245
2246 void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2247 {
2248         struct rtl_priv *rtlpriv = rtl_priv(hw);
2249         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2250         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2251         u32 ratr_bitmap = (u32) mac->basic_rates;
2252         u8 *p_mcsrate = mac->mcs;
2253         u8 ratr_index = 0;
2254         u8 curtxbw_40mhz = mac->bw_40;
2255         u8 curshortgi_40mhz = mac->sgi_40;
2256         u8 curshortgi_20mhz = mac->sgi_20;
2257         enum wireless_mode wirelessmode = mac->mode;
2258         bool shortgi = false;
2259         u8 rate_mask[5];
2260         u8 macid = 0;
2261         u8 mimops = 1;
2262
2263         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2264         switch (wirelessmode) {
2265         case WIRELESS_MODE_B:
2266                 ratr_index = RATR_INX_WIRELESS_B;
2267                 if (ratr_bitmap & 0x0000000c)
2268                         ratr_bitmap &= 0x0000000d;
2269                 else
2270                         ratr_bitmap &= 0x0000000f;
2271                 break;
2272         case WIRELESS_MODE_G:
2273                 ratr_index = RATR_INX_WIRELESS_GB;
2274                 if (rssi_level == 1)
2275                         ratr_bitmap &= 0x00000f00;
2276                 else if (rssi_level == 2)
2277                         ratr_bitmap &= 0x00000ff0;
2278                 else
2279                         ratr_bitmap &= 0x00000ff5;
2280                 break;
2281         case WIRELESS_MODE_A:
2282                 ratr_index = RATR_INX_WIRELESS_A;
2283                 ratr_bitmap &= 0x00000ff0;
2284                 break;
2285         case WIRELESS_MODE_N_24G:
2286         case WIRELESS_MODE_N_5G:
2287                 ratr_index = RATR_INX_WIRELESS_NGB;
2288                 if (mimops == 0) {
2289                         if (rssi_level == 1)
2290                                 ratr_bitmap &= 0x00070000;
2291                         else if (rssi_level == 2)
2292                                 ratr_bitmap &= 0x0007f000;
2293                         else
2294                                 ratr_bitmap &= 0x0007f005;
2295                 } else {
2296                         if (rtlphy->rf_type == RF_1T2R ||
2297                             rtlphy->rf_type == RF_1T1R) {
2298                                 if (curtxbw_40mhz) {
2299                                         if (rssi_level == 1)
2300                                                 ratr_bitmap &= 0x000f0000;
2301                                         else if (rssi_level == 2)
2302                                                 ratr_bitmap &= 0x000ff000;
2303                                         else
2304                                                 ratr_bitmap &= 0x000ff015;
2305                                 } else {
2306                                         if (rssi_level == 1)
2307                                                 ratr_bitmap &= 0x000f0000;
2308                                         else if (rssi_level == 2)
2309                                                 ratr_bitmap &= 0x000ff000;
2310                                         else
2311                                                 ratr_bitmap &= 0x000ff005;
2312                                 }
2313                         } else {
2314                                 if (curtxbw_40mhz) {
2315                                         if (rssi_level == 1)
2316                                                 ratr_bitmap &= 0x0f0f0000;
2317                                         else if (rssi_level == 2)
2318                                                 ratr_bitmap &= 0x0f0ff000;
2319                                         else
2320                                                 ratr_bitmap &= 0x0f0ff015;
2321                                 } else {
2322                                         if (rssi_level == 1)
2323                                                 ratr_bitmap &= 0x0f0f0000;
2324                                         else if (rssi_level == 2)
2325                                                 ratr_bitmap &= 0x0f0ff000;
2326                                         else
2327                                                 ratr_bitmap &= 0x0f0ff005;
2328                                 }
2329                         }
2330                 }
2331                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2332                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2333                         if (macid == 0)
2334                                 shortgi = true;
2335                         else if (macid == 1)
2336                                 shortgi = false;
2337                 }
2338                 break;
2339         default:
2340                 ratr_index = RATR_INX_WIRELESS_NGB;
2341                 if (rtlphy->rf_type == RF_1T2R)
2342                         ratr_bitmap &= 0x000ff0ff;
2343                 else
2344                         ratr_bitmap &= 0x0f0ff0ff;
2345                 break;
2346         }
2347         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2348                  ratr_bitmap));
2349         *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2350                                       ratr_index << 28);
2351         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2352         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2353                                                 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2354                                                 ratr_index, ratr_bitmap,
2355                                                 rate_mask[0], rate_mask[1],
2356                                                 rate_mask[2], rate_mask[3],
2357                                                 rate_mask[4]));
2358         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2359 }
2360
2361 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2362 {
2363         struct rtl_priv *rtlpriv = rtl_priv(hw);
2364         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2365         u16 sifs_timer;
2366
2367         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2368                                       (u8 *)&mac->slot_time);
2369         if (!mac->ht_enable)
2370                 sifs_timer = 0x0a0a;
2371         else
2372                 sifs_timer = 0x0e0e;
2373         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2374 }
2375
2376 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2377 {
2378         struct rtl_priv *rtlpriv = rtl_priv(hw);
2379         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2380         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2381         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2382         u8 u1tmp = 0;
2383         bool actuallyset = false;
2384         unsigned long flag = 0;
2385         /* to do - usb autosuspend */
2386         u8 usb_autosuspend = 0;
2387
2388         if (ppsc->swrf_processing)
2389                 return false;
2390         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2391         if (ppsc->rfchange_inprogress) {
2392                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2393                 return false;
2394         } else {
2395                 ppsc->rfchange_inprogress = true;
2396                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2397         }
2398         cur_rfstate = ppsc->rfpwr_state;
2399         if (usb_autosuspend) {
2400                 /* to do................... */
2401         } else {
2402                 if (ppsc->pwrdown_mode) {
2403                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2404                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2405                                                ERFOFF : ERFON;
2406                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2407                                  ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2408                 } else {
2409                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2410                                        rtl_read_byte(rtlpriv,
2411                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2412                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2413                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2414                                                  ERFON : ERFOFF;
2415                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2416                                 ("GPIO_IN=%02x\n", u1tmp));
2417                 }
2418                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2419                          e_rfpowerstate_toset));
2420         }
2421         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2422                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF  - HW "
2423                          "Radio ON, RF ON\n"));
2424                 ppsc->hwradiooff = false;
2425                 actuallyset = true;
2426         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2427                     ERFOFF)) {
2428                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF  - HW"
2429                          " Radio OFF\n"));
2430                 ppsc->hwradiooff = true;
2431                 actuallyset = true;
2432         } else {
2433                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2434                          ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2435                          " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2436                          "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2437         }
2438         if (actuallyset) {
2439                 ppsc->hwradiooff = true;
2440                 if (e_rfpowerstate_toset == ERFON) {
2441                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2442                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2443                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2444                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2445                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2446                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2447                 }
2448                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2449                 ppsc->rfchange_inprogress = false;
2450                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2451                 /* For power down module, we need to enable register block
2452                  * contrl reg at 0x1c. Then enable power down control bit
2453                  * of register 0x04 BIT4 and BIT15 as 1.
2454                  */
2455                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2456                         /* Enable register area 0x0-0xc. */
2457                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2458                         if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2459                                 /*
2460                                  * We should configure HW PDn source for WiFi
2461                                  * ONLY, and then our HW will be set in
2462                                  * power-down mode if PDn source from all
2463                                  * functions are configured.
2464                                  */
2465                                 u1tmp = rtl_read_byte(rtlpriv,
2466                                                       REG_MULTI_FUNC_CTRL);
2467                                 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2468                                                (u1tmp|WL_HWPDN_EN));
2469                         } else {
2470                                 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2471                         }
2472                 }
2473                 if (e_rfpowerstate_toset == ERFOFF) {
2474                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2475                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2476                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2477                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2478                 }
2479         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2480                 /* Enter D3 or ASPM after GPIO had been done. */
2481                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2482                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2483                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2484                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2485                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2486                 ppsc->rfchange_inprogress = false;
2487                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2488         } else {
2489                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2490                 ppsc->rfchange_inprogress = false;
2491                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2492         }
2493         *valid = 1;
2494         return !ppsc->hwradiooff;
2495 }