1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
29 #ifndef __REALTEK_FIRMWARE92S_H__
30 #define __REALTEK_FIRMWARE92S_H__
32 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
33 #define RTL8190_CPU_START_OFFSET 0x80
34 /* Firmware Local buffer size. 64k */
35 #define MAX_FIRMWARE_CODE_SIZE 0xFF00
37 #define RT_8192S_FIRMWARE_HDR_SIZE 80
38 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
40 /* support till 64 bit bus width OS */
41 #define MAX_DEV_ADDR_SIZE 8
42 #define MAX_FIRMWARE_INFORMATION_SIZE 32
43 #define MAX_802_11_HEADER_LENGTH (40 + \
44 MAX_FIRMWARE_INFORMATION_SIZE)
45 #define ENCRYPTION_MAX_OVERHEAD 128
46 #define MAX_FRAGMENT_COUNT 8
47 #define MAX_TRANSMIT_BUFFER_SIZE (1600 + \
48 (MAX_802_11_HEADER_LENGTH + \
49 ENCRYPTION_MAX_OVERHEAD) *\
52 #define H2C_TX_CMD_HDR_LEN 8
54 /* The following DM control code are for Reg0x364, */
55 #define FW_DIG_ENABLE_CTL BIT(0)
56 #define FW_HIGH_PWR_ENABLE_CTL BIT(1)
57 #define FW_SS_CTL BIT(2)
58 #define FW_RA_INIT_CTL BIT(3)
59 #define FW_RA_BG_CTL BIT(4)
60 #define FW_RA_N_CTL BIT(5)
61 #define FW_PWR_TRK_CTL BIT(6)
62 #define FW_IQK_CTL BIT(7)
63 #define FW_FA_CTL BIT(8)
64 #define FW_DRIVER_CTRL_DM_CTL BIT(9)
65 #define FW_PAPE_CTL_BY_SW_HW BIT(10)
66 #define FW_DISABLE_ALL_DM 0
67 #define FW_PWR_TRK_PARAM_CLR 0x0000ffff
68 #define FW_RA_PARAM_CLR 0xffff0000
70 enum desc_packet_type {
71 DESC_PACKET_TYPE_INIT = 0,
72 DESC_PACKET_TYPE_NORMAL = 1,
75 /* 8-bytes alignment required */
77 /* --- long word 0 ---- */
78 /* 0x12: CE product, 0x92: IT product */
80 /* 0x87: CE product, 0x81: IT product */
82 /* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
83 * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
85 /* the same value as reigster value */
87 /* customer ID low byte */
89 /* customer ID high byte */
91 /* 0x11: 1T1R, 0x12: 1T2R,
92 * 0x92: 1T2R turbo, 0x22: 2T2R */
94 /* 4: 4EP, 6: 6EP, 11: 11EP */
97 /* --- long word 1 ---- */
98 /* regulatory class bit map 0 */
99 u8 regulatory_class_0;
100 /* regulatory class bit map 1 */
101 u8 regulatory_class_1;
102 /* regulatory class bit map 2 */
103 u8 regulatory_class_2;
104 /* regulatory class bit map 3 */
105 u8 regulatory_class_3;
106 /* 0:SWSI, 1:HWSI, 2:HWPI */
112 /* --- long word 2 ---- */
113 /* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
115 /* 1: for MP use, 0: for normal
116 * driver (to be discussed) */
125 /* --- long word 3 ---- */
128 /* 40MHz BW enable */
129 /* 4181 convert AMSDU to AMPDU, 0: disable */
132 /* 11n AMPDU enable */
134 /* FW offloads, 0: driver handles */
135 u8 rate_control_offload;
136 /* FW offloads, 0: driver handles */
137 u8 aggregation_offload;
141 /* --- long word 4 ---- */
142 /* 1. FW offloads, 0: driver handles */
144 /* 2. FW offloads, 0: driver handles */
146 /* 3. FW offloads, 0: driver handles */
148 /* 4. FW offloads, 0: driver handles */
149 u8 tcp_checksum_offload;
150 /* 5. FW offloads, 0: driver handles */
152 /* 6. FW offloads, 0: driver handles */
153 u8 ps_control_offload;
154 /* 7. FW offloads, 0: driver handles */
158 /* --- long word 5 ---- */
159 /* tcp tx packet length low byte */
160 u8 tcp_tx_frame_len_L;
161 /* tcp tx packet length high byte */
162 u8 tcp_tx_frame_len_H;
163 /* tcp rx packet length low byte */
164 u8 tcp_rx_frame_len_L;
165 /* tcp rx packet length high byte */
166 u8 tcp_rx_frame_len_H;
173 /* 8-byte alinment required */
176 /* --- LONG WORD 0 ---- */
178 /* 0x8000 ~ 0x8FFF for FPGA version,
179 * 0x0000 ~ 0x7FFF for ASIC version, */
181 /* define the size of boot loader */
185 /* --- LONG WORD 1 ---- */
186 /* define the size of FW in IMEM */
188 /* define the size of FW in SRAM */
191 /* --- LONG WORD 2 ---- */
192 /* define the size of DMEM variable */
196 /* --- LONG WORD 3 ---- */
200 struct fw_priv fwpriv;
206 FW_STATUS_LOAD_IMEM = 1,
207 FW_STATUS_LOAD_EMEM = 2,
208 FW_STATUS_LOAD_DMEM = 3,
213 struct fw_hdr *pfwheader;
214 enum fw_status fwstatus;
216 u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
217 u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
220 u8 sz_fw_tmpbuffer[164000];
221 u32 sz_fw_tmpbufferlen;
222 u16 cmdpacket_fragthresold;
225 struct h2c_set_pwrmode_parm {
227 u8 flag_low_traffic_en;
229 u8 flag_rf_low_snr_en;
234 /* beacon TO (ms). ¡§=0¡¨ no limit. */
237 /* only for VOIP mode. */
245 struct h2c_joinbss_rpt_parm {
254 /* EAPOL-Key Key Confirmation Key (KCK) */
256 /* EAPOL-Key Key Encryption Key (KEK) */
258 /* Temporal Key 1 (TK1) */
261 /* Temporal Key 2 (TK2) */
270 struct h2c_wpa_two_way_parm {
271 /* algorithm TKIP or AES */
274 struct h2c_wpa_ptk wpa_ptk_value;
278 FW_H2C_SETPWRMODE = 0,
279 FW_H2C_JOINBSSRPT = 1,
280 FW_H2C_WOWLAN_UPDATE_GTK = 2,
281 FW_H2C_WOWLAN_UPDATE_IV = 3,
282 FW_H2C_WOWLAN_OFFLOAD = 4,
286 H2C_READ_MACREG_CMD, /*0*/
287 H2C_WRITE_MACREG_CMD,
291 H2C_WRITERF_CMD, /*5*/
293 H2C_WRITE_EEPROM_CMD,
296 H2C_READ_CAM_CMD, /*10*/
301 H2C_DISCONNECT_CMD, /*15*/
306 H2C_SETKEY_CMD, /*20*/
310 H2C_SETSTAPWRSTATE_CMD,
311 H2C_SETBASICRATE_CMD, /*25*/
312 H2C_GETBASICRATE_CMD,
316 H2C_GETPHYINFO_CMD, /*30*/
321 H2C_SETATIM_CMD, /*35*/
326 H2C_GETCCXREPORT_CMD, /*40*/
327 H2C_GETDTMREPORT_CMD,
328 H2C_GETTXRATESTATICS_CMD,
329 H2C_SETUSBSUSPEND_CMD,
332 H2C_WOWLAN_UPDATE_GTK_CMD,
333 H2C_WOWLAN_FW_OFFLOAD,
336 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
341 /* The following macros are used for FW
342 * CMD map and parameter updated. */
343 #define FW_CMD_IO_CLR(rtlpriv, _Bit) \
346 rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \
349 #define FW_CMD_IO_UPDATE(rtlpriv, _val) \
350 rtlpriv->rtlhal.fwcmd_iomap = _val;
352 #define FW_CMD_IO_SET(rtlpriv, _val) \
354 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
355 FW_CMD_IO_UPDATE(rtlpriv, _val); \
358 #define FW_CMD_PARA_SET(rtlpriv, _val) \
360 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
361 rtlpriv->rtlhal.fwcmd_ioparam = _val; \
364 #define FW_CMD_IO_QUERY(rtlpriv) \
365 (u16)(rtlpriv->rtlhal.fwcmd_iomap)
366 #define FW_CMD_IO_PARA_QUERY(rtlpriv) \
367 ((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
369 int rtl92s_download_fw(struct ieee80211_hw *hw);
370 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
371 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
372 u8 mstatus, u8 ps_qosinfo);