1 /******************************************************************************
3 * Copyright(c) 2009-2014 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
27 #include "phy_common.h"
28 #include "../rtl8723ae/reg.h"
29 #include <linux/module.h>
31 /* These routines are common to RTL8723AE and RTL8723bE */
33 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
34 u32 regaddr, u32 bitmask)
36 struct rtl_priv *rtlpriv = rtl_priv(hw);
37 u32 returnvalue, originalvalue, bitshift;
39 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
40 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
41 originalvalue = rtl_read_dword(rtlpriv, regaddr);
42 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
43 returnvalue = (originalvalue & bitmask) >> bitshift;
45 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
46 "BBR MASK = 0x%x Addr[0x%x]= 0x%x\n",
47 bitmask, regaddr, originalvalue);
51 EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg);
53 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
54 u32 bitmask, u32 data)
56 struct rtl_priv *rtlpriv = rtl_priv(hw);
57 u32 originalvalue, bitshift;
59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
60 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
61 regaddr, bitmask, data);
63 if (bitmask != MASKDWORD) {
64 originalvalue = rtl_read_dword(rtlpriv, regaddr);
65 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
66 data = ((originalvalue & (~bitmask)) | (data << bitshift));
69 rtl_write_dword(rtlpriv, regaddr, data);
71 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
72 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
73 regaddr, bitmask, data);
75 EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg);
77 u32 rtl8723_phy_calculate_bit_shift(u32 bitmask)
81 for (i = 0; i <= 31; i++) {
82 if (((bitmask >> i) & 0x1) == 1)
87 EXPORT_SYMBOL_GPL(rtl8723_phy_calculate_bit_shift);
89 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
90 enum radio_path rfpath, u32 offset)
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_phy *rtlphy = &(rtlpriv->phy);
94 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
96 u32 tmplong, tmplong2;
102 if (RT_CANNOT_IO(hw)) {
103 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
106 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
107 if (rfpath == RF90_PATH_A)
110 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
111 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
112 (newoffset << 23) | BLSSIREADEDGE;
113 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
114 tmplong & (~BLSSIREADEDGE));
116 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
118 if (rfpath == RF90_PATH_A)
119 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
121 else if (rfpath == RF90_PATH_B)
122 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
125 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
128 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
130 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
131 "RFR-%d Addr[0x%x]= 0x%x\n",
132 rfpath, pphyreg->rf_rb, retvalue);
135 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read);
137 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
138 enum radio_path rfpath,
139 u32 offset, u32 data)
143 struct rtl_priv *rtlpriv = rtl_priv(hw);
144 struct rtl_phy *rtlphy = &(rtlpriv->phy);
145 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
147 if (RT_CANNOT_IO(hw)) {
148 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
153 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
154 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
155 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
156 "RFW-%d Addr[0x%x]= 0x%x\n", rfpath,
157 pphyreg->rf3wire_offset, data_and_addr);
159 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write);
161 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
162 enum wireless_mode wirelessmode,
168 switch (wirelessmode) {
169 case WIRELESS_MODE_B:
172 case WIRELESS_MODE_G:
173 case WIRELESS_MODE_N_24G:
178 pwrout_dbm = txpwridx / 2 + offset;
181 EXPORT_SYMBOL_GPL(rtl8723_phy_txpwr_idx_to_dbm);
183 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
185 struct rtl_priv *rtlpriv = rtl_priv(hw);
186 struct rtl_phy *rtlphy = &(rtlpriv->phy);
188 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
189 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
190 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
191 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
193 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
194 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
195 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
196 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
198 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
199 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
201 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
202 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
204 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
205 RFPGA0_XA_LSSIPARAMETER;
206 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
207 RFPGA0_XB_LSSIPARAMETER;
209 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
210 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
211 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
212 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
214 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
215 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
216 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
217 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
219 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
220 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
222 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
223 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
225 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
226 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
227 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
228 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
230 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
231 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
232 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
233 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
235 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
236 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
237 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
238 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
240 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
241 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
242 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
243 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
245 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
246 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
247 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
248 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
250 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
251 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
252 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
253 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
255 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
256 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
257 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
258 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
260 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
261 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
262 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
263 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
265 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
266 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
268 EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def);
270 bool rtl8723_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
273 enum swchnlcmd_id cmdid,
274 u32 para1, u32 para2,
277 struct swchnlcmd *pcmd;
279 if (cmdtable == NULL) {
280 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
284 if (cmdtableidx >= cmdtablesz)
287 pcmd = cmdtable + cmdtableidx;
291 pcmd->msdelay = msdelay;
294 EXPORT_SYMBOL_GPL(rtl8723_phy_set_sw_chnl_cmdarray);
296 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
302 u32 oldval_0, x, tx0_a, reg;
305 if (final_candidate == 0xFF) {
308 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
309 MASKDWORD) >> 22) & 0x3FF;
310 x = result[final_candidate][0];
311 if ((x & 0x00000200) != 0)
313 tx0_a = (x * oldval_0) >> 8;
314 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
315 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
316 ((x * oldval_0 >> 7) & 0x1));
317 y = result[final_candidate][1];
318 if ((y & 0x00000200) != 0)
320 tx0_c = (y * oldval_0) >> 8;
321 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
322 ((tx0_c & 0x3C0) >> 6));
323 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
325 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
326 ((y * oldval_0 >> 7) & 0x1));
329 reg = result[final_candidate][2];
330 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
331 reg = result[final_candidate][3] & 0x3F;
332 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
333 reg = (result[final_candidate][3] >> 6) & 0xF;
334 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
337 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_fill_iqk_matrix);
339 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg,
340 u32 *addabackup, u32 registernum)
344 for (i = 0; i < registernum; i++)
345 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
347 EXPORT_SYMBOL_GPL(rtl8723_save_adda_registers);
349 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw,
350 u32 *macreg, u32 *macbackup)
352 struct rtl_priv *rtlpriv = rtl_priv(hw);
355 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
356 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
357 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
359 EXPORT_SYMBOL_GPL(rtl8723_phy_save_mac_registers);
361 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw,
362 u32 *addareg, u32 *addabackup,
367 for (i = 0; i < regiesternum; i++)
368 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
370 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_adda_registers);
372 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw,
373 u32 *macreg, u32 *macbackup)
375 struct rtl_priv *rtlpriv = rtl_priv(hw);
378 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
379 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
380 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
382 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers);
384 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
385 bool is_patha_on, bool is2t)
390 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
393 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
395 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
398 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
399 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
401 EXPORT_SYMBOL_GPL(rtl8723_phy_path_adda_on);
403 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw,
404 u32 *macreg, u32 *macbackup)
406 struct rtl_priv *rtlpriv = rtl_priv(hw);
409 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
411 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
412 rtl_write_byte(rtlpriv, macreg[i],
413 (u8) (macbackup[i] & (~BIT(3))));
414 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
416 EXPORT_SYMBOL_GPL(rtl8723_phy_mac_setting_calibration);
418 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw)
420 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
421 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
422 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
424 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_standby);
426 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
430 mode = pi_mode ? 0x01000100 : 0x01000000;
431 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
432 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
434 EXPORT_SYMBOL_GPL(rtl8723_phy_pi_mode_switch);