drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25 #include <linux/firmware.h>
  26
  27 #include "../wlcore/wlcore.h"
  28 #include "../wlcore/debug.h"
  29 #include "../wlcore/io.h"
  30 #include "../wlcore/acx.h"
  31 #include "../wlcore/tx.h"
  32 #include "../wlcore/rx.h"
  33 #include "../wlcore/boot.h"
  34
  35 #include "reg.h"
  36 #include "conf.h"
  37 #include "cmd.h"
  38 #include "acx.h"
  39 #include "tx.h"
  40 #include "wl18xx.h"
  41 #include "io.h"
  42 #include "scan.h"
  43 #include "event.h"
  44 #include "debugfs.h"
  45
  46 #define WL18XX_RX_CHECKSUM_MASK      0x40
  47
  48 static char *ht_mode_param = NULL;
  49 static char *board_type_param = NULL;
  50 static bool checksum_param = false;
  51 static int num_rx_desc_param = -1;
  52
  53 /* phy paramters */
  54 static int dc2dc_param = -1;
  55 static int n_antennas_2_param = -1;
  56 static int n_antennas_5_param = -1;
  57 static int low_band_component_param = -1;
  58 static int low_band_component_type_param = -1;
  59 static int high_band_component_param = -1;
  60 static int high_band_component_type_param = -1;
  61 static int pwr_limit_reference_11_abg_param = -1;
  62
  63 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  64         /* MCS rates are used only with 11n */
  65         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  66         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  67         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  68         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  69         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  70         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  71         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  72         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  73         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  74         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  75         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  76         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  77         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  78         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  79         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  80         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  81
  82         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  83         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  84         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  85         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  86
  87         /* TI-specific rate */
  88         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  89
  90         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  91         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  92         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  93         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  94         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  95         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  96         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  97         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  98 };
  99
 100 static const u8 wl18xx_rate_to_idx_5ghz[] = {
 101         /* MCS rates are used only with 11n */
 102         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
 103         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
 104         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
 105         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
 106         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
 107         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
 108         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
 109         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
 110         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
 111         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
 112         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
 113         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
 114         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
 115         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
 116         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
 117         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
 118
 119         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 120         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 121         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 122         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 123
 124         /* TI-specific rate */
 125         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 126
 127         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 128         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 129         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 130         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 131         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 132         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 133         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 134         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 135 };
 136
 137 static const u8 *wl18xx_band_rate_to_idx[] = {
 138         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 139         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 140 };
 141
 142 enum wl18xx_hw_rates {
 143         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 144         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 145         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 146         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 147         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 148         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 149         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 150         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 151         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 152         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 153         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 154         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 155         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 156         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 157         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 158         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 159         WL18XX_CONF_HW_RXTX_RATE_54,
 160         WL18XX_CONF_HW_RXTX_RATE_48,
 161         WL18XX_CONF_HW_RXTX_RATE_36,
 162         WL18XX_CONF_HW_RXTX_RATE_24,
 163         WL18XX_CONF_HW_RXTX_RATE_22,
 164         WL18XX_CONF_HW_RXTX_RATE_18,
 165         WL18XX_CONF_HW_RXTX_RATE_12,
 166         WL18XX_CONF_HW_RXTX_RATE_11,
 167         WL18XX_CONF_HW_RXTX_RATE_9,
 168         WL18XX_CONF_HW_RXTX_RATE_6,
 169         WL18XX_CONF_HW_RXTX_RATE_5_5,
 170         WL18XX_CONF_HW_RXTX_RATE_2,
 171         WL18XX_CONF_HW_RXTX_RATE_1,
 172         WL18XX_CONF_HW_RXTX_RATE_MAX,
 173 };
 174
 175 static struct wlcore_conf wl18xx_conf = {
 176         .sg = {
 177                 .params = {
 178                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 179                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 180                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 181                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 182                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 183                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 184                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 185                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 186                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 187                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 188                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 189                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 190                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 191                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 192                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 193                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 194                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 195                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 196                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 197                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 198                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 199                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 200                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 201                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 202                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 203                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 204                         /* active scan params */
 205                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 206                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 207                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 208                         /* passive scan params */
 209                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 210                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 211                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 212                         /* passive scan in dual antenna params */
 213                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 214                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 215                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 216                         /* general params */
 217                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 218                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 219                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 220                         [CONF_SG_DHCP_TIME] = 5000,
 221                         [CONF_SG_RXT] = 1200,
 222                         [CONF_SG_TXT] = 1000,
 223                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 224                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 225                         [CONF_SG_HV3_MAX_SERVED] = 6,
 226                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 227                         [CONF_SG_UPSD_TIMEOUT] = 10,
 228                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 229                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 230                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 231                         /* AP params */
 232                         [CONF_AP_BEACON_MISS_TX] = 3,
 233                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 234                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 235                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 236                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 237                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 238                         /* CTS Diluting params */
 239                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 240                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 241                 },
 242                 .state = CONF_SG_PROTECTIVE,
 243         },
 244         .rx = {
 245                 .rx_msdu_life_time           = 512000,
 246                 .packet_detection_threshold  = 0,
 247                 .ps_poll_timeout             = 15,
 248                 .upsd_timeout                = 15,
 249                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 250                 .rx_cca_threshold            = 0,
 251                 .irq_blk_threshold           = 0xFFFF,
 252                 .irq_pkt_threshold           = 0,
 253                 .irq_timeout                 = 600,
 254                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 255         },
 256         .tx = {
 257                 .tx_energy_detection         = 0,
 258                 .sta_rc_conf                 = {
 259                         .enabled_rates       = 0,
 260                         .short_retry_limit   = 10,
 261                         .long_retry_limit    = 10,
 262                         .aflags              = 0,
 263                 },
 264                 .ac_conf_count               = 4,
 265                 .ac_conf                     = {
 266                         [CONF_TX_AC_BE] = {
 267                                 .ac          = CONF_TX_AC_BE,
 268                                 .cw_min      = 15,
 269                                 .cw_max      = 63,
 270                                 .aifsn       = 3,
 271                                 .tx_op_limit = 0,
 272                         },
 273                         [CONF_TX_AC_BK] = {
 274                                 .ac          = CONF_TX_AC_BK,
 275                                 .cw_min      = 15,
 276                                 .cw_max      = 63,
 277                                 .aifsn       = 7,
 278                                 .tx_op_limit = 0,
 279                         },
 280                         [CONF_TX_AC_VI] = {
 281                                 .ac          = CONF_TX_AC_VI,
 282                                 .cw_min      = 15,
 283                                 .cw_max      = 63,
 284                                 .aifsn       = CONF_TX_AIFS_PIFS,
 285                                 .tx_op_limit = 3008,
 286                         },
 287                         [CONF_TX_AC_VO] = {
 288                                 .ac          = CONF_TX_AC_VO,
 289                                 .cw_min      = 15,
 290                                 .cw_max      = 63,
 291                                 .aifsn       = CONF_TX_AIFS_PIFS,
 292                                 .tx_op_limit = 1504,
 293                         },
 294                 },
 295                 .max_tx_retries = 100,
 296                 .ap_aging_period = 300,
 297                 .tid_conf_count = 4,
 298                 .tid_conf = {
 299                         [CONF_TX_AC_BE] = {
 300                                 .queue_id    = CONF_TX_AC_BE,
 301                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 302                                 .tsid        = CONF_TX_AC_BE,
 303                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 304                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 305                                 .apsd_conf   = {0, 0},
 306                         },
 307                         [CONF_TX_AC_BK] = {
 308                                 .queue_id    = CONF_TX_AC_BK,
 309                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 310                                 .tsid        = CONF_TX_AC_BK,
 311                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 312                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 313                                 .apsd_conf   = {0, 0},
 314                         },
 315                         [CONF_TX_AC_VI] = {
 316                                 .queue_id    = CONF_TX_AC_VI,
 317                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 318                                 .tsid        = CONF_TX_AC_VI,
 319                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 320                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 321                                 .apsd_conf   = {0, 0},
 322                         },
 323                         [CONF_TX_AC_VO] = {
 324                                 .queue_id    = CONF_TX_AC_VO,
 325                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 326                                 .tsid        = CONF_TX_AC_VO,
 327                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 328                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 329                                 .apsd_conf   = {0, 0},
 330                         },
 331                 },
 332                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 333                 .tx_compl_timeout            = 350,
 334                 .tx_compl_threshold          = 10,
 335                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 336                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 337                 .tmpl_short_retry_limit      = 10,
 338                 .tmpl_long_retry_limit       = 10,
 339                 .tx_watchdog_timeout         = 5000,
 340                 .slow_link_thold             = 3,
 341                 .fast_link_thold             = 30,
 342         },
 343         .conn = {
 344                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 345                 .listen_interval             = 1,
 346                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 347                 .suspend_listen_interval     = 3,
 348                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 349                 .bcn_filt_ie_count           = 3,
 350                 .bcn_filt_ie = {
 351                         [0] = {
 352                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 353                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 354                         },
 355                         [1] = {
 356                                 .ie          = WLAN_EID_HT_OPERATION,
 357                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 358                         },
 359                         [2] = {
 360                                 .ie          = WLAN_EID_ERP_INFO,
 361                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 362                         },
 363                 },
 364                 .synch_fail_thold            = 12,
 365                 .bss_lose_timeout            = 400,
 366                 .beacon_rx_timeout           = 10000,
 367                 .broadcast_timeout           = 20000,
 368                 .rx_broadcast_in_ps          = 1,
 369                 .ps_poll_threshold           = 10,
 370                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 371                 .bet_max_consecutive         = 50,
 372                 .psm_entry_retries           = 8,
 373                 .psm_exit_retries            = 16,
 374                 .psm_entry_nullfunc_retries  = 3,
 375                 .dynamic_ps_timeout          = 1500,
 376                 .forced_ps                   = false,
 377                 .keep_alive_interval         = 55000,
 378                 .max_listen_interval         = 20,
 379                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 380         },
 381         .itrim = {
 382                 .enable = false,
 383                 .timeout = 50000,
 384         },
 385         .pm_config = {
 386                 .host_clk_settling_time = 5000,
 387                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 388         },
 389         .roam_trigger = {
 390                 .trigger_pacing               = 1,
 391                 .avg_weight_rssi_beacon       = 20,
 392                 .avg_weight_rssi_data         = 10,
 393                 .avg_weight_snr_beacon        = 20,
 394                 .avg_weight_snr_data          = 10,
 395         },
 396         .scan = {
 397                 .min_dwell_time_active        = 7500,
 398                 .max_dwell_time_active        = 30000,
 399                 .dwell_time_passive           = 100000,
 400                 .dwell_time_dfs               = 150000,
 401                 .num_probe_reqs               = 2,
 402                 .split_scan_timeout           = 50000,
 403         },
 404         .sched_scan = {
 405                 /*
 406                  * Values are in TU/1000 but since sched scan FW command
 407                  * params are in TUs rounding up may occur.
 408                  */
 409                 .base_dwell_time                = 7500,
 410                 .max_dwell_time_delta           = 22500,
 411                 /* based on 250bits per probe @1Mbps */
 412                 .dwell_time_delta_per_probe     = 2000,
 413                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 414                 .dwell_time_delta_per_probe_5   = 350,
 415                 .dwell_time_passive             = 100000,
 416                 .dwell_time_dfs                 = 150000,
 417                 .num_probe_reqs                 = 2,
 418                 .rssi_threshold                 = -90,
 419                 .snr_threshold                  = 0,
 420         },
 421         .ht = {
 422                 .rx_ba_win_size = 32,
 423                 .tx_ba_win_size = 64,
 424                 .inactivity_timeout = 10000,
 425                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 426         },
 427         .mem = {
 428                 .num_stations                 = 1,
 429                 .ssid_profiles                = 1,
 430                 .rx_block_num                 = 40,
 431                 .tx_min_block_num             = 40,
 432                 .dynamic_memory               = 1,
 433                 .min_req_tx_blocks            = 45,
 434                 .min_req_rx_blocks            = 22,
 435                 .tx_min                       = 27,
 436         },
 437         .fm_coex = {
 438                 .enable                       = true,
 439                 .swallow_period               = 5,
 440                 .n_divider_fref_set_1         = 0xff,       /* default */
 441                 .n_divider_fref_set_2         = 12,
 442                 .m_divider_fref_set_1         = 0xffff,
 443                 .m_divider_fref_set_2         = 148,        /* default */
 444                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 445                 .ldo_stabilization_time       = 0xffff,     /* default */
 446                 .fm_disturbed_band_margin     = 0xff,       /* default */
 447                 .swallow_clk_diff             = 0xff,       /* default */
 448         },
 449         .rx_streaming = {
 450                 .duration                      = 150,
 451                 .queues                        = 0x1,
 452                 .interval                      = 20,
 453                 .always                        = 0,
 454         },
 455         .fwlog = {
 456                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 457                 .mem_blocks                   = 2,
 458                 .severity                     = 0,
 459                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 460                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 461                 .threshold                    = 0,
 462         },
 463         .rate = {
 464                 .rate_retry_score = 32000,
 465                 .per_add = 8192,
 466                 .per_th1 = 2048,
 467                 .per_th2 = 4096,
 468                 .max_per = 8100,
 469                 .inverse_curiosity_factor = 5,
 470                 .tx_fail_low_th = 4,
 471                 .tx_fail_high_th = 10,
 472                 .per_alpha_shift = 4,
 473                 .per_add_shift = 13,
 474                 .per_beta1_shift = 10,
 475                 .per_beta2_shift = 8,
 476                 .rate_check_up = 2,
 477                 .rate_check_down = 12,
 478                 .rate_retry_policy = {
 479                         0x00, 0x00, 0x00, 0x00, 0x00,
 480                         0x00, 0x00, 0x00, 0x00, 0x00,
 481                         0x00, 0x00, 0x00,
 482                 },
 483         },
 484         .hangover = {
 485                 .recover_time               = 0,
 486                 .hangover_period            = 20,
 487                 .dynamic_mode               = 1,
 488                 .early_termination_mode     = 1,
 489                 .max_period                 = 20,
 490                 .min_period                 = 1,
 491                 .increase_delta             = 1,
 492                 .decrease_delta             = 2,
 493                 .quiet_time                 = 4,
 494                 .increase_time              = 1,
 495                 .window_size                = 16,
 496         },
 497         .recovery = {
 498                 .bug_on_recovery            = 0,
 499                 .no_recovery                = 0,
 500         },
 501 };
 502
 503 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 504         .ht = {
 505                 .mode                           = HT_MODE_DEFAULT,
 506         },
 507         .phy = {
 508                 .phy_standalone                 = 0x00,
 509                 .primary_clock_setting_time     = 0x05,
 510                 .clock_valid_on_wake_up         = 0x00,
 511                 .secondary_clock_setting_time   = 0x05,
 512                 .board_type                     = BOARD_TYPE_HDK_18XX,
 513                 .auto_detect                    = 0x00,
 514                 .dedicated_fem                  = FEM_NONE,
 515                 .low_band_component             = COMPONENT_3_WAY_SWITCH,
 516                 .low_band_component_type        = 0x04,
 517                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 518                 .high_band_component_type       = 0x09,
 519                 .tcxo_ldo_voltage               = 0x00,
 520                 .xtal_itrim_val                 = 0x04,
 521                 .srf_state                      = 0x00,
 522                 .io_configuration               = 0x01,
 523                 .sdio_configuration             = 0x00,
 524                 .settings                       = 0x00,
 525                 .enable_clpc                    = 0x00,
 526                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 527                 .rx_profile                     = 0x00,
 528                 .pwr_limit_reference_11_abg     = 0x64,
 529                 .per_chan_pwr_limit_arr_11abg   = {
 530                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 531                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 532                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 533                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 534                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 535                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 536                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 537                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 538                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 539                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 540                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 541                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 542                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 543                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 544                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 545                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 546                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
 547                 .pwr_limit_reference_11p        = 0x64,
 548                 .per_chan_pwr_limit_arr_11p     = { 0xff, 0xff, 0xff, 0xff,
 549                                                     0xff, 0xff, 0xff },
 550                 .psat                           = 0,
 551                 .low_power_val                  = 0x08,
 552                 .med_power_val                  = 0x12,
 553                 .high_power_val                 = 0x18,
 554                 .low_power_val_2nd              = 0x05,
 555                 .med_power_val_2nd              = 0x0a,
 556                 .high_power_val_2nd             = 0x14,
 557                 .external_pa_dc2dc              = 0,
 558                 .number_of_assembled_ant2_4     = 2,
 559                 .number_of_assembled_ant5       = 1,
 560                 .tx_rf_margin                   = 1,
 561         },
 562 };
 563
 564 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 565         [PART_TOP_PRCM_ELP_SOC] = {
 566                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 567                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 568                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 569                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 570         },
 571         [PART_DOWN] = {
 572                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 573                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 574                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 575                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 576         },
 577         [PART_BOOT] = {
 578                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 579                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 580                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 581                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 582         },
 583         [PART_WORK] = {
 584                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 585                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 586                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 587                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 588         },
 589         [PART_PHY_INIT] = {
 590                 .mem  = { .start = 0x80926000,
 591                           .size = sizeof(struct wl18xx_mac_and_phy_params) },
 592                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 593                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 594                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 595         },
 596 };
 597
 598 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 599         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 600         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 601         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 602         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 603         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 604         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 605         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 606         [REG_PC_ON_RECOVERY]            = WL18XX_SCR_PAD4,
 607         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 608         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 609
 610         /* data access memory addresses, used with partition translation */
 611         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 612         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 613
 614         /* raw data access memory addresses */
 615         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 616 };
 617
 618 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
 619         [CLOCK_CONFIG_16_2_M]   = { 7,  104,  801, 4,  true },
 620         [CLOCK_CONFIG_16_368_M] = { 9,  132, 3751, 4,  true },
 621         [CLOCK_CONFIG_16_8_M]   = { 7,  100,    0, 0, false },
 622         [CLOCK_CONFIG_19_2_M]   = { 8,  100,    0, 0, false },
 623         [CLOCK_CONFIG_26_M]     = { 13, 120,    0, 0, false },
 624         [CLOCK_CONFIG_32_736_M] = { 9,  132, 3751, 4,  true },
 625         [CLOCK_CONFIG_33_6_M]   = { 7,  100,    0, 0, false },
 626         [CLOCK_CONFIG_38_468_M] = { 8,  100,    0, 0, false },
 627         [CLOCK_CONFIG_52_M]     = { 13, 120,    0, 0, false },
 628 };
 629
 630 /* TODO: maybe move to a new header file? */
 631 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-2.bin"
 632
 633 static int wl18xx_identify_chip(struct wl1271 *wl)
 634 {
 635         int ret = 0;
 636
 637         switch (wl->chip.id) {
 638         case CHIP_ID_185x_PG20:
 639                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
 640                                  wl->chip.id);
 641                 wl->sr_fw_name = WL18XX_FW_NAME;
 642                 /* wl18xx uses the same firmware for PLT */
 643                 wl->plt_fw_name = WL18XX_FW_NAME;
 644                 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
 645                               WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 646                               WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
 647                               WLCORE_QUIRK_TX_PAD_LAST_FRAME |
 648                               WLCORE_QUIRK_REGDOMAIN_CONF |
 649                               WLCORE_QUIRK_DUAL_PROBE_TMPL;
 650
 651                 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
 652                                       WL18XX_IFTYPE_VER,  WL18XX_MAJOR_VER,
 653                                       WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
 654                                       /* there's no separate multi-role FW */
 655                                       0, 0, 0, 0);
 656                 break;
 657         case CHIP_ID_185x_PG10:
 658                 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
 659                                wl->chip.id);
 660                 ret = -ENODEV;
 661                 goto out;
 662
 663         default:
 664                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 665                 ret = -ENODEV;
 666                 goto out;
 667         }
 668
 669         wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 670         wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 671         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
 672         wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
 673         wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
 674 out:
 675         return ret;
 676 }
 677
 678 static int wl18xx_set_clk(struct wl1271 *wl)
 679 {
 680         u16 clk_freq;
 681         int ret;
 682
 683         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 684         if (ret < 0)
 685                 goto out;
 686
 687         /* TODO: PG2: apparently we need to read the clk type */
 688
 689         ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
 690         if (ret < 0)
 691                 goto out;
 692
 693         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
 694                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
 695                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
 696                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 697
 698         ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
 699                                    wl18xx_clk_table[clk_freq].n);
 700         if (ret < 0)
 701                 goto out;
 702
 703         ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
 704                                    wl18xx_clk_table[clk_freq].m);
 705         if (ret < 0)
 706                 goto out;
 707
 708         if (wl18xx_clk_table[clk_freq].swallow) {
 709                 /* first the 16 lower bits */
 710                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
 711                                            wl18xx_clk_table[clk_freq].q &
 712                                            PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
 713                 if (ret < 0)
 714                         goto out;
 715
 716                 /* then the 16 higher bits, masked out */
 717                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
 718                                         (wl18xx_clk_table[clk_freq].q >> 16) &
 719                                         PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
 720                 if (ret < 0)
 721                         goto out;
 722
 723                 /* first the 16 lower bits */
 724                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
 725                                            wl18xx_clk_table[clk_freq].p &
 726                                            PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
 727                 if (ret < 0)
 728                         goto out;
 729
 730                 /* then the 16 higher bits, masked out */
 731                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
 732                                         (wl18xx_clk_table[clk_freq].p >> 16) &
 733                                         PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
 734         } else {
 735                 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
 736                                            PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
 737         }
 738
 739 out:
 740         return ret;
 741 }
 742
 743 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
 744 {
 745         int ret;
 746
 747         /* disable Rx/Tx */
 748         ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
 749         if (ret < 0)
 750                 goto out;
 751
 752         /* disable auto calibration on start*/
 753         ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
 754
 755 out:
 756         return ret;
 757 }
 758
 759 static int wl18xx_pre_boot(struct wl1271 *wl)
 760 {
 761         int ret;
 762
 763         ret = wl18xx_set_clk(wl);
 764         if (ret < 0)
 765                 goto out;
 766
 767         /* Continue the ELP wake up sequence */
 768         ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 769         if (ret < 0)
 770                 goto out;
 771
 772         udelay(500);
 773
 774         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 775         if (ret < 0)
 776                 goto out;
 777
 778         /* Disable interrupts */
 779         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 780         if (ret < 0)
 781                 goto out;
 782
 783         ret = wl18xx_boot_soft_reset(wl);
 784
 785 out:
 786         return ret;
 787 }
 788
 789 static int wl18xx_pre_upload(struct wl1271 *wl)
 790 {
 791         u32 tmp;
 792         int ret;
 793
 794         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 795         if (ret < 0)
 796                 goto out;
 797
 798         /* TODO: check if this is all needed */
 799         ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 800         if (ret < 0)
 801                 goto out;
 802
 803         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
 804         if (ret < 0)
 805                 goto out;
 806
 807         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 808
 809         ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
 810
 811 out:
 812         return ret;
 813 }
 814
 815 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
 816 {
 817         struct wl18xx_priv *priv = wl->priv;
 818         struct wl18xx_mac_and_phy_params *params;
 819         int ret;
 820
 821         params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
 822         if (!params) {
 823                 ret = -ENOMEM;
 824                 goto out;
 825         }
 826
 827         ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 828         if (ret < 0)
 829                 goto out;
 830
 831         ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
 832                            sizeof(*params), false);
 833
 834 out:
 835         kfree(params);
 836         return ret;
 837 }
 838
 839 static int wl18xx_enable_interrupts(struct wl1271 *wl)
 840 {
 841         u32 event_mask, intr_mask;
 842         int ret;
 843
 844         event_mask = WL18XX_ACX_EVENTS_VECTOR;
 845         intr_mask = WL18XX_INTR_MASK;
 846
 847         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
 848         if (ret < 0)
 849                 goto out;
 850
 851         wlcore_enable_interrupts(wl);
 852
 853         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 854                                WL1271_ACX_INTR_ALL & ~intr_mask);
 855         if (ret < 0)
 856                 goto disable_interrupts;
 857
 858         return ret;
 859
 860 disable_interrupts:
 861         wlcore_disable_interrupts(wl);
 862
 863 out:
 864         return ret;
 865 }
 866
 867 static int wl18xx_boot(struct wl1271 *wl)
 868 {
 869         int ret;
 870
 871         ret = wl18xx_pre_boot(wl);
 872         if (ret < 0)
 873                 goto out;
 874
 875         ret = wl18xx_pre_upload(wl);
 876         if (ret < 0)
 877                 goto out;
 878
 879         ret = wlcore_boot_upload_firmware(wl);
 880         if (ret < 0)
 881                 goto out;
 882
 883         ret = wl18xx_set_mac_and_phy(wl);
 884         if (ret < 0)
 885                 goto out;
 886
 887         wl->event_mask = BSS_LOSS_EVENT_ID |
 888                 SCAN_COMPLETE_EVENT_ID |
 889                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 890                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
 891                 DUMMY_PACKET_EVENT_ID |
 892                 PEER_REMOVE_COMPLETE_EVENT_ID |
 893                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
 894                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
 895                 INACTIVE_STA_EVENT_ID |
 896                 MAX_TX_FAILURE_EVENT_ID |
 897                 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
 898                 DFS_CHANNELS_CONFIG_COMPLETE_EVENT;
 899
 900         ret = wlcore_boot_run_firmware(wl);
 901         if (ret < 0)
 902                 goto out;
 903
 904         ret = wl18xx_enable_interrupts(wl);
 905
 906 out:
 907         return ret;
 908 }
 909
 910 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
 911                                void *buf, size_t len)
 912 {
 913         struct wl18xx_priv *priv = wl->priv;
 914
 915         memcpy(priv->cmd_buf, buf, len);
 916         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
 917
 918         return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
 919                             WL18XX_CMD_MAX_SIZE, false);
 920 }
 921
 922 static int wl18xx_ack_event(struct wl1271 *wl)
 923 {
 924         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
 925                                 WL18XX_INTR_TRIG_EVENT_ACK);
 926 }
 927
 928 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
 929 {
 930         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
 931         return (len + blk_size - 1) / blk_size + spare_blks;
 932 }
 933
 934 static void
 935 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 936                           u32 blks, u32 spare_blks)
 937 {
 938         desc->wl18xx_mem.total_mem_blocks = blks;
 939 }
 940
 941 static void
 942 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 943                             struct sk_buff *skb)
 944 {
 945         desc->length = cpu_to_le16(skb->len);
 946
 947         /* if only the last frame is to be padded, we unset this bit on Tx */
 948         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
 949                 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
 950         else
 951                 desc->wl18xx_mem.ctrl = 0;
 952
 953         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
 954                      "len: %d life: %d mem: %d", desc->hlid,
 955                      le16_to_cpu(desc->length),
 956                      le16_to_cpu(desc->life_time),
 957                      desc->wl18xx_mem.total_mem_blocks);
 958 }
 959
 960 static enum wl_rx_buf_align
 961 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
 962 {
 963         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
 964                 return WLCORE_RX_BUF_PADDED;
 965
 966         return WLCORE_RX_BUF_ALIGNED;
 967 }
 968
 969 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
 970                                     u32 data_len)
 971 {
 972         struct wl1271_rx_descriptor *desc = rx_data;
 973
 974         /* invalid packet */
 975         if (data_len < sizeof(*desc))
 976                 return 0;
 977
 978         return data_len - sizeof(*desc);
 979 }
 980
 981 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
 982 {
 983         wl18xx_tx_immediate_complete(wl);
 984 }
 985
 986 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
 987 {
 988         int ret;
 989         u32 sdio_align_size = 0;
 990         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
 991                               HOST_IF_CFG_ADD_RX_ALIGNMENT;
 992
 993         /* Enable Tx SDIO padding */
 994         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
 995                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
 996                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 997         }
 998
 999         /* Enable Rx SDIO padding */
1000         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1001                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1002                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1003         }
1004
1005         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1006                                             sdio_align_size, extra_mem_blk,
1007                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
1008         if (ret < 0)
1009                 return ret;
1010
1011         return 0;
1012 }
1013
1014 static int wl18xx_hw_init(struct wl1271 *wl)
1015 {
1016         int ret;
1017         struct wl18xx_priv *priv = wl->priv;
1018
1019         /* (re)init private structures. Relevant on recovery as well. */
1020         priv->last_fw_rls_idx = 0;
1021         priv->extra_spare_vif_count = 0;
1022
1023         /* set the default amount of spare blocks in the bitmap */
1024         ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1025         if (ret < 0)
1026                 return ret;
1027
1028         if (checksum_param) {
1029                 ret = wl18xx_acx_set_checksum_state(wl);
1030                 if (ret != 0)
1031                         return ret;
1032         }
1033
1034         return ret;
1035 }
1036
1037 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1038                                     struct wl1271_tx_hw_descr *desc,
1039                                     struct sk_buff *skb)
1040 {
1041         u32 ip_hdr_offset;
1042         struct iphdr *ip_hdr;
1043
1044         if (!checksum_param) {
1045                 desc->wl18xx_checksum_data = 0;
1046                 return;
1047         }
1048
1049         if (skb->ip_summed != CHECKSUM_PARTIAL) {
1050                 desc->wl18xx_checksum_data = 0;
1051                 return;
1052         }
1053
1054         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1055         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1056                 desc->wl18xx_checksum_data = 0;
1057                 return;
1058         }
1059
1060         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1061
1062         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
1063         ip_hdr = (void *)skb_network_header(skb);
1064         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1065 }
1066
1067 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1068                                struct wl1271_rx_descriptor *desc,
1069                                struct sk_buff *skb)
1070 {
1071         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1072                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1073 }
1074
1075 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1076 {
1077         struct wl18xx_priv *priv = wl->priv;
1078
1079         return priv->conf.phy.number_of_assembled_ant2_4 >= 2;
1080 }
1081
1082 /*
1083  * TODO: instead of having these two functions to get the rate mask,
1084  * we should modify the wlvif->rate_set instead
1085  */
1086 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1087                                        struct wl12xx_vif *wlvif)
1088 {
1089         u32 hw_rate_set = wlvif->rate_set;
1090
1091         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1092             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1093                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1094                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1095
1096                 /* we don't support MIMO in wide-channel mode */
1097                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1098         } else if (wl18xx_is_mimo_supported(wl)) {
1099                 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1100                 hw_rate_set |= CONF_TX_MIMO_RATES;
1101         }
1102
1103         return hw_rate_set;
1104 }
1105
1106 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1107                                              struct wl12xx_vif *wlvif)
1108 {
1109         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1110             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1111                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1112
1113                 /* sanity check - we don't support this */
1114                 if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ))
1115                         return 0;
1116
1117                 return CONF_TX_RATE_USE_WIDE_CHAN;
1118         } else if (wl18xx_is_mimo_supported(wl) &&
1119                    wlvif->band == IEEE80211_BAND_2GHZ) {
1120                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1121                 /*
1122                  * we don't care about HT channel here - if a peer doesn't
1123                  * support MIMO, we won't enable it in its rates
1124                  */
1125                 return CONF_TX_MIMO_RATES;
1126         } else {
1127                 return 0;
1128         }
1129 }
1130
1131 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1132 {
1133         u32 fuse;
1134         int ret;
1135
1136         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1137         if (ret < 0)
1138                 goto out;
1139
1140         ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1141         if (ret < 0)
1142                 goto out;
1143
1144         if (ver)
1145                 *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1146
1147         ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1148
1149 out:
1150         return ret;
1151 }
1152
1153 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1154 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1155 {
1156         struct wl18xx_priv *priv = wl->priv;
1157         struct wlcore_conf_file *conf_file;
1158         const struct firmware *fw;
1159         int ret;
1160
1161         ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1162         if (ret < 0) {
1163                 wl1271_error("could not get configuration binary %s: %d",
1164                              WL18XX_CONF_FILE_NAME, ret);
1165                 goto out_fallback;
1166         }
1167
1168         if (fw->size != WL18XX_CONF_SIZE) {
1169                 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1170                              WL18XX_CONF_SIZE, fw->size);
1171                 ret = -EINVAL;
1172                 goto out;
1173         }
1174
1175         conf_file = (struct wlcore_conf_file *) fw->data;
1176
1177         if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1178                 wl1271_error("configuration binary file magic number mismatch, "
1179                              "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1180                              conf_file->header.magic);
1181                 ret = -EINVAL;
1182                 goto out;
1183         }
1184
1185         if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1186                 wl1271_error("configuration binary file version not supported, "
1187                              "expected 0x%08x got 0x%08x",
1188                              WL18XX_CONF_VERSION, conf_file->header.version);
1189                 ret = -EINVAL;
1190                 goto out;
1191         }
1192
1193         memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1194         memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1195
1196         goto out;
1197
1198 out_fallback:
1199         wl1271_warning("falling back to default config");
1200
1201         /* apply driver default configuration */
1202         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1203         /* apply default private configuration */
1204         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1205
1206         /* For now we just fallback */
1207         return 0;
1208
1209 out:
1210         release_firmware(fw);
1211         return ret;
1212 }
1213
1214 static int wl18xx_plt_init(struct wl1271 *wl)
1215 {
1216         int ret;
1217
1218         /* calibrator based auto/fem detect not supported for 18xx */
1219         if (wl->plt_mode == PLT_FEM_DETECT) {
1220                 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1221                 return -EINVAL;
1222         }
1223
1224         ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1225         if (ret < 0)
1226                 return ret;
1227
1228         return wl->ops->boot(wl);
1229 }
1230
1231 static int wl18xx_get_mac(struct wl1271 *wl)
1232 {
1233         u32 mac1, mac2;
1234         int ret;
1235
1236         ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1237         if (ret < 0)
1238                 goto out;
1239
1240         ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1241         if (ret < 0)
1242                 goto out;
1243
1244         ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1245         if (ret < 0)
1246                 goto out;
1247
1248         /* these are the two parts of the BD_ADDR */
1249         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1250                 ((mac1 & 0xff000000) >> 24);
1251         wl->fuse_nic_addr = (mac1 & 0xffffff);
1252
1253         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1254
1255 out:
1256         return ret;
1257 }
1258
1259 static int wl18xx_handle_static_data(struct wl1271 *wl,
1260                                      struct wl1271_static_data *static_data)
1261 {
1262         struct wl18xx_static_data_priv *static_data_priv =
1263                 (struct wl18xx_static_data_priv *) static_data->priv;
1264
1265         strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1266                 sizeof(wl->chip.phy_fw_ver_str));
1267
1268         /* make sure the string is NULL-terminated */
1269         wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1270
1271         wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1272
1273         return 0;
1274 }
1275
1276 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1277 {
1278         struct wl18xx_priv *priv = wl->priv;
1279
1280         /* If we have VIFs requiring extra spare, indulge them */
1281         if (priv->extra_spare_vif_count)
1282                 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1283
1284         return WL18XX_TX_HW_BLOCK_SPARE;
1285 }
1286
1287 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1288                           struct ieee80211_vif *vif,
1289                           struct ieee80211_sta *sta,
1290                           struct ieee80211_key_conf *key_conf)
1291 {
1292         struct wl18xx_priv *priv = wl->priv;
1293         bool change_spare = false;
1294         int ret;
1295
1296         /*
1297          * when adding the first or removing the last GEM/TKIP interface,
1298          * we have to adjust the number of spare blocks.
1299          */
1300         change_spare = (key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1301                 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP) &&
1302                 ((priv->extra_spare_vif_count == 0 && cmd == SET_KEY) ||
1303                  (priv->extra_spare_vif_count == 1 && cmd == DISABLE_KEY));
1304
1305         /* no need to change spare - just regular set_key */
1306         if (!change_spare)
1307                 return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1308
1309         ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1310         if (ret < 0)
1311                 goto out;
1312
1313         /* key is now set, change the spare blocks */
1314         if (cmd == SET_KEY) {
1315                 ret = wl18xx_set_host_cfg_bitmap(wl,
1316                                         WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1317                 if (ret < 0)
1318                         goto out;
1319
1320                 priv->extra_spare_vif_count++;
1321         } else {
1322                 ret = wl18xx_set_host_cfg_bitmap(wl,
1323                                         WL18XX_TX_HW_BLOCK_SPARE);
1324                 if (ret < 0)
1325                         goto out;
1326
1327                 priv->extra_spare_vif_count--;
1328         }
1329
1330 out:
1331         return ret;
1332 }
1333
1334 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1335                                u32 buf_offset, u32 last_len)
1336 {
1337         if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1338                 struct wl1271_tx_hw_descr *last_desc;
1339
1340                 /* get the last TX HW descriptor written to the aggr buf */
1341                 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1342                                                         buf_offset - last_len);
1343
1344                 /* the last frame is padded up to an SDIO block */
1345                 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1346                 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1347         }
1348
1349         /* no modifications */
1350         return buf_offset;
1351 }
1352
1353 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1354                                  struct wl12xx_vif *wlvif,
1355                                  struct ieee80211_sta *sta,
1356                                  u32 changed)
1357 {
1358         bool wide = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1359
1360         wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1361
1362         if (!(changed & IEEE80211_RC_BW_CHANGED))
1363                 return;
1364
1365         mutex_lock(&wl->mutex);
1366
1367         /* sanity */
1368         if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
1369                 goto out;
1370
1371         /* ignore the change before association */
1372         if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
1373                 goto out;
1374
1375         /*
1376          * If we started out as wide, we can change the operation mode. If we
1377          * thought this was a 20mhz AP, we have to reconnect
1378          */
1379         if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1380             wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1381                 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1382         else
1383                 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
1384
1385 out:
1386         mutex_unlock(&wl->mutex);
1387 }
1388
1389 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1390                                struct ieee80211_sta_ht_cap *ht_cap,
1391                                bool allow_ht_operation,
1392                                u32 rate_set, u8 hlid)
1393 {
1394         return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1395                                        rate_set, hlid);
1396 }
1397
1398 static int wl18xx_setup(struct wl1271 *wl);
1399
1400 static struct wlcore_ops wl18xx_ops = {
1401         .setup          = wl18xx_setup,
1402         .identify_chip  = wl18xx_identify_chip,
1403         .boot           = wl18xx_boot,
1404         .plt_init       = wl18xx_plt_init,
1405         .trigger_cmd    = wl18xx_trigger_cmd,
1406         .ack_event      = wl18xx_ack_event,
1407         .wait_for_event = wl18xx_wait_for_event,
1408         .process_mailbox_events = wl18xx_process_mailbox_events,
1409         .calc_tx_blocks = wl18xx_calc_tx_blocks,
1410         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1411         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1412         .get_rx_buf_align = wl18xx_get_rx_buf_align,
1413         .get_rx_packet_len = wl18xx_get_rx_packet_len,
1414         .tx_immediate_compl = wl18xx_tx_immediate_completion,
1415         .tx_delayed_compl = NULL,
1416         .hw_init        = wl18xx_hw_init,
1417         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1418         .get_pg_ver     = wl18xx_get_pg_ver,
1419         .set_rx_csum = wl18xx_set_rx_csum,
1420         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1421         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1422         .get_mac        = wl18xx_get_mac,
1423         .debugfs_init   = wl18xx_debugfs_add_files,
1424         .scan_start     = wl18xx_scan_start,
1425         .scan_stop      = wl18xx_scan_stop,
1426         .sched_scan_start       = wl18xx_sched_scan_start,
1427         .sched_scan_stop        = wl18xx_scan_sched_scan_stop,
1428         .handle_static_data     = wl18xx_handle_static_data,
1429         .get_spare_blocks = wl18xx_get_spare_blocks,
1430         .set_key        = wl18xx_set_key,
1431         .channel_switch = wl18xx_cmd_channel_switch,
1432         .pre_pkt_send   = wl18xx_pre_pkt_send,
1433         .sta_rc_update  = wl18xx_sta_rc_update,
1434         .set_peer_cap   = wl18xx_set_peer_cap,
1435 };
1436
1437 /* HT cap appropriate for wide channels in 2Ghz */
1438 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1439         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1440                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1441                IEEE80211_HT_CAP_GRN_FLD,
1442         .ht_supported = true,
1443         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1444         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1445         .mcs = {
1446                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1447                 .rx_highest = cpu_to_le16(150),
1448                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1449                 },
1450 };
1451
1452 /* HT cap appropriate for wide channels in 5Ghz */
1453 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1454         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1455                IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1456                IEEE80211_HT_CAP_GRN_FLD,
1457         .ht_supported = true,
1458         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1459         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1460         .mcs = {
1461                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1462                 .rx_highest = cpu_to_le16(150),
1463                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1464                 },
1465 };
1466
1467 /* HT cap appropriate for SISO 20 */
1468 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1469         .cap = IEEE80211_HT_CAP_SGI_20 |
1470                IEEE80211_HT_CAP_GRN_FLD,
1471         .ht_supported = true,
1472         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1473         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1474         .mcs = {
1475                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1476                 .rx_highest = cpu_to_le16(72),
1477                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1478                 },
1479 };
1480
1481 /* HT cap appropriate for MIMO rates in 20mhz channel */
1482 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1483         .cap = IEEE80211_HT_CAP_SGI_20 |
1484                IEEE80211_HT_CAP_GRN_FLD,
1485         .ht_supported = true,
1486         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1487         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1488         .mcs = {
1489                 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1490                 .rx_highest = cpu_to_le16(144),
1491                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1492                 },
1493 };
1494
1495 static int wl18xx_setup(struct wl1271 *wl)
1496 {
1497         struct wl18xx_priv *priv = wl->priv;
1498         int ret;
1499
1500         wl->rtable = wl18xx_rtable;
1501         wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1502         wl->num_rx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1503         wl->num_channels = 2;
1504         wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1505         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1506         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1507         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1508         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1509         wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1510         wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1511
1512         if (num_rx_desc_param != -1)
1513                 wl->num_rx_desc = num_rx_desc_param;
1514
1515         ret = wl18xx_conf_init(wl, wl->dev);
1516         if (ret < 0)
1517                 return ret;
1518
1519         /* If the module param is set, update it in conf */
1520         if (board_type_param) {
1521                 if (!strcmp(board_type_param, "fpga")) {
1522                         priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1523                 } else if (!strcmp(board_type_param, "hdk")) {
1524                         priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1525                 } else if (!strcmp(board_type_param, "dvp")) {
1526                         priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1527                 } else if (!strcmp(board_type_param, "evb")) {
1528                         priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1529                 } else if (!strcmp(board_type_param, "com8")) {
1530                         priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1531                 } else {
1532                         wl1271_error("invalid board type '%s'",
1533                                 board_type_param);
1534                         return -EINVAL;
1535                 }
1536         }
1537
1538         if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1539                 wl1271_error("invalid board type '%d'",
1540                         priv->conf.phy.board_type);
1541                 return -EINVAL;
1542         }
1543
1544         if (low_band_component_param != -1)
1545                 priv->conf.phy.low_band_component = low_band_component_param;
1546         if (low_band_component_type_param != -1)
1547                 priv->conf.phy.low_band_component_type =
1548                         low_band_component_type_param;
1549         if (high_band_component_param != -1)
1550                 priv->conf.phy.high_band_component = high_band_component_param;
1551         if (high_band_component_type_param != -1)
1552                 priv->conf.phy.high_band_component_type =
1553                         high_band_component_type_param;
1554         if (pwr_limit_reference_11_abg_param != -1)
1555                 priv->conf.phy.pwr_limit_reference_11_abg =
1556                         pwr_limit_reference_11_abg_param;
1557         if (n_antennas_2_param != -1)
1558                 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1559         if (n_antennas_5_param != -1)
1560                 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1561         if (dc2dc_param != -1)
1562                 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1563
1564         if (ht_mode_param) {
1565                 if (!strcmp(ht_mode_param, "default"))
1566                         priv->conf.ht.mode = HT_MODE_DEFAULT;
1567                 else if (!strcmp(ht_mode_param, "wide"))
1568                         priv->conf.ht.mode = HT_MODE_WIDE;
1569                 else if (!strcmp(ht_mode_param, "siso20"))
1570                         priv->conf.ht.mode = HT_MODE_SISO20;
1571                 else {
1572                         wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1573                         return -EINVAL;
1574                 }
1575         }
1576
1577         if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
1578                 /*
1579                  * Only support mimo with multiple antennas. Fall back to
1580                  * siso40.
1581                  */
1582                 if (wl18xx_is_mimo_supported(wl))
1583                         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1584                                           &wl18xx_mimo_ht_cap_2ghz);
1585                 else
1586                         wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1587                                           &wl18xx_siso40_ht_cap_2ghz);
1588
1589                 /* 5Ghz is always wide */
1590                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1591                                   &wl18xx_siso40_ht_cap_5ghz);
1592         } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
1593                 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1594                                   &wl18xx_siso40_ht_cap_2ghz);
1595                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1596                                   &wl18xx_siso40_ht_cap_5ghz);
1597         } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
1598                 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1599                                   &wl18xx_siso20_ht_cap);
1600                 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1601                                   &wl18xx_siso20_ht_cap);
1602         }
1603
1604         if (!checksum_param) {
1605                 wl18xx_ops.set_rx_csum = NULL;
1606                 wl18xx_ops.init_vif = NULL;
1607         }
1608
1609         /* Enable 11a Band only if we have 5G antennas */
1610         wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1611
1612         return 0;
1613 }
1614
1615 static int __devinit wl18xx_probe(struct platform_device *pdev)
1616 {
1617         struct wl1271 *wl;
1618         struct ieee80211_hw *hw;
1619         int ret;
1620
1621         hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
1622                              WL18XX_AGGR_BUFFER_SIZE,
1623                              sizeof(struct wl18xx_event_mailbox));
1624         if (IS_ERR(hw)) {
1625                 wl1271_error("can't allocate hw");
1626                 ret = PTR_ERR(hw);
1627                 goto out;
1628         }
1629
1630         wl = hw->priv;
1631         wl->ops = &wl18xx_ops;
1632         wl->ptable = wl18xx_ptable;
1633         ret = wlcore_probe(wl, pdev);
1634         if (ret)
1635                 goto out_free;
1636
1637         return ret;
1638
1639 out_free:
1640         wlcore_free_hw(wl);
1641 out:
1642         return ret;
1643 }
1644
1645 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1646         { "wl18xx", 0 },
1647         {  } /* Terminating Entry */
1648 };
1649 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1650
1651 static struct platform_driver wl18xx_driver = {
1652         .probe          = wl18xx_probe,
1653         .remove         = __devexit_p(wlcore_remove),
1654         .id_table       = wl18xx_id_table,
1655         .driver = {
1656                 .name   = "wl18xx_driver",
1657                 .owner  = THIS_MODULE,
1658         }
1659 };
1660
1661 module_platform_driver(wl18xx_driver);
1662 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1663 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1664
1665 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1666 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1667                  "dvp");
1668
1669 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1670 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1671
1672 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1673 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1674
1675 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1676 MODULE_PARM_DESC(n_antennas_2,
1677                  "Number of installed 2.4GHz antennas: 1 (default) or 2");
1678
1679 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1680 MODULE_PARM_DESC(n_antennas_5,
1681                  "Number of installed 5GHz antennas: 1 (default) or 2");
1682
1683 module_param_named(low_band_component, low_band_component_param, int,
1684                    S_IRUSR);
1685 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1686                  "(default is 0x01)");
1687
1688 module_param_named(low_band_component_type, low_band_component_type_param,
1689                    int, S_IRUSR);
1690 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1691                  "(default is 0x05 or 0x06 depending on the board_type)");
1692
1693 module_param_named(high_band_component, high_band_component_param, int,
1694                    S_IRUSR);
1695 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1696                  "(default is 0x01)");
1697
1698 module_param_named(high_band_component_type, high_band_component_type_param,
1699                    int, S_IRUSR);
1700 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1701                  "(default is 0x09)");
1702
1703 module_param_named(pwr_limit_reference_11_abg,
1704                    pwr_limit_reference_11_abg_param, int, S_IRUSR);
1705 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1706                  "(default is 0xc8)");
1707
1708 module_param_named(num_rx_desc,
1709                    num_rx_desc_param, int, S_IRUSR);
1710 MODULE_PARM_DESC(num_rx_desc_param,
1711                  "Number of Rx descriptors: u8 (default is 32)");
1712
1713 MODULE_LICENSE("GPL v2");
1714 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1715 MODULE_FIRMWARE(WL18XX_FW_NAME);