2 * This file is part of wl1271
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2010 Nokia Corporation
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #ifndef __WL1271_ACX_H__
26 #define __WL1271_ACX_H__
29 #include "wl1271_cmd.h"
31 /*************************************************************************
33 Host Interrupt Register (WiLink -> Host)
35 **************************************************************************/
36 /* HW Initiated interrupt Watchdog timer expiration */
37 #define WL1271_ACX_INTR_WATCHDOG BIT(0)
38 /* Init sequence is done (masked interrupt, detection through polling only ) */
39 #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40 /* Event was entered to Event MBOX #A*/
41 #define WL1271_ACX_INTR_EVENT_A BIT(2)
42 /* Event was entered to Event MBOX #B*/
43 #define WL1271_ACX_INTR_EVENT_B BIT(3)
44 /* Command processing completion*/
45 #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46 /* Signaling the host on HW wakeup */
47 #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49 #define WL1271_ACX_INTR_DATA BIT(6)
50 /* Trace message on MBOX #A */
51 #define WL1271_ACX_INTR_TRACE_A BIT(7)
52 /* Trace message on MBOX #B */
53 #define WL1271_ACX_INTR_TRACE_B BIT(8)
55 #define WL1271_ACX_INTR_ALL 0xFFFFFFFF
56 #define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
57 WL1271_ACX_INTR_INIT_COMPLETE | \
58 WL1271_ACX_INTR_EVENT_A | \
59 WL1271_ACX_INTR_EVENT_B | \
60 WL1271_ACX_INTR_CMD_COMPLETE | \
61 WL1271_ACX_INTR_HW_AVAILABLE | \
64 #define WL1271_INTR_MASK (WL1271_ACX_INTR_EVENT_A | \
65 WL1271_ACX_INTR_EVENT_B | \
66 WL1271_ACX_INTR_HW_AVAILABLE | \
69 /* Target's information element */
71 struct wl1271_cmd_header cmd;
73 /* acx (or information element) header */
76 /* payload length (not including headers */
80 struct acx_error_counter {
81 struct acx_header header;
83 /* The number of PLCP errors since the last time this */
84 /* information element was interrogated. This field is */
85 /* automatically cleared when it is interrogated.*/
88 /* The number of FCS errors since the last time this */
89 /* information element was interrogated. This field is */
90 /* automatically cleared when it is interrogated.*/
93 /* The number of MPDUs without PLCP header errors received*/
94 /* since the last time this information element was interrogated. */
95 /* This field is automatically cleared when it is interrogated.*/
98 /* the number of missed sequence numbers in the squentially */
99 /* values of frames seq numbers */
103 enum wl1271_psm_mode {
107 /* Power save mode */
110 /* Extreme low power */
114 struct acx_sleep_auth {
115 struct acx_header header;
117 /* The sleep level authorization of the device. */
118 /* 0 - Always active*/
119 /* 1 - Power down mode: light / fast sleep*/
120 /* 2 - ELP mode: Deep / Max sleep*/
126 HOSTIF_PCI_MASTER_HOST_INDIRECT,
127 HOSTIF_PCI_MASTER_HOST_DIRECT,
130 HOSTIF_DONTCARE = 0xFF
133 #define DEFAULT_UCAST_PRIORITY 0
134 #define DEFAULT_RX_Q_PRIORITY 0
135 #define DEFAULT_NUM_STATIONS 1
136 #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
137 #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
138 #define TRACE_BUFFER_MAX_SIZE 256
140 #define DP_RX_PACKET_RING_CHUNK_SIZE 1600
141 #define DP_TX_PACKET_RING_CHUNK_SIZE 1600
142 #define DP_RX_PACKET_RING_CHUNK_NUM 2
143 #define DP_TX_PACKET_RING_CHUNK_NUM 2
144 #define DP_TX_COMPLETE_TIME_OUT 20
146 #define TX_MSDU_LIFETIME_MIN 0
147 #define TX_MSDU_LIFETIME_MAX 3000
148 #define TX_MSDU_LIFETIME_DEF 512
149 #define RX_MSDU_LIFETIME_MIN 0
150 #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
151 #define RX_MSDU_LIFETIME_DEF 512000
153 struct acx_rx_msdu_lifetime {
154 struct acx_header header;
157 * The maximum amount of time, in TU, before the
158 * firmware discards the MSDU.
164 * RX Config Options Table
168 * 13 Copy RX Status - when set, write three receive status words
169 * to top of rx'd MPDUs.
170 * When cleared, do not write three status words (added rev 1.5)
172 * 11 RX Complete upon FCS error - when set, give rx complete
173 * interrupt for FCS errors, after the rx filtering, e.g. unicast
174 * frames not to us with FCS error will not generate an interrupt.
175 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
176 * probe request, and probe response frames with an SSID that does
177 * not match the SSID specified by the host in the START/JOIN
179 * When clear, the WiLink receives frames with any SSID.
180 * 9 Broadcast Filter Enable - When set, the WiLink discards all
181 * broadcast frames. When clear, the WiLink receives all received
184 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
185 * with a BSSID that does not match the BSSID specified by the
187 * When clear, the WiLink receives frames from any BSSID.
188 * 4 MAC Addr Filter - When set, the WiLink discards any frames
189 * with a destination address that does not match the MAC address
191 * When clear, the WiLink receives frames destined to any MAC
193 * 3 Promiscuous - When set, the WiLink receives all valid frames
194 * (i.e., all frames that pass the FCS check).
195 * When clear, only frames that pass the other filters specified
197 * 2 FCS - When set, the WiLink includes the FCS with the received
199 * When cleared, the FCS is discarded.
200 * 1 PLCP header - When set, write all data from baseband to frame
201 * buffer including PHY header.
202 * 0 Reserved - Always equal to 0.
204 * RX Filter Options Table
207 * 31:12 Reserved - Always equal to 0.
208 * 11 Association - When set, the WiLink receives all association
209 * related frames (association request/response, reassocation
210 * request/response, and disassociation). When clear, these frames
212 * 10 Auth/De auth - When set, the WiLink receives all authentication
213 * and de-authentication frames. When clear, these frames are
215 * 9 Beacon - When set, the WiLink receives all beacon frames.
216 * When clear, these frames are discarded.
217 * 8 Contention Free - When set, the WiLink receives all contention
219 * When clear, these frames are discarded.
220 * 7 Control - When set, the WiLink receives all control frames.
221 * When clear, these frames are discarded.
222 * 6 Data - When set, the WiLink receives all data frames.
223 * When clear, these frames are discarded.
224 * 5 FCS Error - When set, the WiLink receives frames that have FCS
226 * When clear, these frames are discarded.
227 * 4 Management - When set, the WiLink receives all management
229 * When clear, these frames are discarded.
230 * 3 Probe Request - When set, the WiLink receives all probe request
232 * When clear, these frames are discarded.
233 * 2 Probe Response - When set, the WiLink receives all probe
235 * When clear, these frames are discarded.
236 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
238 * When clear, these frames are discarded.
239 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
240 * that have reserved frame types and sub types as defined by the
241 * 802.11 specification.
242 * When clear, these frames are discarded.
244 struct acx_rx_config {
245 struct acx_header header;
247 __le32 config_options;
248 __le32 filter_options;
251 struct acx_packet_detection {
252 struct acx_header header;
261 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
262 MAX_SLOT_TIMES = 0xFF
265 #define STATION_WONE_INDEX 0
268 struct acx_header header;
270 u8 wone_index; /* Reserved */
276 #define ACX_MC_ADDRESS_GROUP_MAX (8)
277 #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
279 struct acx_dot11_grp_addr_tbl {
280 struct acx_header header;
285 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
288 struct acx_rx_timeout {
289 struct acx_header header;
291 __le16 ps_poll_timeout;
295 struct acx_rts_threshold {
296 struct acx_header header;
302 struct acx_beacon_filter_option {
303 struct acx_header header;
308 * The number of beacons without the unicast TIM
309 * bit set that the firmware buffers before
310 * signaling the host about ready frames.
311 * When set to 0 and the filter is enabled, beacons
312 * without the unicast TIM bit set are dropped.
319 * ACXBeaconFilterEntry (not 221)
320 * Byte Offset Size (Bytes) Definition
321 * =========== ============ ==========
323 * 1 1 Treatment bit mask
325 * ACXBeaconFilterEntry (221)
326 * Byte Offset Size (Bytes) Definition
327 * =========== ============ ==========
329 * 1 1 Treatment bit mask
335 * Treatment bit mask - The information element handling:
336 * bit 0 - The information element is compared and transferred
338 * bit 1 - The information element is transferred to the host
339 * with each appearance or disappearance.
340 * Note that both bits can be set at the same time.
342 #define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
343 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
344 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
345 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
346 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
347 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
348 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
349 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
351 struct acx_beacon_filter_ie_table {
352 struct acx_header header;
356 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
359 struct acx_conn_monit_params {
360 struct acx_header header;
362 __le32 synch_fail_thold; /* number of beacons missed */
363 __le32 bss_lose_timeout; /* number of TU's from synch fail */
366 struct acx_bt_wlan_coex {
367 struct acx_header header;
373 struct acx_bt_wlan_coex_param {
374 struct acx_header header;
376 __le32 params[CONF_SG_PARAMS_MAX];
381 struct acx_dco_itrim_params {
382 struct acx_header header;
389 struct acx_energy_detection {
390 struct acx_header header;
392 /* The RX Clear Channel Assessment threshold in the PHY */
393 __le16 rx_cca_threshold;
394 u8 tx_energy_detection;
398 struct acx_beacon_broadcast {
399 struct acx_header header;
401 __le16 beacon_rx_timeout;
402 __le16 broadcast_timeout;
404 /* Enables receiving of broadcast packets in PS mode */
405 u8 rx_broadcast_in_ps;
407 /* Consecutive PS Poll failures before updating the host */
408 u8 ps_poll_threshold;
412 struct acx_event_mask {
413 struct acx_header header;
416 __le32 high_event_mask; /* Unused */
419 #define CFG_RX_FCS BIT(2)
420 #define CFG_RX_ALL_GOOD BIT(3)
421 #define CFG_UNI_FILTER_EN BIT(4)
422 #define CFG_BSSID_FILTER_EN BIT(5)
423 #define CFG_MC_FILTER_EN BIT(6)
424 #define CFG_MC_ADDR0_EN BIT(7)
425 #define CFG_MC_ADDR1_EN BIT(8)
426 #define CFG_BC_REJECT_EN BIT(9)
427 #define CFG_SSID_FILTER_EN BIT(10)
428 #define CFG_RX_INT_FCS_ERROR BIT(11)
429 #define CFG_RX_INT_ENCRYPTED BIT(12)
430 #define CFG_RX_WR_RX_STATUS BIT(13)
431 #define CFG_RX_FILTER_NULTI BIT(14)
432 #define CFG_RX_RESERVE BIT(15)
433 #define CFG_RX_TIMESTAMP_TSF BIT(16)
435 #define CFG_RX_RSV_EN BIT(0)
436 #define CFG_RX_RCTS_ACK BIT(1)
437 #define CFG_RX_PRSP_EN BIT(2)
438 #define CFG_RX_PREQ_EN BIT(3)
439 #define CFG_RX_MGMT_EN BIT(4)
440 #define CFG_RX_FCS_ERROR BIT(5)
441 #define CFG_RX_DATA_EN BIT(6)
442 #define CFG_RX_CTL_EN BIT(7)
443 #define CFG_RX_CF_EN BIT(8)
444 #define CFG_RX_BCN_EN BIT(9)
445 #define CFG_RX_AUTH_EN BIT(10)
446 #define CFG_RX_ASSOC_EN BIT(11)
448 #define SCAN_PASSIVE BIT(0)
449 #define SCAN_5GHZ_BAND BIT(1)
450 #define SCAN_TRIGGERED BIT(2)
451 #define SCAN_PRIORITY_HIGH BIT(3)
453 /* When set, disable HW encryption */
454 #define DF_ENCRYPTION_DISABLE 0x01
455 #define DF_SNIFF_MODE_ENABLE 0x80
457 struct acx_feature_config {
458 struct acx_header header;
461 __le32 data_flow_options;
464 struct acx_current_tx_power {
465 struct acx_header header;
471 struct acx_wake_up_condition {
472 struct acx_header header;
474 u8 wake_up_event; /* Only one bit can be set */
480 struct acx_header header;
483 * To be set when associated with an AP.
489 enum acx_preamble_type {
490 ACX_PREAMBLE_LONG = 0,
491 ACX_PREAMBLE_SHORT = 1
494 struct acx_preamble {
495 struct acx_header header;
498 * When set, the WiLink transmits the frames with a short preamble and
499 * when cleared, the WiLink transmits the frames with a long preamble.
505 enum acx_ctsprotect_type {
506 CTSPROTECT_DISABLE = 0,
507 CTSPROTECT_ENABLE = 1
510 struct acx_ctsprotect {
511 struct acx_header header;
516 struct acx_tx_statistics {
517 __le32 internal_desc_overflow;
520 struct acx_rx_statistics {
526 __le32 xfr_hint_trig;
528 __le32 reset_counter;
531 struct acx_dma_statistics {
538 struct acx_isr_statistics {
539 /* host command complete */
545 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
548 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
551 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
552 __le32 rx_mem_overflow;
554 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
560 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
563 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
566 /* (INT_STS_ND & INT_TRIG_DMA0) */
569 /* (INT_STS_ND & INT_TRIG_DMA1) */
572 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
573 __le32 tx_exch_complete;
575 /* (INT_STS_ND & INT_TRIG_COMMAND) */
578 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
581 /* (INT_STS_ND & INT_TRIG_PM_802) */
582 __le32 hw_pm_mode_changes;
584 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
585 __le32 host_acknowledges;
587 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
590 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
593 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
597 struct acx_wep_statistics {
598 /* WEP address keys configured */
599 __le32 addr_key_count;
601 /* default keys configured */
602 __le32 default_key_count;
606 /* number of times that WEP key not found on lookup */
607 __le32 key_not_found;
609 /* number of times that WEP key decryption failed */
612 /* WEP packets decrypted */
615 /* WEP decrypt interrupts */
619 #define ACX_MISSED_BEACONS_SPREAD 10
621 struct acx_pwr_statistics {
622 /* the amount of enters into power save mode (both PD & ELP) */
625 /* the amount of enters into ELP mode */
628 /* the amount of missing beacon interrupts to the host */
631 /* the amount of wake on host-access times */
634 /* the amount of wake on timer-expire */
635 __le32 wake_on_timer_exp;
637 /* the number of packets that were transmitted with PS bit set */
640 /* the number of packets that were transmitted with PS bit clear */
641 __le32 tx_without_ps;
643 /* the number of received beacons */
646 /* the number of entering into PowerOn (power save off) */
647 __le32 power_save_off;
649 /* the number of entries into power save mode */
653 * the number of exits from power save, not including failed PS
659 * the number of times the TSF counter was adjusted because
664 /* Gives statistics about the spread continuous missed beacons.
665 * The 16 LSB are dedicated for the PS mode.
666 * The 16 MSB are dedicated for the PS mode.
667 * cont_miss_bcns_spread[0] - single missed beacon.
668 * cont_miss_bcns_spread[1] - two continuous missed beacons.
669 * cont_miss_bcns_spread[2] - three continuous missed beacons.
671 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
673 __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
675 /* the number of beacons in awake mode */
676 __le32 rcvd_awake_beacons;
679 struct acx_mic_statistics {
684 struct acx_aes_statistics {
687 __le32 encrypt_packets;
688 __le32 decrypt_packets;
689 __le32 encrypt_interrupt;
690 __le32 decrypt_interrupt;
693 struct acx_event_statistics {
700 __le32 phy_transmit_error;
704 struct acx_ps_statistics {
705 __le32 pspoll_timeouts;
706 __le32 upsd_timeouts;
707 __le32 upsd_max_sptime;
708 __le32 upsd_max_apturn;
709 __le32 pspoll_max_apturn;
710 __le32 pspoll_utilization;
711 __le32 upsd_utilization;
714 struct acx_rxpipe_statistics {
715 __le32 rx_prep_beacon_drop;
716 __le32 descr_host_int_trig_rx_data;
717 __le32 beacon_buffer_thres_host_int_trig_rx_data;
718 __le32 missed_beacon_host_int_trig_rx_data;
719 __le32 tx_xfr_host_int_trig_rx_data;
722 struct acx_statistics {
723 struct acx_header header;
725 struct acx_tx_statistics tx;
726 struct acx_rx_statistics rx;
727 struct acx_dma_statistics dma;
728 struct acx_isr_statistics isr;
729 struct acx_wep_statistics wep;
730 struct acx_pwr_statistics pwr;
731 struct acx_aes_statistics aes;
732 struct acx_mic_statistics mic;
733 struct acx_event_statistics event;
734 struct acx_ps_statistics ps;
735 struct acx_rxpipe_statistics rxpipe;
738 struct acx_rate_class {
739 __le32 enabled_rates;
740 u8 short_retry_limit;
746 #define ACX_TX_BASIC_RATE 0
747 #define ACX_TX_AP_FULL_RATE 1
748 #define ACX_TX_RATE_POLICY_CNT 2
749 struct acx_rate_policy {
750 struct acx_header header;
752 __le32 rate_class_cnt;
753 struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES];
757 struct acx_header header;
766 struct acx_tid_config {
767 struct acx_header header;
777 struct acx_frag_threshold {
778 struct acx_header header;
779 __le16 frag_threshold;
783 struct acx_tx_config_options {
784 struct acx_header header;
785 __le16 tx_compl_timeout; /* msec */
786 __le16 tx_compl_threshold; /* number of packets */
789 #define ACX_RX_MEM_BLOCKS 70
790 #define ACX_TX_MIN_MEM_BLOCKS 40
791 #define ACX_TX_DESCRIPTORS 32
792 #define ACX_NUM_SSID_PROFILES 1
794 struct wl1271_acx_config_memory {
795 struct acx_header header;
798 u8 tx_min_mem_block_num;
800 u8 num_ssid_profiles;
801 __le32 total_tx_descriptors;
804 struct wl1271_acx_mem_map {
805 struct acx_header header;
810 __le32 wep_defkey_start;
811 __le32 wep_defkey_end;
813 __le32 sta_table_start;
814 __le32 sta_table_end;
816 __le32 packet_template_start;
817 __le32 packet_template_end;
819 /* Address of the TX result interface (control block) */
821 __le32 tx_result_queue_start;
823 __le32 queue_memory_start;
824 __le32 queue_memory_end;
826 __le32 packet_memory_pool_start;
827 __le32 packet_memory_pool_end;
829 __le32 debug_buffer1_start;
830 __le32 debug_buffer1_end;
832 __le32 debug_buffer2_start;
833 __le32 debug_buffer2_end;
835 /* Number of blocks FW allocated for TX packets */
836 __le32 num_tx_mem_blocks;
838 /* Number of blocks FW allocated for RX packets */
839 __le32 num_rx_mem_blocks;
841 /* the following 4 fields are valid in SLAVE mode only */
848 struct wl1271_acx_rx_config_opt {
849 struct acx_header header;
851 __le16 mblk_threshold;
859 struct wl1271_acx_bet_enable {
860 struct acx_header header;
867 #define ACX_IPV4_VERSION 4
868 #define ACX_IPV6_VERSION 6
869 #define ACX_IPV4_ADDR_SIZE 4
870 struct wl1271_acx_arp_filter {
871 struct acx_header header;
872 u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
873 u8 enable; /* 1 to enable ARP filtering, 0 to disable */
875 u8 address[16]; /* The configured device IP address - all ARP
876 requests directed to this IP address will pass
877 through. For IPv4, the first four bytes are
881 struct wl1271_acx_pm_config {
882 struct acx_header header;
884 __le32 host_clk_settling_time;
885 u8 host_fast_wakeup_support;
889 struct wl1271_acx_keep_alive_mode {
890 struct acx_header header;
897 ACX_KEEP_ALIVE_NO_TX = 0,
898 ACX_KEEP_ALIVE_PERIOD_ONLY
902 ACX_KEEP_ALIVE_TPL_INVALID = 0,
903 ACX_KEEP_ALIVE_TPL_VALID
906 struct wl1271_acx_keep_alive_config {
907 struct acx_header header;
917 WL1271_ACX_TRIG_TYPE_LEVEL = 0,
918 WL1271_ACX_TRIG_TYPE_EDGE,
922 WL1271_ACX_TRIG_DIR_LOW = 0,
923 WL1271_ACX_TRIG_DIR_HIGH,
924 WL1271_ACX_TRIG_DIR_BIDIR,
928 WL1271_ACX_TRIG_ENABLE = 1,
929 WL1271_ACX_TRIG_DISABLE,
933 WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
934 WL1271_ACX_TRIG_METRIC_RSSI_DATA,
935 WL1271_ACX_TRIG_METRIC_SNR_BEACON,
936 WL1271_ACX_TRIG_METRIC_SNR_DATA,
940 WL1271_ACX_TRIG_IDX_RSSI = 0,
941 WL1271_ACX_TRIG_COUNT = 8,
944 struct wl1271_acx_rssi_snr_trigger {
945 struct acx_header header;
948 __le16 pacing; /* 0 - 60000 ms */
958 struct wl1271_acx_rssi_snr_avg_weights {
959 struct acx_header header;
967 struct wl1271_acx_fw_tsf_information {
968 struct acx_header header;
970 __le32 current_tsf_high;
971 __le32 current_tsf_low;
972 __le32 last_bttt_high;
973 __le32 last_tbtt_low;
979 ACX_WAKE_UP_CONDITIONS = 0x0002,
980 ACX_MEM_CFG = 0x0003,
983 ACX_MEM_MAP = 0x0008,
985 /* ACX_FW_REV is missing in the ref driver, but seems to work */
987 ACX_MEDIUM_USAGE = 0x000F,
989 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */
990 ACX_STATISTICS = 0x0013, /* Debug API */
991 ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
992 ACX_FEATURE_CFG = 0x0015,
993 ACX_TID_CFG = 0x001A,
994 ACX_PS_RX_STREAMING = 0x001B,
995 ACX_BEACON_FILTER_OPT = 0x001F,
996 ACX_NOISE_HIST = 0x0021,
997 ACX_HDK_VERSION = 0x0022, /* ??? */
998 ACX_PD_THRESHOLD = 0x0023,
999 ACX_TX_CONFIG_OPT = 0x0024,
1000 ACX_CCA_THRESHOLD = 0x0025,
1001 ACX_EVENT_MBOX_MASK = 0x0026,
1002 ACX_CONN_MONIT_PARAMS = 0x002D,
1003 ACX_CONS_TX_FAILURE = 0x002F,
1004 ACX_BCN_DTIM_OPTIONS = 0x0031,
1005 ACX_SG_ENABLE = 0x0032,
1006 ACX_SG_CFG = 0x0033,
1007 ACX_BEACON_FILTER_TABLE = 0x0038,
1008 ACX_ARP_IP_FILTER = 0x0039,
1009 ACX_ROAMING_STATISTICS_TBL = 0x003B,
1010 ACX_RATE_POLICY = 0x003D,
1011 ACX_CTS_PROTECTION = 0x003E,
1012 ACX_SLEEP_AUTH = 0x003F,
1013 ACX_PREAMBLE_TYPE = 0x0040,
1014 ACX_ERROR_CNT = 0x0041,
1015 ACX_IBSS_FILTER = 0x0044,
1016 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1017 ACX_TSF_INFO = 0x0046,
1018 ACX_CONFIG_PS_WMM = 0x0049,
1019 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1020 ACX_SET_RX_DATA_FILTER = 0x004B,
1021 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1022 ACX_RX_CONFIG_OPT = 0x004E,
1023 ACX_FRAG_CFG = 0x004F,
1024 ACX_BET_ENABLE = 0x0050,
1025 ACX_RSSI_SNR_TRIGGER = 0x0051,
1026 ACX_RSSI_SNR_WEIGHTS = 0x0052,
1027 ACX_KEEP_ALIVE_MODE = 0x0053,
1028 ACX_SET_KEEP_ALIVE_CONFIG = 0x0054,
1029 ACX_BA_SESSION_RESPONDER_POLICY = 0x0055,
1030 ACX_BA_SESSION_INITIATOR_POLICY = 0x0056,
1031 ACX_PEER_HT_CAP = 0x0057,
1032 ACX_HT_BSS_OPERATION = 0x0058,
1033 ACX_COEX_ACTIVITY = 0x0059,
1034 ACX_SET_DCO_ITRIM_PARAMS = 0x0061,
1035 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1036 DOT11_CUR_TX_PWR = 0x100D,
1037 DOT11_RX_DOT11_MODE = 0x1012,
1038 DOT11_RTS_THRESHOLD = 0x1013,
1039 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1040 ACX_PM_CONFIG = 0x1016,
1042 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1048 int wl1271_acx_wake_up_conditions(struct wl1271 *wl);
1049 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1050 int wl1271_acx_tx_power(struct wl1271 *wl, int power);
1051 int wl1271_acx_feature_cfg(struct wl1271 *wl);
1052 int wl1271_acx_mem_map(struct wl1271 *wl,
1053 struct acx_header *mem_map, size_t len);
1054 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1055 int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
1056 int wl1271_acx_pd_threshold(struct wl1271 *wl);
1057 int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
1058 int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable,
1059 void *mc_list, u32 mc_list_len);
1060 int wl1271_acx_service_period_timeout(struct wl1271 *wl);
1061 int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold);
1062 int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1063 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter);
1064 int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
1065 int wl1271_acx_conn_monit_params(struct wl1271 *wl, bool enable);
1066 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1067 int wl1271_acx_sg_cfg(struct wl1271 *wl);
1068 int wl1271_acx_cca_threshold(struct wl1271 *wl);
1069 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
1070 int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
1071 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1072 int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
1073 int wl1271_acx_cts_protect(struct wl1271 *wl,
1074 enum acx_ctsprotect_type ctsprotect);
1075 int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
1076 int wl1271_acx_rate_policies(struct wl1271 *wl);
1077 int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max,
1078 u8 aifsn, u16 txop);
1079 int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type,
1080 u8 tsid, u8 ps_scheme, u8 ack_policy,
1081 u32 apsd_conf0, u32 apsd_conf1);
1082 int wl1271_acx_frag_threshold(struct wl1271 *wl);
1083 int wl1271_acx_tx_config_options(struct wl1271 *wl);
1084 int wl1271_acx_mem_cfg(struct wl1271 *wl);
1085 int wl1271_acx_init_mem_config(struct wl1271 *wl);
1086 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1087 int wl1271_acx_smart_reflex(struct wl1271 *wl);
1088 int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable);
1089 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, bool enable, __be32 address);
1090 int wl1271_acx_pm_config(struct wl1271 *wl);
1091 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable);
1092 int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid);
1093 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable,
1094 s16 thold, u8 hyst);
1095 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl);
1096 int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
1098 #endif /* __WL1271_ACX_H__ */