2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/gpio.h>
25 #include <linux/slab.h>
27 #include "wl1271_acx.h"
28 #include "wl1271_reg.h"
29 #include "wl1271_boot.h"
30 #include "wl1271_io.h"
31 #include "wl1271_event.h"
33 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
40 .start = REGISTERS_BASE,
59 .start = REGISTERS_BASE,
92 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
96 /* 10.5.0 run the firmware (I) */
97 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
99 /* 10.5.1 run the firmware (II) */
101 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
104 static void wl1271_boot_fw_version(struct wl1271 *wl)
106 struct wl1271_static_data static_data;
108 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
111 strncpy(wl->chip.fw_ver, static_data.fw_version,
112 sizeof(wl->chip.fw_ver));
114 /* make sure the string is NULL-terminated */
115 wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
118 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
119 size_t fw_data_len, u32 dest)
121 struct wl1271_partition_set partition;
122 int addr, chunk_num, partition_limit;
125 /* whal_FwCtrl_LoadFwImageSm() */
127 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
129 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
130 fw_data_len, CHUNK_SIZE);
132 if ((fw_data_len % 4) != 0) {
133 wl1271_error("firmware length not multiple of four");
137 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
139 wl1271_error("allocation for firmware upload chunk failed");
143 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
144 partition.mem.start = dest;
145 wl1271_set_partition(wl, &partition);
147 /* 10.1 set partition limit and chunk num */
149 partition_limit = part_table[PART_DOWN].mem.size;
151 while (chunk_num < fw_data_len / CHUNK_SIZE) {
152 /* 10.2 update partition, if needed */
153 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
154 if (addr > partition_limit) {
155 addr = dest + chunk_num * CHUNK_SIZE;
156 partition_limit = chunk_num * CHUNK_SIZE +
157 part_table[PART_DOWN].mem.size;
158 partition.mem.start = addr;
159 wl1271_set_partition(wl, &partition);
162 /* 10.3 upload the chunk */
163 addr = dest + chunk_num * CHUNK_SIZE;
164 p = buf + chunk_num * CHUNK_SIZE;
165 memcpy(chunk, p, CHUNK_SIZE);
166 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
168 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
173 /* 10.4 upload the last chunk */
174 addr = dest + chunk_num * CHUNK_SIZE;
175 p = buf + chunk_num * CHUNK_SIZE;
176 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
177 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
178 fw_data_len % CHUNK_SIZE, p, addr);
179 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
185 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
187 u32 chunks, addr, len;
192 chunks = be32_to_cpup((__be32 *) fw);
195 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
198 addr = be32_to_cpup((__be32 *) fw);
200 len = be32_to_cpup((__be32 *) fw);
204 wl1271_info("firmware chunk too long: %u", len);
207 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
209 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
218 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
220 size_t nvs_len, burst_len;
223 u8 *nvs_ptr, *nvs_aligned;
229 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
230 * configurations) can be removed when those NVS files stop floating
233 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
234 wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
235 if (wl->nvs->general_params.dual_mode_select)
236 wl->enable_11a = true;
239 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
240 (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
242 wl1271_error("nvs size is not as expected: %zu != %zu",
243 wl->nvs_len, sizeof(struct wl1271_nvs_file));
250 /* only the first part of the NVS needs to be uploaded */
251 nvs_len = sizeof(wl->nvs->nvs);
252 nvs_ptr = (u8 *)wl->nvs->nvs;
254 /* update current MAC address to NVS */
255 nvs_ptr[11] = wl->mac_addr[0];
256 nvs_ptr[10] = wl->mac_addr[1];
257 nvs_ptr[6] = wl->mac_addr[2];
258 nvs_ptr[5] = wl->mac_addr[3];
259 nvs_ptr[4] = wl->mac_addr[4];
260 nvs_ptr[3] = wl->mac_addr[5];
263 * Layout before the actual NVS tables:
264 * 1 byte : burst length.
265 * 2 bytes: destination address.
266 * n bytes: data to burst copy.
268 * This is ended by a 0 length, then the NVS tables.
271 /* FIXME: Do we need to check here whether the LSB is 1? */
273 burst_len = nvs_ptr[0];
274 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
277 * Due to our new wl1271_translate_reg_addr function,
278 * we need to add the REGISTER_BASE to the destination
280 dest_addr += REGISTERS_BASE;
282 /* We move our pointer to the data */
285 for (i = 0; i < burst_len; i++) {
286 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
287 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
289 wl1271_debug(DEBUG_BOOT,
290 "nvs burst write 0x%x: 0x%x",
292 wl1271_write32(wl, dest_addr, val);
300 * We've reached the first zero length, the first NVS table
301 * is located at an aligned offset which is at least 7 bytes further.
303 nvs_ptr = (u8 *)wl->nvs->nvs +
304 ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
305 nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
307 /* Now we must set the partition correctly */
308 wl1271_set_partition(wl, &part_table[PART_WORK]);
310 /* Copy the NVS tables to a new block to ensure alignment */
311 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
315 /* And finally we upload the NVS tables */
316 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
322 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
324 wl1271_enable_interrupts(wl);
325 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
326 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
327 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
330 static int wl1271_boot_soft_reset(struct wl1271 *wl)
332 unsigned long timeout;
335 /* perform soft reset */
336 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
338 /* SOFT_RESET is self clearing */
339 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
341 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
342 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
343 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
346 if (time_after(jiffies, timeout)) {
347 /* 1.2 check pWhalBus->uSelfClearTime if the
348 * timeout was reached */
349 wl1271_error("soft reset timeout");
353 udelay(SOFT_RESET_STALL_TIME);
357 wl1271_write32(wl, ENABLE, 0x0);
359 /* disable auto calibration on start*/
360 wl1271_write32(wl, SPARE_A2, 0xffff);
365 static int wl1271_boot_run_firmware(struct wl1271 *wl)
370 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
372 chip_id = wl1271_read32(wl, CHIP_ID_B);
374 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
376 if (chip_id != wl->chip.id) {
377 wl1271_error("chip id doesn't match after firmware boot");
381 /* wait for init to complete */
383 while (loop++ < INIT_LOOP) {
384 udelay(INIT_LOOP_DELAY);
385 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
387 if (intr == 0xffffffff) {
388 wl1271_error("error reading hardware complete "
392 /* check that ACX_INTR_INIT_COMPLETE is enabled */
393 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
394 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
395 WL1271_ACX_INTR_INIT_COMPLETE);
400 if (loop > INIT_LOOP) {
401 wl1271_error("timeout waiting for the hardware to "
402 "complete initialization");
406 /* get hardware config command mail box */
407 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
409 /* get hardware config event mail box */
410 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
412 /* set the working partition to its "running" mode offset */
413 wl1271_set_partition(wl, &part_table[PART_WORK]);
415 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
416 wl->cmd_box_addr, wl->event_box_addr);
418 wl1271_boot_fw_version(wl);
421 * in case of full asynchronous mode the firmware event must be
422 * ready to receive event from the command mailbox
425 /* unmask required mbox events */
426 wl->event_mask = BSS_LOSE_EVENT_ID |
427 SCAN_COMPLETE_EVENT_ID |
429 JOIN_EVENT_COMPLETE_ID |
430 DISCONNECT_EVENT_COMPLETE_ID |
431 RSSI_SNR_TRIGGER_0_EVENT_ID |
432 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
433 SOFT_GEMINI_SENSE_EVENT_ID;
435 ret = wl1271_event_unmask(wl);
437 wl1271_error("EVENT mask setting failed");
441 wl1271_event_mbox_config(wl);
443 /* firmware startup completed */
447 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
451 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
453 /* We use HIGH polarity, so unset the LOW bit */
454 polarity &= ~POLARITY_LOW;
455 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
460 static void wl1271_boot_hw_version(struct wl1271 *wl)
464 fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
465 fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
467 wl->hw_pg_ver = (s8)fuse;
470 int wl1271_boot(struct wl1271 *wl)
474 int ref_clock = wl->ref_clock;
476 wl1271_boot_hw_version(wl);
478 if (ref_clock == 0 || ref_clock == 2 || ref_clock == 4)
479 /* ref clk: 19.2/38.4/38.4-XTAL */
481 else if (ref_clock == 1 || ref_clock == 3)
487 if (ref_clock != 0) {
489 /* Set clock type (open drain) */
490 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
491 val &= FREF_CLK_TYPE_BITS;
492 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
494 /* Set clock pull mode (no pull) */
495 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
497 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
500 /* Set clock polarity */
501 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
502 val &= FREF_CLK_POLARITY_BITS;
503 val |= CLK_REQ_OUTN_SEL;
504 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
507 wl1271_write32(wl, PLL_PARAMETERS, clk);
509 pause = wl1271_read32(wl, PLL_PARAMETERS);
511 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
513 pause &= ~(WU_COUNTER_PAUSE_VAL);
514 pause |= WU_COUNTER_PAUSE_VAL;
515 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
517 /* Continue the ELP wake up sequence */
518 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
521 wl1271_set_partition(wl, &part_table[PART_DRPW]);
523 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
524 to be used by DRPw FW. The RTRIM value will be added by the FW
525 before taking DRPw out of reset */
527 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
528 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
530 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
533 clk |= (ref_clock << 1) << 4;
534 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
536 wl1271_set_partition(wl, &part_table[PART_WORK]);
538 /* Disable interrupts */
539 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
541 ret = wl1271_boot_soft_reset(wl);
545 /* 2. start processing NVS file */
546 ret = wl1271_boot_upload_nvs(wl);
550 /* write firmware's last address (ie. it's length) to
551 * ACX_EEPROMLESS_IND_REG */
552 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
554 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
556 tmp = wl1271_read32(wl, CHIP_ID_B);
558 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
560 /* 6. read the EEPROM parameters */
561 tmp = wl1271_read32(wl, SCR_PAD2);
563 ret = wl1271_boot_write_irq_polarity(wl);
567 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
568 WL1271_ACX_ALL_EVENTS_VECTOR);
570 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
573 ret = wl1271_boot_upload_firmware(wl);
577 /* 10.5 start firmware */
578 ret = wl1271_boot_run_firmware(wl);
582 /* Enable firmware interrupts now */
583 wl1271_boot_enable_interrupts(wl);
585 /* set the wl1271 default filters */
586 wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
587 wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
589 wl1271_event_mbox_config(wl);