1 /* ZD1211 USB-WLAN driver for Linux
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
34 void zd_chip_init(struct zd_chip *chip,
35 struct ieee80211_hw *hw,
36 struct usb_interface *intf)
38 memset(chip, 0, sizeof(*chip));
39 mutex_init(&chip->mutex);
40 zd_usb_init(&chip->usb, hw, intf);
41 zd_rf_init(&chip->rf);
44 void zd_chip_clear(struct zd_chip *chip)
46 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
47 zd_usb_clear(&chip->usb);
48 zd_rf_clear(&chip->rf);
49 mutex_destroy(&chip->mutex);
50 ZD_MEMCLEAR(chip, sizeof(*chip));
53 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
55 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
56 return scnprintf(buffer, size, "%02x-%02x-%02x",
57 addr[0], addr[1], addr[2]);
60 /* Prints an identifier line, which will support debugging. */
61 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
65 i = scnprintf(buffer, size, "zd1211%s chip ",
66 zd_chip_is_zd1211b(chip) ? "b" : "");
67 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += scnprint_mac_oui(chip, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " ");
71 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
72 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
73 chip->patch_cck_gain ? 'g' : '-',
74 chip->patch_cr157 ? '7' : '-',
75 chip->patch_6m_band_edge ? '6' : '-',
76 chip->new_phy_layout ? 'N' : '-',
77 chip->al2230s_bit ? 'S' : '-');
81 static void print_id(struct zd_chip *chip)
85 scnprint_id(chip, buffer, sizeof(buffer));
86 buffer[sizeof(buffer)-1] = 0;
87 dev_info(zd_chip_dev(chip), "%s\n", buffer);
90 static zd_addr_t inc_addr(zd_addr_t addr)
93 /* Control registers use byte addressing, but everything else uses word
95 if ((a & 0xf000) == CR_START)
102 /* Read a variable number of 32-bit values. Parameter count is not allowed to
103 * exceed USB_MAX_IOREAD32_COUNT.
105 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
112 unsigned int count16;
114 if (count > USB_MAX_IOREAD32_COUNT)
117 /* Allocate a single memory block for values and addresses. */
119 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
122 dev_dbg_f(zd_chip_dev(chip),
123 "error ENOMEM in allocation of a16\n");
127 v16 = (u16 *)(a16 + count16);
129 for (i = 0; i < count; i++) {
131 /* We read the high word always first. */
132 a16[j] = inc_addr(addr[i]);
136 r = zd_ioread16v_locked(chip, v16, a16, count16);
138 dev_dbg_f(zd_chip_dev(chip),
139 "error: zd_ioread16v_locked. Error number %d\n", r);
143 for (i = 0; i < count; i++) {
145 values[i] = (v16[j] << 16) | v16[j+1];
153 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
157 struct zd_ioreq16 *ioreqs16;
158 unsigned int count16;
160 ZD_ASSERT(mutex_is_locked(&chip->mutex));
164 if (count > USB_MAX_IOWRITE32_COUNT)
167 /* Allocate a single memory block for values and addresses. */
169 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
172 dev_dbg_f(zd_chip_dev(chip),
173 "error %d in ioreqs16 allocation\n", r);
177 for (i = 0; i < count; i++) {
179 /* We write the high word always first. */
180 ioreqs16[j].value = ioreqs[i].value >> 16;
181 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
182 ioreqs16[j+1].value = ioreqs[i].value;
183 ioreqs16[j+1].addr = ioreqs[i].addr;
186 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
189 dev_dbg_f(zd_chip_dev(chip),
190 "error %d in zd_usb_write16v\n", r);
198 int zd_iowrite16a_locked(struct zd_chip *chip,
199 const struct zd_ioreq16 *ioreqs, unsigned int count)
202 unsigned int i, j, t, max;
204 ZD_ASSERT(mutex_is_locked(&chip->mutex));
205 for (i = 0; i < count; i += j + t) {
208 if (max > USB_MAX_IOWRITE16_COUNT)
209 max = USB_MAX_IOWRITE16_COUNT;
210 for (j = 0; j < max; j++) {
211 if (!ioreqs[i+j].addr) {
217 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
219 dev_dbg_f(zd_chip_dev(chip),
220 "error zd_usb_iowrite16v. Error number %d\n",
229 /* Writes a variable number of 32 bit registers. The functions will split
230 * that in several USB requests. A split can be forced by inserting an IO
231 * request with an zero address field.
233 int zd_iowrite32a_locked(struct zd_chip *chip,
234 const struct zd_ioreq32 *ioreqs, unsigned int count)
237 unsigned int i, j, t, max;
239 for (i = 0; i < count; i += j + t) {
242 if (max > USB_MAX_IOWRITE32_COUNT)
243 max = USB_MAX_IOWRITE32_COUNT;
244 for (j = 0; j < max; j++) {
245 if (!ioreqs[i+j].addr) {
251 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
253 dev_dbg_f(zd_chip_dev(chip),
254 "error _zd_iowrite32v_locked."
255 " Error number %d\n", r);
263 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
267 mutex_lock(&chip->mutex);
268 r = zd_ioread16_locked(chip, value, addr);
269 mutex_unlock(&chip->mutex);
273 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
277 mutex_lock(&chip->mutex);
278 r = zd_ioread32_locked(chip, value, addr);
279 mutex_unlock(&chip->mutex);
283 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
287 mutex_lock(&chip->mutex);
288 r = zd_iowrite16_locked(chip, value, addr);
289 mutex_unlock(&chip->mutex);
293 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
297 mutex_lock(&chip->mutex);
298 r = zd_iowrite32_locked(chip, value, addr);
299 mutex_unlock(&chip->mutex);
303 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
304 u32 *values, unsigned int count)
308 mutex_lock(&chip->mutex);
309 r = zd_ioread32v_locked(chip, values, addresses, count);
310 mutex_unlock(&chip->mutex);
314 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
319 mutex_lock(&chip->mutex);
320 r = zd_iowrite32a_locked(chip, ioreqs, count);
321 mutex_unlock(&chip->mutex);
325 static int read_pod(struct zd_chip *chip, u8 *rf_type)
330 ZD_ASSERT(mutex_is_locked(&chip->mutex));
331 r = zd_ioread32_locked(chip, &value, E2P_POD);
334 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
336 /* FIXME: AL2230 handling (Bit 7 in POD) */
337 *rf_type = value & 0x0f;
338 chip->pa_type = (value >> 16) & 0x0f;
339 chip->patch_cck_gain = (value >> 8) & 0x1;
340 chip->patch_cr157 = (value >> 13) & 0x1;
341 chip->patch_6m_band_edge = (value >> 21) & 0x1;
342 chip->new_phy_layout = (value >> 31) & 0x1;
343 chip->al2230s_bit = (value >> 7) & 0x1;
344 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
345 chip->supports_tx_led = 1;
346 if (value & (1 << 24)) { /* LED scenario */
347 if (value & (1 << 29))
348 chip->supports_tx_led = 0;
351 dev_dbg_f(zd_chip_dev(chip),
352 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
353 "patch 6M %d new PHY %d link LED%d tx led %d\n",
354 zd_rf_name(*rf_type), *rf_type,
355 chip->pa_type, chip->patch_cck_gain,
356 chip->patch_cr157, chip->patch_6m_band_edge,
357 chip->new_phy_layout,
358 chip->link_led == LED1 ? 1 : 2,
359 chip->supports_tx_led);
364 chip->patch_cck_gain = 0;
365 chip->patch_cr157 = 0;
366 chip->patch_6m_band_edge = 0;
367 chip->new_phy_layout = 0;
371 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
372 * CR_MAC_ADDR_P2 must be overwritten
374 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
377 struct zd_ioreq32 reqs[2] = {
378 [0] = { .addr = CR_MAC_ADDR_P1 },
379 [1] = { .addr = CR_MAC_ADDR_P2 },
383 reqs[0].value = (mac_addr[3] << 24)
384 | (mac_addr[2] << 16)
387 reqs[1].value = (mac_addr[5] << 8)
389 dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr);
391 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
394 mutex_lock(&chip->mutex);
395 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
396 mutex_unlock(&chip->mutex);
400 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
405 mutex_lock(&chip->mutex);
406 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
407 mutex_unlock(&chip->mutex);
411 *regdomain = value >> 16;
412 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
417 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
418 zd_addr_t e2p_addr, u32 guard)
424 ZD_ASSERT(mutex_is_locked(&chip->mutex));
426 r = zd_ioread32_locked(chip, &v,
427 (zd_addr_t)((u16)e2p_addr+i/2));
433 values[i++] = v >> 8;
434 values[i++] = v >> 16;
435 values[i++] = v >> 24;
438 for (;i < count; i++)
439 values[i] = v >> (8*(i%3));
444 static int read_pwr_cal_values(struct zd_chip *chip)
446 return read_values(chip, chip->pwr_cal_values,
447 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
451 static int read_pwr_int_values(struct zd_chip *chip)
453 return read_values(chip, chip->pwr_int_values,
454 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
458 static int read_ofdm_cal_values(struct zd_chip *chip)
462 static const zd_addr_t addresses[] = {
468 for (i = 0; i < 3; i++) {
469 r = read_values(chip, chip->ofdm_cal_values[i],
470 E2P_CHANNEL_COUNT, addresses[i], 0);
477 static int read_cal_int_tables(struct zd_chip *chip)
481 r = read_pwr_cal_values(chip);
484 r = read_pwr_int_values(chip);
487 r = read_ofdm_cal_values(chip);
493 /* phy means physical registers */
494 int zd_chip_lock_phy_regs(struct zd_chip *chip)
499 ZD_ASSERT(mutex_is_locked(&chip->mutex));
500 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
502 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
506 tmp &= ~UNLOCK_PHY_REGS;
508 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
510 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
514 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
519 ZD_ASSERT(mutex_is_locked(&chip->mutex));
520 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
522 dev_err(zd_chip_dev(chip),
523 "error ioread32(CR_REG1): %d\n", r);
527 tmp |= UNLOCK_PHY_REGS;
529 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
531 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
535 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
536 static int patch_cr157(struct zd_chip *chip)
541 if (!chip->patch_cr157)
544 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
548 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
549 return zd_iowrite32_locked(chip, value >> 8, CR157);
553 * 6M band edge can be optionally overwritten for certain RF's
554 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
555 * bit (for AL2230, AL2230S)
557 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
559 ZD_ASSERT(mutex_is_locked(&chip->mutex));
560 if (!chip->patch_6m_band_edge)
563 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
566 /* Generic implementation of 6M band edge patching, used by most RFs via
567 * zd_rf_generic_patch_6m() */
568 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
570 struct zd_ioreq16 ioreqs[] = {
571 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
575 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
576 if (channel == 1 || channel == 11)
577 ioreqs[0].value = 0x12;
579 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
580 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
583 static int zd1211_hw_reset_phy(struct zd_chip *chip)
585 static const struct zd_ioreq16 ioreqs[] = {
586 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
587 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
588 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
589 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
590 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
591 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
592 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
593 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
594 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
595 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
596 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
597 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
598 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
599 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
600 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
601 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
602 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
603 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
604 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
605 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
606 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
607 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
608 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
609 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
610 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
611 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
612 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
613 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
614 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
615 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
616 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
617 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
618 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
620 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
621 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
622 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
623 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
624 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
625 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
626 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
627 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
628 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
629 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
630 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
631 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
632 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
633 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
634 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
635 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
636 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
637 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
638 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
639 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
640 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
641 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
642 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
643 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
644 { CR170, 0xba }, { CR171, 0xba },
645 /* Note: CR204 must lead the CR203 */
653 dev_dbg_f(zd_chip_dev(chip), "\n");
655 r = zd_chip_lock_phy_regs(chip);
659 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
663 r = patch_cr157(chip);
665 t = zd_chip_unlock_phy_regs(chip);
672 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
674 static const struct zd_ioreq16 ioreqs[] = {
675 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
676 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
678 /* power control { { CR11, 1 << 6 }, */
680 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
681 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
682 { CR18, 0x0a }, { CR19, 0x48 },
683 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
684 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
685 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
686 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
687 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
688 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
689 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
690 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
691 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
692 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
693 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
694 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
695 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
696 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
697 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
698 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
699 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
700 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
701 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
702 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
703 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
705 { CR95, 0x20 }, /* ZD1211B */
706 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
707 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
708 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
709 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
710 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
711 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
712 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
713 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
714 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
715 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
716 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
717 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
718 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
719 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
720 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
721 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
722 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
723 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
724 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
725 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
726 { CR170, 0xba }, { CR171, 0xba },
727 /* Note: CR204 must lead the CR203 */
735 dev_dbg_f(zd_chip_dev(chip), "\n");
737 r = zd_chip_lock_phy_regs(chip);
741 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
742 t = zd_chip_unlock_phy_regs(chip);
749 static int hw_reset_phy(struct zd_chip *chip)
751 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
752 zd1211_hw_reset_phy(chip);
755 static int zd1211_hw_init_hmac(struct zd_chip *chip)
757 static const struct zd_ioreq32 ioreqs[] = {
758 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT },
759 { CR_RX_THRESHOLD, 0x000c0640 },
762 dev_dbg_f(zd_chip_dev(chip), "\n");
763 ZD_ASSERT(mutex_is_locked(&chip->mutex));
764 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
767 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
769 static const struct zd_ioreq32 ioreqs[] = {
770 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT },
771 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
772 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
773 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
774 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
775 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
776 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
777 { CR_ZD1211B_TXOP, 0x01800824 },
778 { CR_RX_THRESHOLD, 0x000c0eff, },
781 dev_dbg_f(zd_chip_dev(chip), "\n");
782 ZD_ASSERT(mutex_is_locked(&chip->mutex));
783 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
786 static int hw_init_hmac(struct zd_chip *chip)
789 static const struct zd_ioreq32 ioreqs[] = {
790 { CR_ACK_TIMEOUT_EXT, 0x20 },
791 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
792 { CR_SNIFFER_ON, 0 },
793 { CR_RX_FILTER, STA_RX_FILTER },
794 { CR_GROUP_HASH_P1, 0x00 },
795 { CR_GROUP_HASH_P2, 0x80000000 },
797 { CR_ADDA_PWR_DWN, 0x7f },
798 { CR_BCN_PLCP_CFG, 0x00f00401 },
799 { CR_PHY_DELAY, 0x00 },
800 { CR_ACK_TIMEOUT_EXT, 0x80 },
801 { CR_ADDA_PWR_DWN, 0x00 },
802 { CR_ACK_TIME_80211, 0x100 },
803 { CR_RX_PE_DELAY, 0x70 },
804 { CR_PS_CTRL, 0x10000000 },
805 { CR_RTS_CTS_RATE, 0x02030203 },
806 { CR_AFTER_PNP, 0x1 },
807 { CR_WEP_PROTECT, 0x114 },
808 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
809 { CR_CAM_MODE, MODE_AP_WDS},
812 ZD_ASSERT(mutex_is_locked(&chip->mutex));
813 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
817 return zd_chip_is_zd1211b(chip) ?
818 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
827 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
830 static const zd_addr_t aw_pt_bi_addr[] =
831 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
834 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
835 ARRAY_SIZE(aw_pt_bi_addr));
837 memset(s, 0, sizeof(*s));
841 s->atim_wnd_period = values[0];
842 s->pre_tbtt = values[1];
843 s->beacon_interval = values[2];
847 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
849 struct zd_ioreq32 reqs[3];
851 if (s->beacon_interval <= 5)
852 s->beacon_interval = 5;
853 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
854 s->pre_tbtt = s->beacon_interval - 1;
855 if (s->atim_wnd_period >= s->pre_tbtt)
856 s->atim_wnd_period = s->pre_tbtt - 1;
858 reqs[0].addr = CR_ATIM_WND_PERIOD;
859 reqs[0].value = s->atim_wnd_period;
860 reqs[1].addr = CR_PRE_TBTT;
861 reqs[1].value = s->pre_tbtt;
862 reqs[2].addr = CR_BCN_INTERVAL;
863 reqs[2].value = s->beacon_interval;
865 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
869 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
874 ZD_ASSERT(mutex_is_locked(&chip->mutex));
875 r = get_aw_pt_bi(chip, &s);
878 s.beacon_interval = interval;
879 return set_aw_pt_bi(chip, &s);
882 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
886 mutex_lock(&chip->mutex);
887 r = set_beacon_interval(chip, interval);
888 mutex_unlock(&chip->mutex);
892 static int hw_init(struct zd_chip *chip)
896 dev_dbg_f(zd_chip_dev(chip), "\n");
897 ZD_ASSERT(mutex_is_locked(&chip->mutex));
898 r = hw_reset_phy(chip);
902 r = hw_init_hmac(chip);
906 return set_beacon_interval(chip, 100);
909 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
911 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
915 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
916 const char *addr_string)
921 r = zd_ioread32_locked(chip, &value, addr);
923 dev_dbg_f(zd_chip_dev(chip),
924 "error reading %s. Error number %d\n", addr_string, r);
928 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
929 addr_string, (unsigned int)value);
933 static int test_init(struct zd_chip *chip)
937 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
940 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
943 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
946 static void dump_fw_registers(struct zd_chip *chip)
948 const zd_addr_t addr[4] = {
949 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
950 fw_reg_addr(chip, FW_REG_USB_SPEED),
951 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
952 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
958 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
961 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
966 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
967 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
968 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
973 static int print_fw_version(struct zd_chip *chip)
978 r = zd_ioread16_locked(chip, &version,
979 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
983 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
987 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
990 ZD_ASSERT(mutex_is_locked(&chip->mutex));
991 /* This sets the mandatory rates, which only depend from the standard
992 * that the device is supporting. Until further notice we should try
993 * to support 802.11g also for full speed USB.
996 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
998 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
999 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1001 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1004 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1009 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1010 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1011 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1013 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1014 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1015 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1016 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1017 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1019 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1022 int zd_chip_enable_hwint(struct zd_chip *chip)
1026 mutex_lock(&chip->mutex);
1027 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1028 mutex_unlock(&chip->mutex);
1032 static int disable_hwint(struct zd_chip *chip)
1034 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1037 int zd_chip_disable_hwint(struct zd_chip *chip)
1041 mutex_lock(&chip->mutex);
1042 r = disable_hwint(chip);
1043 mutex_unlock(&chip->mutex);
1047 static int read_fw_regs_offset(struct zd_chip *chip)
1051 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1052 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1056 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1057 (u16)chip->fw_regs_base);
1062 /* Read mac address using pre-firmware interface */
1063 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1065 dev_dbg_f(zd_chip_dev(chip), "\n");
1066 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1070 int zd_chip_init_hw(struct zd_chip *chip)
1075 dev_dbg_f(zd_chip_dev(chip), "\n");
1077 mutex_lock(&chip->mutex);
1080 r = test_init(chip);
1084 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1088 r = read_fw_regs_offset(chip);
1092 /* GPI is always disabled, also in the other driver.
1094 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1097 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1100 /* Currently we support IEEE 802.11g for full and high speed USB.
1101 * It might be discussed, whether we should suppport pure b mode for
1104 r = set_mandatory_rates(chip, 1);
1107 /* Disabling interrupts is certainly a smart thing here.
1109 r = disable_hwint(chip);
1112 r = read_pod(chip, &rf_type);
1118 r = zd_rf_init_hw(&chip->rf, rf_type);
1122 r = print_fw_version(chip);
1127 dump_fw_registers(chip);
1128 r = test_init(chip);
1133 r = read_cal_int_tables(chip);
1139 mutex_unlock(&chip->mutex);
1143 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1145 u8 value = chip->pwr_int_values[channel - 1];
1146 return zd_iowrite16_locked(chip, value, CR31);
1149 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1151 u8 value = chip->pwr_cal_values[channel-1];
1152 return zd_iowrite16_locked(chip, value, CR68);
1155 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1157 struct zd_ioreq16 ioreqs[3];
1159 ioreqs[0].addr = CR67;
1160 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1161 ioreqs[1].addr = CR66;
1162 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1163 ioreqs[2].addr = CR65;
1164 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1166 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1169 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1174 if (!zd_rf_should_update_pwr_int(&chip->rf))
1177 r = update_pwr_int(chip, channel);
1180 if (zd_chip_is_zd1211b(chip)) {
1181 static const struct zd_ioreq16 ioreqs[] = {
1187 r = update_ofdm_cal(chip, channel);
1190 r = update_pwr_cal(chip, channel);
1193 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1201 /* The CCK baseband gain can be optionally patched by the EEPROM */
1202 static int patch_cck_gain(struct zd_chip *chip)
1207 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1210 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1211 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1214 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1215 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1218 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1222 mutex_lock(&chip->mutex);
1223 r = zd_chip_lock_phy_regs(chip);
1226 r = zd_rf_set_channel(&chip->rf, channel);
1229 r = update_channel_integration_and_calibration(chip, channel);
1232 r = patch_cck_gain(chip);
1235 r = patch_6m_band_edge(chip, channel);
1238 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1240 t = zd_chip_unlock_phy_regs(chip);
1244 mutex_unlock(&chip->mutex);
1248 u8 zd_chip_get_channel(struct zd_chip *chip)
1252 mutex_lock(&chip->mutex);
1253 channel = chip->rf.channel;
1254 mutex_unlock(&chip->mutex);
1258 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1260 const zd_addr_t a[] = {
1261 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1266 u16 v[ARRAY_SIZE(a)];
1267 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1268 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1273 mutex_lock(&chip->mutex);
1274 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1278 other_led = chip->link_led == LED1 ? LED2 : LED1;
1282 ioreqs[0].value = FW_LINK_OFF;
1283 ioreqs[1].value = v[1] & ~(LED1|LED2);
1285 case ZD_LED_SCANNING:
1286 ioreqs[0].value = FW_LINK_OFF;
1287 ioreqs[1].value = v[1] & ~other_led;
1288 if (get_seconds() % 3 == 0) {
1289 ioreqs[1].value &= ~chip->link_led;
1291 ioreqs[1].value |= chip->link_led;
1294 case ZD_LED_ASSOCIATED:
1295 ioreqs[0].value = FW_LINK_TX;
1296 ioreqs[1].value = v[1] & ~other_led;
1297 ioreqs[1].value |= chip->link_led;
1304 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1305 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1311 mutex_unlock(&chip->mutex);
1315 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1319 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1322 mutex_lock(&chip->mutex);
1323 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1324 mutex_unlock(&chip->mutex);
1328 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1330 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1334 * zd_rx_rate - report zd-rate
1335 * @rx_frame - received frame
1336 * @rx_status - rx_status as given by the device
1338 * This function converts the rate as encoded in the received packet to the
1339 * zd-rate, we are using on other places in the driver.
1341 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1344 if (status->frame_status & ZD_RX_OFDM) {
1345 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1347 switch (zd_cck_plcp_header_signal(rx_frame)) {
1348 case ZD_CCK_PLCP_SIGNAL_1M:
1349 zd_rate = ZD_CCK_RATE_1M;
1351 case ZD_CCK_PLCP_SIGNAL_2M:
1352 zd_rate = ZD_CCK_RATE_2M;
1354 case ZD_CCK_PLCP_SIGNAL_5M5:
1355 zd_rate = ZD_CCK_RATE_5_5M;
1357 case ZD_CCK_PLCP_SIGNAL_11M:
1358 zd_rate = ZD_CCK_RATE_11M;
1368 int zd_chip_switch_radio_on(struct zd_chip *chip)
1372 mutex_lock(&chip->mutex);
1373 r = zd_switch_radio_on(&chip->rf);
1374 mutex_unlock(&chip->mutex);
1378 int zd_chip_switch_radio_off(struct zd_chip *chip)
1382 mutex_lock(&chip->mutex);
1383 r = zd_switch_radio_off(&chip->rf);
1384 mutex_unlock(&chip->mutex);
1388 int zd_chip_enable_int(struct zd_chip *chip)
1392 mutex_lock(&chip->mutex);
1393 r = zd_usb_enable_int(&chip->usb);
1394 mutex_unlock(&chip->mutex);
1398 void zd_chip_disable_int(struct zd_chip *chip)
1400 mutex_lock(&chip->mutex);
1401 zd_usb_disable_int(&chip->usb);
1402 mutex_unlock(&chip->mutex);
1405 int zd_chip_enable_rxtx(struct zd_chip *chip)
1409 mutex_lock(&chip->mutex);
1410 zd_usb_enable_tx(&chip->usb);
1411 r = zd_usb_enable_rx(&chip->usb);
1412 mutex_unlock(&chip->mutex);
1416 void zd_chip_disable_rxtx(struct zd_chip *chip)
1418 mutex_lock(&chip->mutex);
1419 zd_usb_disable_rx(&chip->usb);
1420 zd_usb_disable_tx(&chip->usb);
1421 mutex_unlock(&chip->mutex);
1424 int zd_rfwritev_locked(struct zd_chip *chip,
1425 const u32* values, unsigned int count, u8 bits)
1430 for (i = 0; i < count; i++) {
1431 r = zd_rfwrite_locked(chip, values[i], bits);
1440 * We can optionally program the RF directly through CR regs, if supported by
1441 * the hardware. This is much faster than the older method.
1443 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1445 struct zd_ioreq16 ioreqs[] = {
1446 { CR244, (value >> 16) & 0xff },
1447 { CR243, (value >> 8) & 0xff },
1448 { CR242, value & 0xff },
1450 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1451 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1454 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1455 const u32 *values, unsigned int count)
1460 for (i = 0; i < count; i++) {
1461 r = zd_rfwrite_cr_locked(chip, values[i]);
1469 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1470 struct zd_mc_hash *hash)
1472 struct zd_ioreq32 ioreqs[] = {
1473 { CR_GROUP_HASH_P1, hash->low },
1474 { CR_GROUP_HASH_P2, hash->high },
1477 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1480 u64 zd_chip_get_tsf(struct zd_chip *chip)
1483 static const zd_addr_t aw_pt_bi_addr[] =
1484 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1488 mutex_lock(&chip->mutex);
1489 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1490 ARRAY_SIZE(aw_pt_bi_addr));
1491 mutex_unlock(&chip->mutex);
1496 tsf = (tsf << 32) | values[0];