1 /* ZD1211 USB-WLAN driver for Linux
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
31 #include "zd_ieee80211.h"
35 void zd_chip_init(struct zd_chip *chip,
36 struct ieee80211_hw *hw,
37 struct usb_interface *intf)
39 memset(chip, 0, sizeof(*chip));
40 mutex_init(&chip->mutex);
41 zd_usb_init(&chip->usb, hw, intf);
42 zd_rf_init(&chip->rf);
45 void zd_chip_clear(struct zd_chip *chip)
47 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
48 zd_usb_clear(&chip->usb);
49 zd_rf_clear(&chip->rf);
50 mutex_destroy(&chip->mutex);
51 ZD_MEMCLEAR(chip, sizeof(*chip));
54 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
56 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
57 return scnprintf(buffer, size, "%02x-%02x-%02x",
58 addr[0], addr[1], addr[2]);
61 /* Prints an identifier line, which will support debugging. */
62 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
66 i = scnprintf(buffer, size, "zd1211%s chip ",
67 zd_chip_is_zd1211b(chip) ? "b" : "");
68 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += scnprint_mac_oui(chip, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " ");
72 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
73 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
74 chip->patch_cck_gain ? 'g' : '-',
75 chip->patch_cr157 ? '7' : '-',
76 chip->patch_6m_band_edge ? '6' : '-',
77 chip->new_phy_layout ? 'N' : '-',
78 chip->al2230s_bit ? 'S' : '-');
82 static void print_id(struct zd_chip *chip)
86 scnprint_id(chip, buffer, sizeof(buffer));
87 buffer[sizeof(buffer)-1] = 0;
88 dev_info(zd_chip_dev(chip), "%s\n", buffer);
91 static zd_addr_t inc_addr(zd_addr_t addr)
94 /* Control registers use byte addressing, but everything else uses word
96 if ((a & 0xf000) == CR_START)
103 /* Read a variable number of 32-bit values. Parameter count is not allowed to
104 * exceed USB_MAX_IOREAD32_COUNT.
106 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
113 unsigned int count16;
115 if (count > USB_MAX_IOREAD32_COUNT)
118 /* Allocate a single memory block for values and addresses. */
120 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
123 dev_dbg_f(zd_chip_dev(chip),
124 "error ENOMEM in allocation of a16\n");
128 v16 = (u16 *)(a16 + count16);
130 for (i = 0; i < count; i++) {
132 /* We read the high word always first. */
133 a16[j] = inc_addr(addr[i]);
137 r = zd_ioread16v_locked(chip, v16, a16, count16);
139 dev_dbg_f(zd_chip_dev(chip),
140 "error: zd_ioread16v_locked. Error number %d\n", r);
144 for (i = 0; i < count; i++) {
146 values[i] = (v16[j] << 16) | v16[j+1];
154 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
158 struct zd_ioreq16 *ioreqs16;
159 unsigned int count16;
161 ZD_ASSERT(mutex_is_locked(&chip->mutex));
165 if (count > USB_MAX_IOWRITE32_COUNT)
168 /* Allocate a single memory block for values and addresses. */
170 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
173 dev_dbg_f(zd_chip_dev(chip),
174 "error %d in ioreqs16 allocation\n", r);
178 for (i = 0; i < count; i++) {
180 /* We write the high word always first. */
181 ioreqs16[j].value = ioreqs[i].value >> 16;
182 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
183 ioreqs16[j+1].value = ioreqs[i].value;
184 ioreqs16[j+1].addr = ioreqs[i].addr;
187 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
190 dev_dbg_f(zd_chip_dev(chip),
191 "error %d in zd_usb_write16v\n", r);
199 int zd_iowrite16a_locked(struct zd_chip *chip,
200 const struct zd_ioreq16 *ioreqs, unsigned int count)
203 unsigned int i, j, t, max;
205 ZD_ASSERT(mutex_is_locked(&chip->mutex));
206 for (i = 0; i < count; i += j + t) {
209 if (max > USB_MAX_IOWRITE16_COUNT)
210 max = USB_MAX_IOWRITE16_COUNT;
211 for (j = 0; j < max; j++) {
212 if (!ioreqs[i+j].addr) {
218 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
220 dev_dbg_f(zd_chip_dev(chip),
221 "error zd_usb_iowrite16v. Error number %d\n",
230 /* Writes a variable number of 32 bit registers. The functions will split
231 * that in several USB requests. A split can be forced by inserting an IO
232 * request with an zero address field.
234 int zd_iowrite32a_locked(struct zd_chip *chip,
235 const struct zd_ioreq32 *ioreqs, unsigned int count)
238 unsigned int i, j, t, max;
240 for (i = 0; i < count; i += j + t) {
243 if (max > USB_MAX_IOWRITE32_COUNT)
244 max = USB_MAX_IOWRITE32_COUNT;
245 for (j = 0; j < max; j++) {
246 if (!ioreqs[i+j].addr) {
252 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
254 dev_dbg_f(zd_chip_dev(chip),
255 "error _zd_iowrite32v_locked."
256 " Error number %d\n", r);
264 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
268 mutex_lock(&chip->mutex);
269 r = zd_ioread16_locked(chip, value, addr);
270 mutex_unlock(&chip->mutex);
274 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
278 mutex_lock(&chip->mutex);
279 r = zd_ioread32_locked(chip, value, addr);
280 mutex_unlock(&chip->mutex);
284 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
288 mutex_lock(&chip->mutex);
289 r = zd_iowrite16_locked(chip, value, addr);
290 mutex_unlock(&chip->mutex);
294 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
298 mutex_lock(&chip->mutex);
299 r = zd_iowrite32_locked(chip, value, addr);
300 mutex_unlock(&chip->mutex);
304 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
305 u32 *values, unsigned int count)
309 mutex_lock(&chip->mutex);
310 r = zd_ioread32v_locked(chip, values, addresses, count);
311 mutex_unlock(&chip->mutex);
315 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
320 mutex_lock(&chip->mutex);
321 r = zd_iowrite32a_locked(chip, ioreqs, count);
322 mutex_unlock(&chip->mutex);
326 static int read_pod(struct zd_chip *chip, u8 *rf_type)
331 ZD_ASSERT(mutex_is_locked(&chip->mutex));
332 r = zd_ioread32_locked(chip, &value, E2P_POD);
335 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
337 /* FIXME: AL2230 handling (Bit 7 in POD) */
338 *rf_type = value & 0x0f;
339 chip->pa_type = (value >> 16) & 0x0f;
340 chip->patch_cck_gain = (value >> 8) & 0x1;
341 chip->patch_cr157 = (value >> 13) & 0x1;
342 chip->patch_6m_band_edge = (value >> 21) & 0x1;
343 chip->new_phy_layout = (value >> 31) & 0x1;
344 chip->al2230s_bit = (value >> 7) & 0x1;
345 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
346 chip->supports_tx_led = 1;
347 if (value & (1 << 24)) { /* LED scenario */
348 if (value & (1 << 29))
349 chip->supports_tx_led = 0;
352 dev_dbg_f(zd_chip_dev(chip),
353 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
354 "patch 6M %d new PHY %d link LED%d tx led %d\n",
355 zd_rf_name(*rf_type), *rf_type,
356 chip->pa_type, chip->patch_cck_gain,
357 chip->patch_cr157, chip->patch_6m_band_edge,
358 chip->new_phy_layout,
359 chip->link_led == LED1 ? 1 : 2,
360 chip->supports_tx_led);
365 chip->patch_cck_gain = 0;
366 chip->patch_cr157 = 0;
367 chip->patch_6m_band_edge = 0;
368 chip->new_phy_layout = 0;
372 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
373 * CR_MAC_ADDR_P2 must be overwritten
375 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
378 struct zd_ioreq32 reqs[2] = {
379 [0] = { .addr = CR_MAC_ADDR_P1 },
380 [1] = { .addr = CR_MAC_ADDR_P2 },
382 DECLARE_MAC_BUF(mac);
385 reqs[0].value = (mac_addr[3] << 24)
386 | (mac_addr[2] << 16)
389 reqs[1].value = (mac_addr[5] << 8)
391 dev_dbg_f(zd_chip_dev(chip),
392 "mac addr %s\n", print_mac(mac, mac_addr));
394 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
397 mutex_lock(&chip->mutex);
398 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
399 mutex_unlock(&chip->mutex);
403 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
408 mutex_lock(&chip->mutex);
409 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
410 mutex_unlock(&chip->mutex);
414 *regdomain = value >> 16;
415 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
420 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
421 zd_addr_t e2p_addr, u32 guard)
427 ZD_ASSERT(mutex_is_locked(&chip->mutex));
429 r = zd_ioread32_locked(chip, &v,
430 (zd_addr_t)((u16)e2p_addr+i/2));
436 values[i++] = v >> 8;
437 values[i++] = v >> 16;
438 values[i++] = v >> 24;
441 for (;i < count; i++)
442 values[i] = v >> (8*(i%3));
447 static int read_pwr_cal_values(struct zd_chip *chip)
449 return read_values(chip, chip->pwr_cal_values,
450 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
454 static int read_pwr_int_values(struct zd_chip *chip)
456 return read_values(chip, chip->pwr_int_values,
457 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
461 static int read_ofdm_cal_values(struct zd_chip *chip)
465 static const zd_addr_t addresses[] = {
471 for (i = 0; i < 3; i++) {
472 r = read_values(chip, chip->ofdm_cal_values[i],
473 E2P_CHANNEL_COUNT, addresses[i], 0);
480 static int read_cal_int_tables(struct zd_chip *chip)
484 r = read_pwr_cal_values(chip);
487 r = read_pwr_int_values(chip);
490 r = read_ofdm_cal_values(chip);
496 /* phy means physical registers */
497 int zd_chip_lock_phy_regs(struct zd_chip *chip)
502 ZD_ASSERT(mutex_is_locked(&chip->mutex));
503 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
505 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
509 tmp &= ~UNLOCK_PHY_REGS;
511 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
513 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
517 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
522 ZD_ASSERT(mutex_is_locked(&chip->mutex));
523 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
525 dev_err(zd_chip_dev(chip),
526 "error ioread32(CR_REG1): %d\n", r);
530 tmp |= UNLOCK_PHY_REGS;
532 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
534 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
538 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
539 static int patch_cr157(struct zd_chip *chip)
544 if (!chip->patch_cr157)
547 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
551 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
552 return zd_iowrite32_locked(chip, value >> 8, CR157);
556 * 6M band edge can be optionally overwritten for certain RF's
557 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
558 * bit (for AL2230, AL2230S)
560 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
562 ZD_ASSERT(mutex_is_locked(&chip->mutex));
563 if (!chip->patch_6m_band_edge)
566 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
569 /* Generic implementation of 6M band edge patching, used by most RFs via
570 * zd_rf_generic_patch_6m() */
571 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
573 struct zd_ioreq16 ioreqs[] = {
574 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
578 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
579 if (channel == 1 || channel == 11)
580 ioreqs[0].value = 0x12;
582 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
583 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
586 static int zd1211_hw_reset_phy(struct zd_chip *chip)
588 static const struct zd_ioreq16 ioreqs[] = {
589 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
590 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
591 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
592 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
593 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
594 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
595 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
596 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
597 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
598 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
599 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
600 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
601 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
602 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
603 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
604 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
605 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
606 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
607 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
608 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
609 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
610 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
611 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
612 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
613 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
614 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
615 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
616 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
617 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
618 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
619 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
620 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
621 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
623 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
624 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
625 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
626 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
627 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
628 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
629 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
630 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
631 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
632 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
633 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
634 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
635 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
636 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
637 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
638 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
639 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
640 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
641 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
642 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
643 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
644 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
645 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
646 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
647 { CR170, 0xba }, { CR171, 0xba },
648 /* Note: CR204 must lead the CR203 */
656 dev_dbg_f(zd_chip_dev(chip), "\n");
658 r = zd_chip_lock_phy_regs(chip);
662 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
666 r = patch_cr157(chip);
668 t = zd_chip_unlock_phy_regs(chip);
675 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
677 static const struct zd_ioreq16 ioreqs[] = {
678 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
679 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
681 /* power control { { CR11, 1 << 6 }, */
683 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
684 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
685 { CR18, 0x0a }, { CR19, 0x48 },
686 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
687 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
688 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
689 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
690 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
691 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
692 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
693 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
694 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
695 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
696 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
697 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
698 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
699 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
700 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
701 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
702 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
703 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
704 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
705 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
706 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
708 { CR95, 0x20 }, /* ZD1211B */
709 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
710 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
711 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
712 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
713 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
714 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
715 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
716 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
717 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
718 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
719 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
720 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
721 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
722 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
723 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
724 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
725 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
726 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
727 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
728 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
729 { CR170, 0xba }, { CR171, 0xba },
730 /* Note: CR204 must lead the CR203 */
738 dev_dbg_f(zd_chip_dev(chip), "\n");
740 r = zd_chip_lock_phy_regs(chip);
744 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
745 t = zd_chip_unlock_phy_regs(chip);
752 static int hw_reset_phy(struct zd_chip *chip)
754 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
755 zd1211_hw_reset_phy(chip);
758 static int zd1211_hw_init_hmac(struct zd_chip *chip)
760 static const struct zd_ioreq32 ioreqs[] = {
761 { CR_ZD1211_RETRY_MAX, 0x2 },
762 { CR_RX_THRESHOLD, 0x000c0640 },
765 dev_dbg_f(zd_chip_dev(chip), "\n");
766 ZD_ASSERT(mutex_is_locked(&chip->mutex));
767 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
770 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
772 static const struct zd_ioreq32 ioreqs[] = {
773 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
774 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
775 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
776 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
777 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
778 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
779 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
780 { CR_ZD1211B_TXOP, 0x01800824 },
781 { CR_RX_THRESHOLD, 0x000c0eff, },
784 dev_dbg_f(zd_chip_dev(chip), "\n");
785 ZD_ASSERT(mutex_is_locked(&chip->mutex));
786 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
789 static int hw_init_hmac(struct zd_chip *chip)
792 static const struct zd_ioreq32 ioreqs[] = {
793 { CR_ACK_TIMEOUT_EXT, 0x20 },
794 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
795 { CR_SNIFFER_ON, 0 },
796 { CR_RX_FILTER, STA_RX_FILTER },
797 { CR_GROUP_HASH_P1, 0x00 },
798 { CR_GROUP_HASH_P2, 0x80000000 },
800 { CR_ADDA_PWR_DWN, 0x7f },
801 { CR_BCN_PLCP_CFG, 0x00f00401 },
802 { CR_PHY_DELAY, 0x00 },
803 { CR_ACK_TIMEOUT_EXT, 0x80 },
804 { CR_ADDA_PWR_DWN, 0x00 },
805 { CR_ACK_TIME_80211, 0x100 },
806 { CR_RX_PE_DELAY, 0x70 },
807 { CR_PS_CTRL, 0x10000000 },
808 { CR_RTS_CTS_RATE, 0x02030203 },
809 { CR_AFTER_PNP, 0x1 },
810 { CR_WEP_PROTECT, 0x114 },
811 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
814 ZD_ASSERT(mutex_is_locked(&chip->mutex));
815 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
819 return zd_chip_is_zd1211b(chip) ?
820 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
829 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
832 static const zd_addr_t aw_pt_bi_addr[] =
833 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
836 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
837 ARRAY_SIZE(aw_pt_bi_addr));
839 memset(s, 0, sizeof(*s));
843 s->atim_wnd_period = values[0];
844 s->pre_tbtt = values[1];
845 s->beacon_interval = values[2];
849 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
851 struct zd_ioreq32 reqs[3];
853 if (s->beacon_interval <= 5)
854 s->beacon_interval = 5;
855 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
856 s->pre_tbtt = s->beacon_interval - 1;
857 if (s->atim_wnd_period >= s->pre_tbtt)
858 s->atim_wnd_period = s->pre_tbtt - 1;
860 reqs[0].addr = CR_ATIM_WND_PERIOD;
861 reqs[0].value = s->atim_wnd_period;
862 reqs[1].addr = CR_PRE_TBTT;
863 reqs[1].value = s->pre_tbtt;
864 reqs[2].addr = CR_BCN_INTERVAL;
865 reqs[2].value = s->beacon_interval;
867 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
871 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
876 ZD_ASSERT(mutex_is_locked(&chip->mutex));
877 r = get_aw_pt_bi(chip, &s);
880 s.beacon_interval = interval;
881 return set_aw_pt_bi(chip, &s);
884 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
888 mutex_lock(&chip->mutex);
889 r = set_beacon_interval(chip, interval);
890 mutex_unlock(&chip->mutex);
894 static int hw_init(struct zd_chip *chip)
898 dev_dbg_f(zd_chip_dev(chip), "\n");
899 ZD_ASSERT(mutex_is_locked(&chip->mutex));
900 r = hw_reset_phy(chip);
904 r = hw_init_hmac(chip);
908 return set_beacon_interval(chip, 100);
911 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
913 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
917 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
918 const char *addr_string)
923 r = zd_ioread32_locked(chip, &value, addr);
925 dev_dbg_f(zd_chip_dev(chip),
926 "error reading %s. Error number %d\n", addr_string, r);
930 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
931 addr_string, (unsigned int)value);
935 static int test_init(struct zd_chip *chip)
939 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
942 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
945 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
948 static void dump_fw_registers(struct zd_chip *chip)
950 const zd_addr_t addr[4] = {
951 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
952 fw_reg_addr(chip, FW_REG_USB_SPEED),
953 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
954 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
960 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
963 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
968 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
970 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
971 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
975 static int print_fw_version(struct zd_chip *chip)
980 r = zd_ioread16_locked(chip, &version,
981 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
985 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
989 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
992 ZD_ASSERT(mutex_is_locked(&chip->mutex));
993 /* This sets the mandatory rates, which only depend from the standard
994 * that the device is supporting. Until further notice we should try
995 * to support 802.11g also for full speed USB.
998 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1000 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1001 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1003 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1006 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1011 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1012 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1013 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1015 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1016 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1017 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1018 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1019 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1021 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1024 int zd_chip_enable_hwint(struct zd_chip *chip)
1028 mutex_lock(&chip->mutex);
1029 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1030 mutex_unlock(&chip->mutex);
1034 static int disable_hwint(struct zd_chip *chip)
1036 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1039 int zd_chip_disable_hwint(struct zd_chip *chip)
1043 mutex_lock(&chip->mutex);
1044 r = disable_hwint(chip);
1045 mutex_unlock(&chip->mutex);
1049 static int read_fw_regs_offset(struct zd_chip *chip)
1053 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1054 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1058 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1059 (u16)chip->fw_regs_base);
1064 /* Read mac address using pre-firmware interface */
1065 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1067 dev_dbg_f(zd_chip_dev(chip), "\n");
1068 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1072 int zd_chip_init_hw(struct zd_chip *chip)
1077 dev_dbg_f(zd_chip_dev(chip), "\n");
1079 mutex_lock(&chip->mutex);
1082 r = test_init(chip);
1086 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1090 r = read_fw_regs_offset(chip);
1094 /* GPI is always disabled, also in the other driver.
1096 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1099 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1102 /* Currently we support IEEE 802.11g for full and high speed USB.
1103 * It might be discussed, whether we should suppport pure b mode for
1106 r = set_mandatory_rates(chip, 1);
1109 /* Disabling interrupts is certainly a smart thing here.
1111 r = disable_hwint(chip);
1114 r = read_pod(chip, &rf_type);
1120 r = zd_rf_init_hw(&chip->rf, rf_type);
1124 r = print_fw_version(chip);
1129 dump_fw_registers(chip);
1130 r = test_init(chip);
1135 r = read_cal_int_tables(chip);
1141 mutex_unlock(&chip->mutex);
1145 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1147 u8 value = chip->pwr_int_values[channel - 1];
1148 return zd_iowrite16_locked(chip, value, CR31);
1151 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1153 u8 value = chip->pwr_cal_values[channel-1];
1154 return zd_iowrite16_locked(chip, value, CR68);
1157 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1159 struct zd_ioreq16 ioreqs[3];
1161 ioreqs[0].addr = CR67;
1162 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1163 ioreqs[1].addr = CR66;
1164 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1165 ioreqs[2].addr = CR65;
1166 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1168 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1171 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1176 if (!zd_rf_should_update_pwr_int(&chip->rf))
1179 r = update_pwr_int(chip, channel);
1182 if (zd_chip_is_zd1211b(chip)) {
1183 static const struct zd_ioreq16 ioreqs[] = {
1189 r = update_ofdm_cal(chip, channel);
1192 r = update_pwr_cal(chip, channel);
1195 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1203 /* The CCK baseband gain can be optionally patched by the EEPROM */
1204 static int patch_cck_gain(struct zd_chip *chip)
1209 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1212 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1213 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1216 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1217 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1220 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1224 mutex_lock(&chip->mutex);
1225 r = zd_chip_lock_phy_regs(chip);
1228 r = zd_rf_set_channel(&chip->rf, channel);
1231 r = update_channel_integration_and_calibration(chip, channel);
1234 r = patch_cck_gain(chip);
1237 r = patch_6m_band_edge(chip, channel);
1240 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1242 t = zd_chip_unlock_phy_regs(chip);
1246 mutex_unlock(&chip->mutex);
1250 u8 zd_chip_get_channel(struct zd_chip *chip)
1254 mutex_lock(&chip->mutex);
1255 channel = chip->rf.channel;
1256 mutex_unlock(&chip->mutex);
1260 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1262 const zd_addr_t a[] = {
1263 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1268 u16 v[ARRAY_SIZE(a)];
1269 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1270 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1275 mutex_lock(&chip->mutex);
1276 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1280 other_led = chip->link_led == LED1 ? LED2 : LED1;
1284 ioreqs[0].value = FW_LINK_OFF;
1285 ioreqs[1].value = v[1] & ~(LED1|LED2);
1288 ioreqs[0].value = FW_LINK_OFF;
1289 ioreqs[1].value = v[1] & ~other_led;
1290 if (get_seconds() % 3 == 0) {
1291 ioreqs[1].value &= ~chip->link_led;
1293 ioreqs[1].value |= chip->link_led;
1296 case LED_ASSOCIATED:
1297 ioreqs[0].value = FW_LINK_TX;
1298 ioreqs[1].value = v[1] & ~other_led;
1299 ioreqs[1].value |= chip->link_led;
1306 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1307 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1313 mutex_unlock(&chip->mutex);
1317 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1321 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1324 mutex_lock(&chip->mutex);
1325 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1326 mutex_unlock(&chip->mutex);
1330 static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size)
1332 static const u16 constants[] = {
1333 715, 655, 585, 540, 470, 410, 360, 315,
1334 270, 235, 205, 175, 150, 125, 105, 85,
1341 /* It seems that their quality parameter is somehow per signal
1342 * and is now transferred per bit.
1345 case ZD_OFDM_RATE_6M:
1346 case ZD_OFDM_RATE_12M:
1347 case ZD_OFDM_RATE_24M:
1350 case ZD_OFDM_RATE_9M:
1351 case ZD_OFDM_RATE_18M:
1352 case ZD_OFDM_RATE_36M:
1353 case ZD_OFDM_RATE_54M:
1357 case ZD_OFDM_RATE_48M:
1365 x = (10000 * status_quality)/size;
1366 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1367 if (x > constants[i])
1372 case ZD_OFDM_RATE_6M:
1373 case ZD_OFDM_RATE_9M:
1376 case ZD_OFDM_RATE_12M:
1377 case ZD_OFDM_RATE_18M:
1380 case ZD_OFDM_RATE_24M:
1381 case ZD_OFDM_RATE_36M:
1384 case ZD_OFDM_RATE_48M:
1385 case ZD_OFDM_RATE_54M:
1395 static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size)
1399 r = ofdm_qual_db(status_quality, zd_rate, size);
1405 return r <= 100 ? r : 100;
1408 static unsigned int log10times100(unsigned int x)
1410 static const u8 log10[] = {
1412 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1413 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1414 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1415 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1416 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1417 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1418 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1419 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1420 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1421 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1422 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1423 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1424 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1425 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1426 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1427 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1428 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1429 223, 223, 223, 224, 224, 224, 224,
1432 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1436 MAX_CCK_EVM_DB = 45,
1439 static int cck_evm_db(u8 status_quality)
1441 return (20 * log10times100(status_quality)) / 100;
1444 static int cck_snr_db(u8 status_quality)
1446 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1451 static int cck_qual_percent(u8 status_quality)
1455 r = cck_snr_db(status_quality);
1457 return r <= 100 ? r : 100;
1460 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1462 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1465 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1466 const struct rx_status *status)
1468 return (status->frame_status&ZD_RX_OFDM) ?
1469 ofdm_qual_percent(status->signal_quality_ofdm,
1470 zd_rate_from_ofdm_plcp_header(rx_frame),
1472 cck_qual_percent(status->signal_quality_cck);
1476 * zd_rx_rate - report zd-rate
1477 * @rx_frame - received frame
1478 * @rx_status - rx_status as given by the device
1480 * This function converts the rate as encoded in the received packet to the
1481 * zd-rate, we are using on other places in the driver.
1483 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1486 if (status->frame_status & ZD_RX_OFDM) {
1487 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1489 switch (zd_cck_plcp_header_signal(rx_frame)) {
1490 case ZD_CCK_PLCP_SIGNAL_1M:
1491 zd_rate = ZD_CCK_RATE_1M;
1493 case ZD_CCK_PLCP_SIGNAL_2M:
1494 zd_rate = ZD_CCK_RATE_2M;
1496 case ZD_CCK_PLCP_SIGNAL_5M5:
1497 zd_rate = ZD_CCK_RATE_5_5M;
1499 case ZD_CCK_PLCP_SIGNAL_11M:
1500 zd_rate = ZD_CCK_RATE_11M;
1510 int zd_chip_switch_radio_on(struct zd_chip *chip)
1514 mutex_lock(&chip->mutex);
1515 r = zd_switch_radio_on(&chip->rf);
1516 mutex_unlock(&chip->mutex);
1520 int zd_chip_switch_radio_off(struct zd_chip *chip)
1524 mutex_lock(&chip->mutex);
1525 r = zd_switch_radio_off(&chip->rf);
1526 mutex_unlock(&chip->mutex);
1530 int zd_chip_enable_int(struct zd_chip *chip)
1534 mutex_lock(&chip->mutex);
1535 r = zd_usb_enable_int(&chip->usb);
1536 mutex_unlock(&chip->mutex);
1540 void zd_chip_disable_int(struct zd_chip *chip)
1542 mutex_lock(&chip->mutex);
1543 zd_usb_disable_int(&chip->usb);
1544 mutex_unlock(&chip->mutex);
1547 int zd_chip_enable_rxtx(struct zd_chip *chip)
1551 mutex_lock(&chip->mutex);
1552 zd_usb_enable_tx(&chip->usb);
1553 r = zd_usb_enable_rx(&chip->usb);
1554 mutex_unlock(&chip->mutex);
1558 void zd_chip_disable_rxtx(struct zd_chip *chip)
1560 mutex_lock(&chip->mutex);
1561 zd_usb_disable_rx(&chip->usb);
1562 zd_usb_disable_tx(&chip->usb);
1563 mutex_unlock(&chip->mutex);
1566 int zd_rfwritev_locked(struct zd_chip *chip,
1567 const u32* values, unsigned int count, u8 bits)
1572 for (i = 0; i < count; i++) {
1573 r = zd_rfwrite_locked(chip, values[i], bits);
1582 * We can optionally program the RF directly through CR regs, if supported by
1583 * the hardware. This is much faster than the older method.
1585 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1587 struct zd_ioreq16 ioreqs[] = {
1588 { CR244, (value >> 16) & 0xff },
1589 { CR243, (value >> 8) & 0xff },
1590 { CR242, value & 0xff },
1592 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1593 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1596 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1597 const u32 *values, unsigned int count)
1602 for (i = 0; i < count; i++) {
1603 r = zd_rfwrite_cr_locked(chip, values[i]);
1611 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1612 struct zd_mc_hash *hash)
1614 struct zd_ioreq32 ioreqs[] = {
1615 { CR_GROUP_HASH_P1, hash->low },
1616 { CR_GROUP_HASH_P2, hash->high },
1619 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));