1 /* ZD1211 USB-WLAN driver for Linux
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
35 void zd_chip_init(struct zd_chip *chip,
36 struct ieee80211_hw *hw,
37 struct usb_interface *intf)
39 memset(chip, 0, sizeof(*chip));
40 mutex_init(&chip->mutex);
41 zd_usb_init(&chip->usb, hw, intf);
42 zd_rf_init(&chip->rf);
45 void zd_chip_clear(struct zd_chip *chip)
47 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
48 zd_usb_clear(&chip->usb);
49 zd_rf_clear(&chip->rf);
50 mutex_destroy(&chip->mutex);
51 ZD_MEMCLEAR(chip, sizeof(*chip));
54 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
56 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
57 return scnprintf(buffer, size, "%02x-%02x-%02x",
58 addr[0], addr[1], addr[2]);
61 /* Prints an identifier line, which will support debugging. */
62 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
66 i = scnprintf(buffer, size, "zd1211%s chip ",
67 zd_chip_is_zd1211b(chip) ? "b" : "");
68 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += scnprint_mac_oui(chip, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " ");
72 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
73 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
74 chip->patch_cck_gain ? 'g' : '-',
75 chip->patch_cr157 ? '7' : '-',
76 chip->patch_6m_band_edge ? '6' : '-',
77 chip->new_phy_layout ? 'N' : '-',
78 chip->al2230s_bit ? 'S' : '-');
82 static void print_id(struct zd_chip *chip)
86 scnprint_id(chip, buffer, sizeof(buffer));
87 buffer[sizeof(buffer)-1] = 0;
88 dev_info(zd_chip_dev(chip), "%s\n", buffer);
91 static zd_addr_t inc_addr(zd_addr_t addr)
94 /* Control registers use byte addressing, but everything else uses word
96 if ((a & 0xf000) == CR_START)
103 /* Read a variable number of 32-bit values. Parameter count is not allowed to
104 * exceed USB_MAX_IOREAD32_COUNT.
106 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
113 unsigned int count16;
115 if (count > USB_MAX_IOREAD32_COUNT)
118 /* Allocate a single memory block for values and addresses. */
120 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
123 dev_dbg_f(zd_chip_dev(chip),
124 "error ENOMEM in allocation of a16\n");
128 v16 = (u16 *)(a16 + count16);
130 for (i = 0; i < count; i++) {
132 /* We read the high word always first. */
133 a16[j] = inc_addr(addr[i]);
137 r = zd_ioread16v_locked(chip, v16, a16, count16);
139 dev_dbg_f(zd_chip_dev(chip),
140 "error: zd_ioread16v_locked. Error number %d\n", r);
144 for (i = 0; i < count; i++) {
146 values[i] = (v16[j] << 16) | v16[j+1];
154 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
158 struct zd_ioreq16 *ioreqs16;
159 unsigned int count16;
161 ZD_ASSERT(mutex_is_locked(&chip->mutex));
165 if (count > USB_MAX_IOWRITE32_COUNT)
168 /* Allocate a single memory block for values and addresses. */
170 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
173 dev_dbg_f(zd_chip_dev(chip),
174 "error %d in ioreqs16 allocation\n", r);
178 for (i = 0; i < count; i++) {
180 /* We write the high word always first. */
181 ioreqs16[j].value = ioreqs[i].value >> 16;
182 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
183 ioreqs16[j+1].value = ioreqs[i].value;
184 ioreqs16[j+1].addr = ioreqs[i].addr;
187 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
190 dev_dbg_f(zd_chip_dev(chip),
191 "error %d in zd_usb_write16v\n", r);
199 int zd_iowrite16a_locked(struct zd_chip *chip,
200 const struct zd_ioreq16 *ioreqs, unsigned int count)
203 unsigned int i, j, t, max;
205 ZD_ASSERT(mutex_is_locked(&chip->mutex));
206 for (i = 0; i < count; i += j + t) {
209 if (max > USB_MAX_IOWRITE16_COUNT)
210 max = USB_MAX_IOWRITE16_COUNT;
211 for (j = 0; j < max; j++) {
212 if (!ioreqs[i+j].addr) {
218 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
220 dev_dbg_f(zd_chip_dev(chip),
221 "error zd_usb_iowrite16v. Error number %d\n",
230 /* Writes a variable number of 32 bit registers. The functions will split
231 * that in several USB requests. A split can be forced by inserting an IO
232 * request with an zero address field.
234 int zd_iowrite32a_locked(struct zd_chip *chip,
235 const struct zd_ioreq32 *ioreqs, unsigned int count)
238 unsigned int i, j, t, max;
240 for (i = 0; i < count; i += j + t) {
243 if (max > USB_MAX_IOWRITE32_COUNT)
244 max = USB_MAX_IOWRITE32_COUNT;
245 for (j = 0; j < max; j++) {
246 if (!ioreqs[i+j].addr) {
252 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
254 dev_dbg_f(zd_chip_dev(chip),
255 "error _zd_iowrite32v_locked."
256 " Error number %d\n", r);
264 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
268 mutex_lock(&chip->mutex);
269 r = zd_ioread16_locked(chip, value, addr);
270 mutex_unlock(&chip->mutex);
274 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
278 mutex_lock(&chip->mutex);
279 r = zd_ioread32_locked(chip, value, addr);
280 mutex_unlock(&chip->mutex);
284 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
288 mutex_lock(&chip->mutex);
289 r = zd_iowrite16_locked(chip, value, addr);
290 mutex_unlock(&chip->mutex);
294 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
298 mutex_lock(&chip->mutex);
299 r = zd_iowrite32_locked(chip, value, addr);
300 mutex_unlock(&chip->mutex);
304 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
305 u32 *values, unsigned int count)
309 mutex_lock(&chip->mutex);
310 r = zd_ioread32v_locked(chip, values, addresses, count);
311 mutex_unlock(&chip->mutex);
315 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
320 mutex_lock(&chip->mutex);
321 r = zd_iowrite32a_locked(chip, ioreqs, count);
322 mutex_unlock(&chip->mutex);
326 static int read_pod(struct zd_chip *chip, u8 *rf_type)
331 ZD_ASSERT(mutex_is_locked(&chip->mutex));
332 r = zd_ioread32_locked(chip, &value, E2P_POD);
335 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
337 /* FIXME: AL2230 handling (Bit 7 in POD) */
338 *rf_type = value & 0x0f;
339 chip->pa_type = (value >> 16) & 0x0f;
340 chip->patch_cck_gain = (value >> 8) & 0x1;
341 chip->patch_cr157 = (value >> 13) & 0x1;
342 chip->patch_6m_band_edge = (value >> 21) & 0x1;
343 chip->new_phy_layout = (value >> 31) & 0x1;
344 chip->al2230s_bit = (value >> 7) & 0x1;
345 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
346 chip->supports_tx_led = 1;
347 if (value & (1 << 24)) { /* LED scenario */
348 if (value & (1 << 29))
349 chip->supports_tx_led = 0;
352 dev_dbg_f(zd_chip_dev(chip),
353 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
354 "patch 6M %d new PHY %d link LED%d tx led %d\n",
355 zd_rf_name(*rf_type), *rf_type,
356 chip->pa_type, chip->patch_cck_gain,
357 chip->patch_cr157, chip->patch_6m_band_edge,
358 chip->new_phy_layout,
359 chip->link_led == LED1 ? 1 : 2,
360 chip->supports_tx_led);
365 chip->patch_cck_gain = 0;
366 chip->patch_cr157 = 0;
367 chip->patch_6m_band_edge = 0;
368 chip->new_phy_layout = 0;
372 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
373 * CR_MAC_ADDR_P2 must be overwritten
375 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
378 struct zd_ioreq32 reqs[2] = {
379 [0] = { .addr = CR_MAC_ADDR_P1 },
380 [1] = { .addr = CR_MAC_ADDR_P2 },
384 reqs[0].value = (mac_addr[3] << 24)
385 | (mac_addr[2] << 16)
388 reqs[1].value = (mac_addr[5] << 8)
390 dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr);
392 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
395 mutex_lock(&chip->mutex);
396 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
397 mutex_unlock(&chip->mutex);
401 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
406 mutex_lock(&chip->mutex);
407 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
408 mutex_unlock(&chip->mutex);
412 *regdomain = value >> 16;
413 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
418 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
419 zd_addr_t e2p_addr, u32 guard)
425 ZD_ASSERT(mutex_is_locked(&chip->mutex));
427 r = zd_ioread32_locked(chip, &v,
428 (zd_addr_t)((u16)e2p_addr+i/2));
434 values[i++] = v >> 8;
435 values[i++] = v >> 16;
436 values[i++] = v >> 24;
439 for (;i < count; i++)
440 values[i] = v >> (8*(i%3));
445 static int read_pwr_cal_values(struct zd_chip *chip)
447 return read_values(chip, chip->pwr_cal_values,
448 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
452 static int read_pwr_int_values(struct zd_chip *chip)
454 return read_values(chip, chip->pwr_int_values,
455 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
459 static int read_ofdm_cal_values(struct zd_chip *chip)
463 static const zd_addr_t addresses[] = {
469 for (i = 0; i < 3; i++) {
470 r = read_values(chip, chip->ofdm_cal_values[i],
471 E2P_CHANNEL_COUNT, addresses[i], 0);
478 static int read_cal_int_tables(struct zd_chip *chip)
482 r = read_pwr_cal_values(chip);
485 r = read_pwr_int_values(chip);
488 r = read_ofdm_cal_values(chip);
494 /* phy means physical registers */
495 int zd_chip_lock_phy_regs(struct zd_chip *chip)
500 ZD_ASSERT(mutex_is_locked(&chip->mutex));
501 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
503 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
507 tmp &= ~UNLOCK_PHY_REGS;
509 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
511 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
515 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
520 ZD_ASSERT(mutex_is_locked(&chip->mutex));
521 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
523 dev_err(zd_chip_dev(chip),
524 "error ioread32(CR_REG1): %d\n", r);
528 tmp |= UNLOCK_PHY_REGS;
530 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
532 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
536 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
537 static int patch_cr157(struct zd_chip *chip)
542 if (!chip->patch_cr157)
545 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
549 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
550 return zd_iowrite32_locked(chip, value >> 8, CR157);
554 * 6M band edge can be optionally overwritten for certain RF's
555 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
556 * bit (for AL2230, AL2230S)
558 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
560 ZD_ASSERT(mutex_is_locked(&chip->mutex));
561 if (!chip->patch_6m_band_edge)
564 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
567 /* Generic implementation of 6M band edge patching, used by most RFs via
568 * zd_rf_generic_patch_6m() */
569 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
571 struct zd_ioreq16 ioreqs[] = {
572 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
576 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
577 if (channel == 1 || channel == 11)
578 ioreqs[0].value = 0x12;
580 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
581 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
584 static int zd1211_hw_reset_phy(struct zd_chip *chip)
586 static const struct zd_ioreq16 ioreqs[] = {
587 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
588 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
589 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
590 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
591 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
592 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
593 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
594 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
595 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
596 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
597 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
598 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
599 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
600 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
601 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
602 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
603 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
604 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
605 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
606 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
607 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
608 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
609 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
610 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
611 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
612 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
613 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
614 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
615 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
616 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
617 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
618 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
619 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
621 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
622 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
623 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
624 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
625 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
626 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
627 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
628 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
629 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
630 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
631 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
632 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
633 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
634 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
635 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
636 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
637 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
638 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
639 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
640 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
641 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
642 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
643 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
644 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
645 { CR170, 0xba }, { CR171, 0xba },
646 /* Note: CR204 must lead the CR203 */
654 dev_dbg_f(zd_chip_dev(chip), "\n");
656 r = zd_chip_lock_phy_regs(chip);
660 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
664 r = patch_cr157(chip);
666 t = zd_chip_unlock_phy_regs(chip);
673 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
675 static const struct zd_ioreq16 ioreqs[] = {
676 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
677 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
679 /* power control { { CR11, 1 << 6 }, */
681 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
682 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
683 { CR18, 0x0a }, { CR19, 0x48 },
684 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
685 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
686 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
687 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
688 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
689 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
690 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
691 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
692 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
693 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
694 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
695 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
696 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
697 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
698 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
699 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
700 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
701 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
702 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
703 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
704 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
706 { CR95, 0x20 }, /* ZD1211B */
707 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
708 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
709 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
710 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
711 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
712 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
713 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
714 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
715 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
716 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
717 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
718 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
719 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
720 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
721 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
722 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
723 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
724 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
725 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
726 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
727 { CR170, 0xba }, { CR171, 0xba },
728 /* Note: CR204 must lead the CR203 */
736 dev_dbg_f(zd_chip_dev(chip), "\n");
738 r = zd_chip_lock_phy_regs(chip);
742 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
743 t = zd_chip_unlock_phy_regs(chip);
750 static int hw_reset_phy(struct zd_chip *chip)
752 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
753 zd1211_hw_reset_phy(chip);
756 static int zd1211_hw_init_hmac(struct zd_chip *chip)
758 static const struct zd_ioreq32 ioreqs[] = {
759 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT },
760 { CR_RX_THRESHOLD, 0x000c0640 },
763 dev_dbg_f(zd_chip_dev(chip), "\n");
764 ZD_ASSERT(mutex_is_locked(&chip->mutex));
765 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
768 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
770 static const struct zd_ioreq32 ioreqs[] = {
771 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT },
772 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
773 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
774 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
775 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
776 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
777 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
778 { CR_ZD1211B_TXOP, 0x01800824 },
779 { CR_RX_THRESHOLD, 0x000c0eff, },
782 dev_dbg_f(zd_chip_dev(chip), "\n");
783 ZD_ASSERT(mutex_is_locked(&chip->mutex));
784 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
787 static int hw_init_hmac(struct zd_chip *chip)
790 static const struct zd_ioreq32 ioreqs[] = {
791 { CR_ACK_TIMEOUT_EXT, 0x20 },
792 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
793 { CR_SNIFFER_ON, 0 },
794 { CR_RX_FILTER, STA_RX_FILTER },
795 { CR_GROUP_HASH_P1, 0x00 },
796 { CR_GROUP_HASH_P2, 0x80000000 },
798 { CR_ADDA_PWR_DWN, 0x7f },
799 { CR_BCN_PLCP_CFG, 0x00f00401 },
800 { CR_PHY_DELAY, 0x00 },
801 { CR_ACK_TIMEOUT_EXT, 0x80 },
802 { CR_ADDA_PWR_DWN, 0x00 },
803 { CR_ACK_TIME_80211, 0x100 },
804 { CR_RX_PE_DELAY, 0x70 },
805 { CR_PS_CTRL, 0x10000000 },
806 { CR_RTS_CTS_RATE, 0x02030203 },
807 { CR_AFTER_PNP, 0x1 },
808 { CR_WEP_PROTECT, 0x114 },
809 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
810 { CR_CAM_MODE, MODE_AP_WDS},
813 ZD_ASSERT(mutex_is_locked(&chip->mutex));
814 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
818 return zd_chip_is_zd1211b(chip) ?
819 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
828 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
831 static const zd_addr_t aw_pt_bi_addr[] =
832 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
835 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
836 ARRAY_SIZE(aw_pt_bi_addr));
838 memset(s, 0, sizeof(*s));
842 s->atim_wnd_period = values[0];
843 s->pre_tbtt = values[1];
844 s->beacon_interval = values[2];
848 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
850 struct zd_ioreq32 reqs[3];
852 if (s->beacon_interval <= 5)
853 s->beacon_interval = 5;
854 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
855 s->pre_tbtt = s->beacon_interval - 1;
856 if (s->atim_wnd_period >= s->pre_tbtt)
857 s->atim_wnd_period = s->pre_tbtt - 1;
859 reqs[0].addr = CR_ATIM_WND_PERIOD;
860 reqs[0].value = s->atim_wnd_period;
861 reqs[1].addr = CR_PRE_TBTT;
862 reqs[1].value = s->pre_tbtt;
863 reqs[2].addr = CR_BCN_INTERVAL;
864 reqs[2].value = s->beacon_interval;
866 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
870 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
875 ZD_ASSERT(mutex_is_locked(&chip->mutex));
876 r = get_aw_pt_bi(chip, &s);
879 s.beacon_interval = interval;
880 return set_aw_pt_bi(chip, &s);
883 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
887 mutex_lock(&chip->mutex);
888 r = set_beacon_interval(chip, interval);
889 mutex_unlock(&chip->mutex);
893 static int hw_init(struct zd_chip *chip)
897 dev_dbg_f(zd_chip_dev(chip), "\n");
898 ZD_ASSERT(mutex_is_locked(&chip->mutex));
899 r = hw_reset_phy(chip);
903 r = hw_init_hmac(chip);
907 return set_beacon_interval(chip, 100);
910 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
912 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
916 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
917 const char *addr_string)
922 r = zd_ioread32_locked(chip, &value, addr);
924 dev_dbg_f(zd_chip_dev(chip),
925 "error reading %s. Error number %d\n", addr_string, r);
929 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
930 addr_string, (unsigned int)value);
934 static int test_init(struct zd_chip *chip)
938 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
941 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
944 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
947 static void dump_fw_registers(struct zd_chip *chip)
949 const zd_addr_t addr[4] = {
950 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
951 fw_reg_addr(chip, FW_REG_USB_SPEED),
952 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
953 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
959 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
962 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
967 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
968 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
970 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
974 static int print_fw_version(struct zd_chip *chip)
976 struct wiphy *wiphy = zd_chip_to_mac(chip)->hw->wiphy;
980 r = zd_ioread16_locked(chip, &version,
981 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
985 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
987 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version),
993 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
996 ZD_ASSERT(mutex_is_locked(&chip->mutex));
997 /* This sets the mandatory rates, which only depend from the standard
998 * that the device is supporting. Until further notice we should try
999 * to support 802.11g also for full speed USB.
1002 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1004 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1005 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1007 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1010 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1015 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1016 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1017 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1019 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1020 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1021 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1022 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1023 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1025 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1028 int zd_chip_enable_hwint(struct zd_chip *chip)
1032 mutex_lock(&chip->mutex);
1033 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1034 mutex_unlock(&chip->mutex);
1038 static int disable_hwint(struct zd_chip *chip)
1040 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1043 int zd_chip_disable_hwint(struct zd_chip *chip)
1047 mutex_lock(&chip->mutex);
1048 r = disable_hwint(chip);
1049 mutex_unlock(&chip->mutex);
1053 static int read_fw_regs_offset(struct zd_chip *chip)
1057 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1058 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1062 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1063 (u16)chip->fw_regs_base);
1068 /* Read mac address using pre-firmware interface */
1069 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1071 dev_dbg_f(zd_chip_dev(chip), "\n");
1072 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1076 int zd_chip_init_hw(struct zd_chip *chip)
1081 dev_dbg_f(zd_chip_dev(chip), "\n");
1083 mutex_lock(&chip->mutex);
1086 r = test_init(chip);
1090 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1094 r = read_fw_regs_offset(chip);
1098 /* GPI is always disabled, also in the other driver.
1100 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1103 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1106 /* Currently we support IEEE 802.11g for full and high speed USB.
1107 * It might be discussed, whether we should suppport pure b mode for
1110 r = set_mandatory_rates(chip, 1);
1113 /* Disabling interrupts is certainly a smart thing here.
1115 r = disable_hwint(chip);
1118 r = read_pod(chip, &rf_type);
1124 r = zd_rf_init_hw(&chip->rf, rf_type);
1128 r = print_fw_version(chip);
1133 dump_fw_registers(chip);
1134 r = test_init(chip);
1139 r = read_cal_int_tables(chip);
1145 mutex_unlock(&chip->mutex);
1149 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1151 u8 value = chip->pwr_int_values[channel - 1];
1152 return zd_iowrite16_locked(chip, value, CR31);
1155 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1157 u8 value = chip->pwr_cal_values[channel-1];
1158 return zd_iowrite16_locked(chip, value, CR68);
1161 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1163 struct zd_ioreq16 ioreqs[3];
1165 ioreqs[0].addr = CR67;
1166 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1167 ioreqs[1].addr = CR66;
1168 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1169 ioreqs[2].addr = CR65;
1170 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1172 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1175 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1180 if (!zd_rf_should_update_pwr_int(&chip->rf))
1183 r = update_pwr_int(chip, channel);
1186 if (zd_chip_is_zd1211b(chip)) {
1187 static const struct zd_ioreq16 ioreqs[] = {
1193 r = update_ofdm_cal(chip, channel);
1196 r = update_pwr_cal(chip, channel);
1199 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1207 /* The CCK baseband gain can be optionally patched by the EEPROM */
1208 static int patch_cck_gain(struct zd_chip *chip)
1213 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1216 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1217 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1220 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1221 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1224 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1228 mutex_lock(&chip->mutex);
1229 r = zd_chip_lock_phy_regs(chip);
1232 r = zd_rf_set_channel(&chip->rf, channel);
1235 r = update_channel_integration_and_calibration(chip, channel);
1238 r = patch_cck_gain(chip);
1241 r = patch_6m_band_edge(chip, channel);
1244 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1246 t = zd_chip_unlock_phy_regs(chip);
1250 mutex_unlock(&chip->mutex);
1254 u8 zd_chip_get_channel(struct zd_chip *chip)
1258 mutex_lock(&chip->mutex);
1259 channel = chip->rf.channel;
1260 mutex_unlock(&chip->mutex);
1264 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1266 const zd_addr_t a[] = {
1267 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1272 u16 v[ARRAY_SIZE(a)];
1273 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1274 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1279 mutex_lock(&chip->mutex);
1280 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1284 other_led = chip->link_led == LED1 ? LED2 : LED1;
1288 ioreqs[0].value = FW_LINK_OFF;
1289 ioreqs[1].value = v[1] & ~(LED1|LED2);
1291 case ZD_LED_SCANNING:
1292 ioreqs[0].value = FW_LINK_OFF;
1293 ioreqs[1].value = v[1] & ~other_led;
1294 if (get_seconds() % 3 == 0) {
1295 ioreqs[1].value &= ~chip->link_led;
1297 ioreqs[1].value |= chip->link_led;
1300 case ZD_LED_ASSOCIATED:
1301 ioreqs[0].value = FW_LINK_TX;
1302 ioreqs[1].value = v[1] & ~other_led;
1303 ioreqs[1].value |= chip->link_led;
1310 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1311 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1317 mutex_unlock(&chip->mutex);
1321 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1325 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1328 mutex_lock(&chip->mutex);
1329 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1330 mutex_unlock(&chip->mutex);
1334 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1336 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1340 * zd_rx_rate - report zd-rate
1341 * @rx_frame - received frame
1342 * @rx_status - rx_status as given by the device
1344 * This function converts the rate as encoded in the received packet to the
1345 * zd-rate, we are using on other places in the driver.
1347 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1350 if (status->frame_status & ZD_RX_OFDM) {
1351 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1353 switch (zd_cck_plcp_header_signal(rx_frame)) {
1354 case ZD_CCK_PLCP_SIGNAL_1M:
1355 zd_rate = ZD_CCK_RATE_1M;
1357 case ZD_CCK_PLCP_SIGNAL_2M:
1358 zd_rate = ZD_CCK_RATE_2M;
1360 case ZD_CCK_PLCP_SIGNAL_5M5:
1361 zd_rate = ZD_CCK_RATE_5_5M;
1363 case ZD_CCK_PLCP_SIGNAL_11M:
1364 zd_rate = ZD_CCK_RATE_11M;
1374 int zd_chip_switch_radio_on(struct zd_chip *chip)
1378 mutex_lock(&chip->mutex);
1379 r = zd_switch_radio_on(&chip->rf);
1380 mutex_unlock(&chip->mutex);
1384 int zd_chip_switch_radio_off(struct zd_chip *chip)
1388 mutex_lock(&chip->mutex);
1389 r = zd_switch_radio_off(&chip->rf);
1390 mutex_unlock(&chip->mutex);
1394 int zd_chip_enable_int(struct zd_chip *chip)
1398 mutex_lock(&chip->mutex);
1399 r = zd_usb_enable_int(&chip->usb);
1400 mutex_unlock(&chip->mutex);
1404 void zd_chip_disable_int(struct zd_chip *chip)
1406 mutex_lock(&chip->mutex);
1407 zd_usb_disable_int(&chip->usb);
1408 mutex_unlock(&chip->mutex);
1411 int zd_chip_enable_rxtx(struct zd_chip *chip)
1415 mutex_lock(&chip->mutex);
1416 zd_usb_enable_tx(&chip->usb);
1417 r = zd_usb_enable_rx(&chip->usb);
1418 mutex_unlock(&chip->mutex);
1422 void zd_chip_disable_rxtx(struct zd_chip *chip)
1424 mutex_lock(&chip->mutex);
1425 zd_usb_disable_rx(&chip->usb);
1426 zd_usb_disable_tx(&chip->usb);
1427 mutex_unlock(&chip->mutex);
1430 int zd_rfwritev_locked(struct zd_chip *chip,
1431 const u32* values, unsigned int count, u8 bits)
1436 for (i = 0; i < count; i++) {
1437 r = zd_rfwrite_locked(chip, values[i], bits);
1446 * We can optionally program the RF directly through CR regs, if supported by
1447 * the hardware. This is much faster than the older method.
1449 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1451 struct zd_ioreq16 ioreqs[] = {
1452 { CR244, (value >> 16) & 0xff },
1453 { CR243, (value >> 8) & 0xff },
1454 { CR242, value & 0xff },
1456 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1457 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1460 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1461 const u32 *values, unsigned int count)
1466 for (i = 0; i < count; i++) {
1467 r = zd_rfwrite_cr_locked(chip, values[i]);
1475 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1476 struct zd_mc_hash *hash)
1478 struct zd_ioreq32 ioreqs[] = {
1479 { CR_GROUP_HASH_P1, hash->low },
1480 { CR_GROUP_HASH_P2, hash->high },
1483 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1486 u64 zd_chip_get_tsf(struct zd_chip *chip)
1489 static const zd_addr_t aw_pt_bi_addr[] =
1490 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1494 mutex_lock(&chip->mutex);
1495 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1496 ARRAY_SIZE(aw_pt_bi_addr));
1497 mutex_unlock(&chip->mutex);
1502 tsf = (tsf << 32) | values[0];