2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
5 * Michal SIMEK <monstr@monstr.eu>
7 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm-generic/errno.h>
21 #include <linux/kernel.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define ENET_ADDR_LENGTH 6
26 #define ETH_FCS_LEN 4 /* Octets in the FCS */
29 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
30 /* Xmit interrupt enable bit */
31 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
32 /* Program the MAC address */
33 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
34 /* define for programming the MAC address into the EMAC Lite */
35 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
37 /* Transmit packet length upper byte */
38 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
39 /* Transmit packet length lower byte */
40 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
43 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
44 /* Recv interrupt enable bit */
45 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
47 /* MDIO Address Register Bit Masks */
48 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
49 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
50 #define XEL_MDIOADDR_PHYADR_SHIFT 5
51 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
53 /* MDIO Write Data Register Bit Masks */
54 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
56 /* MDIO Read Data Register Bit Masks */
57 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
59 /* MDIO Control Register Bit Masks */
60 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
61 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
63 struct emaclite_regs {
64 u32 tx_ping; /* 0x0 - TX Ping buffer */
66 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
67 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
68 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
69 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
70 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
71 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
72 u32 tx_ping_tsr; /* 0x7fc - Tx status */
73 u32 tx_pong; /* 0x800 - TX Pong buffer */
75 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
76 u32 reserved3; /* 0xff8 */
77 u32 tx_pong_tsr; /* 0xffc - Tx status */
78 u32 rx_ping; /* 0x1000 - Receive Buffer */
80 u32 rx_ping_rsr; /* 0x17fc - Rx status */
81 u32 rx_pong; /* 0x1800 - Receive Buffer */
83 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
87 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
88 u32 txpp; /* TX ping pong buffer */
89 u32 rxpp; /* RX ping pong buffer */
91 struct emaclite_regs *regs;
92 struct phy_device *phydev;
96 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
98 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
107 from32ptr = (u32 *) srcptr;
109 /* Word aligned buffer, no correction needed. */
110 to32ptr = (u32 *) destptr;
111 while (bytecount > 3) {
112 *to32ptr++ = *from32ptr++;
115 to8ptr = (u8 *) to32ptr;
117 alignbuffer = *from32ptr++;
118 from8ptr = (u8 *) &alignbuffer;
120 for (i = 0; i < bytecount; i++)
121 *to8ptr++ = *from8ptr++;
124 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
128 u32 *to32ptr = (u32 *) destptr;
133 from32ptr = (u32 *) srcptr;
134 while (bytecount > 3) {
136 *to32ptr++ = *from32ptr++;
141 to8ptr = (u8 *) &alignbuffer;
142 from8ptr = (u8 *) from32ptr;
144 for (i = 0; i < bytecount; i++)
145 *to8ptr++ = *from8ptr++;
147 *to32ptr++ = alignbuffer;
150 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
151 bool set, unsigned int timeout)
154 unsigned long start = get_timer(0);
162 if ((val & mask) == mask)
165 if (get_timer(start) > timeout)
176 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
177 func, reg, mask, set);
182 static int mdio_wait(struct emaclite_regs *regs)
184 return wait_for_bit(__func__, ®s->mdioctrl,
185 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
188 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
191 struct emaclite_regs *regs = emaclite->regs;
196 u32 ctrl_reg = in_be32(®s->mdioctrl);
197 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
198 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
199 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
205 *data = in_be32(®s->mdiord);
209 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
212 struct emaclite_regs *regs = emaclite->regs;
218 * Write the PHY address, register number and clear the OP bit in the
219 * MDIO Address register and then write the value into the MDIO Write
220 * Data register. Finally, set the Status bit in the MDIO Control
221 * register to start a MDIO write transaction.
223 u32 ctrl_reg = in_be32(®s->mdioctrl);
224 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
225 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
226 out_be32(®s->mdiowr, data);
227 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
235 static void emaclite_stop(struct udevice *dev)
240 /* Use MII register 1 (MII status register) to detect PHY */
241 #define PHY_DETECT_REG 1
243 /* Mask used to verify certain PHY features (or register contents)
244 * in the register above:
245 * 0x1000: 10Mbps full duplex support
246 * 0x0800: 10Mbps half duplex support
247 * 0x0008: Auto-negotiation support
249 #define PHY_DETECT_MASK 0x1808
251 static int setup_phy(struct udevice *dev)
255 struct xemaclite *emaclite = dev_get_priv(dev);
256 struct phy_device *phydev;
258 u32 supported = SUPPORTED_10baseT_Half |
259 SUPPORTED_10baseT_Full |
260 SUPPORTED_100baseT_Half |
261 SUPPORTED_100baseT_Full;
263 if (emaclite->phyaddr != -1) {
264 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
265 if ((phyreg != 0xFFFF) &&
266 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
267 /* Found a valid PHY address */
268 debug("Default phy address %d is valid\n",
271 debug("PHY address is not setup correctly %d\n",
273 emaclite->phyaddr = -1;
277 if (emaclite->phyaddr == -1) {
278 /* detect the PHY address */
279 for (i = 31; i >= 0; i--) {
280 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
281 if ((phyreg != 0xFFFF) &&
282 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
283 /* Found a valid PHY address */
284 emaclite->phyaddr = i;
285 debug("emaclite: Found valid phy address, %d\n",
292 /* interface - look at tsec */
293 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
294 PHY_INTERFACE_MODE_MII);
296 * Phy can support 1000baseT but device NOT that's why phydev->supported
297 * must be setup for 1000baseT. phydev->advertising setups what speeds
298 * will be used for autonegotiation where 1000baseT must be disabled.
300 phydev->supported = supported | SUPPORTED_1000baseT_Half |
301 SUPPORTED_1000baseT_Full;
302 phydev->advertising = supported;
303 emaclite->phydev = phydev;
308 printf("%s: No link.\n", phydev->dev->name);
312 /* Do not setup anything */
316 static int emaclite_start(struct udevice *dev)
318 struct xemaclite *emaclite = dev_get_priv(dev);
319 struct eth_pdata *pdata = dev_get_platdata(dev);
320 struct emaclite_regs *regs = emaclite->regs;
322 debug("EmacLite Initialization Started\n");
325 * TX - TX_PING & TX_PONG initialization
327 /* Restart PING TX */
328 out_be32(®s->tx_ping_tsr, 0);
329 /* Copy MAC address */
330 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
333 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
334 /* Update the MAC address in the EMAC Lite */
335 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
336 /* Wait for EMAC Lite to finish with the MAC address update */
337 while ((in_be32 (®s->tx_ping_tsr) &
338 XEL_TSR_PROG_MAC_ADDR) != 0)
341 if (emaclite->txpp) {
342 /* The same operation with PONG TX */
343 out_be32(®s->tx_pong_tsr, 0);
344 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
346 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
347 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
348 while ((in_be32(®s->tx_pong_tsr) &
349 XEL_TSR_PROG_MAC_ADDR) != 0)
354 * RX - RX_PING & RX_PONG initialization
356 /* Write out the value to flush the RX buffer */
357 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
360 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
362 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
363 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
367 debug("EmacLite Initialization complete\n");
371 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
374 struct emaclite_regs *regs = emaclite->regs;
377 * Read the other buffer register
378 * and determine if the other buffer is available
380 tmp = ~in_be32(®s->tx_ping_tsr);
382 tmp |= ~in_be32(®s->tx_pong_tsr);
384 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
387 static int emaclite_send(struct udevice *dev, void *ptr, int len)
390 struct xemaclite *emaclite = dev_get_priv(dev);
391 struct emaclite_regs *regs = emaclite->regs;
398 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
404 printf("Error: Timeout waiting for ethernet TX buffer\n");
405 /* Restart PING TX */
406 out_be32(®s->tx_ping_tsr, 0);
407 if (emaclite->txpp) {
408 out_be32(®s->tx_pong_tsr, 0);
413 /* Determine if the expected buffer address is empty */
414 reg = in_be32(®s->tx_ping_tsr);
415 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
416 debug("Send packet from tx_ping buffer\n");
417 /* Write the frame to the buffer */
418 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
419 out_be32(®s->tx_ping_tplr, len &
420 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
421 reg = in_be32(®s->tx_ping_tsr);
422 reg |= XEL_TSR_XMIT_BUSY_MASK;
423 out_be32(®s->tx_ping_tsr, reg);
427 if (emaclite->txpp) {
428 /* Determine if the expected buffer address is empty */
429 reg = in_be32(®s->tx_pong_tsr);
430 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
431 debug("Send packet from tx_pong buffer\n");
432 /* Write the frame to the buffer */
433 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
434 out_be32(®s->tx_pong_tplr, len &
435 (XEL_TPLR_LENGTH_MASK_HI |
436 XEL_TPLR_LENGTH_MASK_LO));
437 reg = in_be32(®s->tx_pong_tsr);
438 reg |= XEL_TSR_XMIT_BUSY_MASK;
439 out_be32(®s->tx_pong_tsr, reg);
444 puts("Error while sending frame\n");
448 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
450 u32 length, first_read, reg, attempt = 0;
452 struct xemaclite *emaclite = dev->priv;
453 struct emaclite_regs *regs = emaclite->regs;
454 struct ethernet_hdr *eth;
455 struct ip_udp_hdr *ip;
458 if (!emaclite->use_rx_pong_buffer_next) {
459 reg = in_be32(®s->rx_ping_rsr);
460 debug("Testing data at rx_ping\n");
461 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
462 debug("Data found in rx_ping buffer\n");
463 addr = ®s->rx_ping;
464 ack = ®s->rx_ping_rsr;
466 debug("Data not found in rx_ping buffer\n");
467 /* Pong buffer is not available - return immediately */
471 /* Try pong buffer if this is first attempt */
474 emaclite->use_rx_pong_buffer_next =
475 !emaclite->use_rx_pong_buffer_next;
479 reg = in_be32(®s->rx_pong_rsr);
480 debug("Testing data at rx_pong\n");
481 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
482 debug("Data found in rx_pong buffer\n");
483 addr = ®s->rx_pong;
484 ack = ®s->rx_pong_rsr;
486 debug("Data not found in rx_pong buffer\n");
487 /* Try ping buffer if this is first attempt */
490 emaclite->use_rx_pong_buffer_next =
491 !emaclite->use_rx_pong_buffer_next;
496 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
497 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
498 xemaclite_alignedread(addr, etherrxbuff, first_read);
500 /* Detect real packet size */
501 eth = (struct ethernet_hdr *)etherrxbuff;
502 switch (ntohs(eth->et_protlen)) {
505 debug("ARP Packet %x\n", length);
508 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
509 length = ntohs(ip->ip_len);
510 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
511 debug("IP Packet %x\n", length);
514 debug("Other Packet\n");
519 /* Read the rest of the packet which is longer then first read */
520 if (length != first_read)
521 xemaclite_alignedread(addr + first_read,
522 etherrxbuff + first_read,
523 length - first_read);
525 /* Acknowledge the frame */
527 reg &= ~XEL_RSR_RECV_DONE_MASK;
530 debug("Packet receive from 0x%p, length %dB\n", addr, length);
531 *packetp = etherrxbuff;
535 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
541 ret = phyread(bus->priv, addr, reg, &val);
542 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
546 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
549 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
550 return phywrite(bus->priv, addr, reg, value);
553 static int emaclite_probe(struct udevice *dev)
555 struct xemaclite *emaclite = dev_get_priv(dev);
558 emaclite->bus = mdio_alloc();
559 emaclite->bus->read = emaclite_miiphy_read;
560 emaclite->bus->write = emaclite_miiphy_write;
561 emaclite->bus->priv = emaclite;
562 strcpy(emaclite->bus->name, "emaclite");
564 ret = mdio_register(emaclite->bus);
571 static int emaclite_remove(struct udevice *dev)
573 struct xemaclite *emaclite = dev_get_priv(dev);
575 free(emaclite->phydev);
576 mdio_unregister(emaclite->bus);
577 mdio_free(emaclite->bus);
582 static const struct eth_ops emaclite_ops = {
583 .start = emaclite_start,
584 .send = emaclite_send,
585 .recv = emaclite_recv,
586 .stop = emaclite_stop,
589 static int emaclite_ofdata_to_platdata(struct udevice *dev)
591 struct eth_pdata *pdata = dev_get_platdata(dev);
592 struct xemaclite *emaclite = dev_get_priv(dev);
595 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
596 emaclite->regs = (struct emaclite_regs *)pdata->iobase;
598 emaclite->phyaddr = -1;
600 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
603 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
606 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
607 "xlnx,tx-ping-pong", 0);
608 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
609 "xlnx,rx-ping-pong", 0);
611 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
612 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
617 static const struct udevice_id emaclite_ids[] = {
618 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
622 U_BOOT_DRIVER(emaclite) = {
625 .of_match = emaclite_ids,
626 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
627 .probe = emaclite_probe,
628 .remove = emaclite_remove,
629 .ops = &emaclite_ops,
630 .priv_auto_alloc_size = sizeof(struct xemaclite),
631 .platdata_auto_alloc_size = sizeof(struct eth_pdata),