2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Intel PCIe NTB Linux driver
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
48 #include <linux/debugfs.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/random.h>
55 #include <linux/slab.h>
59 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
62 MODULE_DESCRIPTION(NTB_NAME);
63 MODULE_VERSION(NTB_VER);
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_AUTHOR("Intel Corporation");
67 static bool xeon_errata_workaround = true;
68 module_param(xeon_errata_workaround, bool, 0644);
69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
72 NTB_CONN_TRANSPARENT = 0,
87 static struct dentry *debugfs_dir;
89 #define BWD_LINK_RECOVERY_TIME 500
91 /* Translate memory window 0,1 to BAR 2,4 */
92 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
94 static const struct pci_device_id ntb_pci_tbl[] = {
95 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
96 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
97 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
98 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
99 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
100 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
101 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
102 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
103 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
104 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
105 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
106 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
107 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
113 * ntb_register_event_callback() - register event callback
114 * @ndev: pointer to ntb_device instance
115 * @func: callback function to register
117 * This function registers a callback for any HW driver events such as link
118 * up/down, power management notices and etc.
120 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
122 int ntb_register_event_callback(struct ntb_device *ndev,
123 void (*func)(void *handle,
124 enum ntb_hw_event event))
129 ndev->event_cb = func;
135 * ntb_unregister_event_callback() - unregisters the event callback
136 * @ndev: pointer to ntb_device instance
138 * This function unregisters the existing callback from transport
140 void ntb_unregister_event_callback(struct ntb_device *ndev)
142 ndev->event_cb = NULL;
145 static void ntb_irq_work(unsigned long data)
147 struct ntb_db_cb *db_cb = (struct ntb_db_cb *)data;
150 rc = db_cb->callback(db_cb->data, db_cb->db_num);
152 tasklet_schedule(&db_cb->irq_work);
154 struct ntb_device *ndev = db_cb->ndev;
157 mask = readw(ndev->reg_ofs.ldb_mask);
158 clear_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
159 writew(mask, ndev->reg_ofs.ldb_mask);
164 * ntb_register_db_callback() - register a callback for doorbell interrupt
165 * @ndev: pointer to ntb_device instance
166 * @idx: doorbell index to register callback, zero based
167 * @data: pointer to be returned to caller with every callback
168 * @func: callback function to register
170 * This function registers a callback function for the doorbell interrupt
171 * on the primary side. The function will unmask the doorbell as well to
174 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
176 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
177 void *data, int (*func)(void *data, int db_num))
181 if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
182 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
186 ndev->db_cb[idx].callback = func;
187 ndev->db_cb[idx].data = data;
188 ndev->db_cb[idx].ndev = ndev;
190 tasklet_init(&ndev->db_cb[idx].irq_work, ntb_irq_work,
191 (unsigned long) &ndev->db_cb[idx]);
193 /* unmask interrupt */
194 mask = readw(ndev->reg_ofs.ldb_mask);
195 clear_bit(idx * ndev->bits_per_vector, &mask);
196 writew(mask, ndev->reg_ofs.ldb_mask);
202 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
203 * @ndev: pointer to ntb_device instance
204 * @idx: doorbell index to register callback, zero based
206 * This function unregisters a callback function for the doorbell interrupt
207 * on the primary side. The function will also mask the said doorbell.
209 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
213 if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
216 mask = readw(ndev->reg_ofs.ldb_mask);
217 set_bit(idx * ndev->bits_per_vector, &mask);
218 writew(mask, ndev->reg_ofs.ldb_mask);
220 tasklet_disable(&ndev->db_cb[idx].irq_work);
222 ndev->db_cb[idx].callback = NULL;
226 * ntb_find_transport() - find the transport pointer
227 * @transport: pointer to pci device
229 * Given the pci device pointer, return the transport pointer passed in when
230 * the transport attached when it was inited.
232 * RETURNS: pointer to transport.
234 void *ntb_find_transport(struct pci_dev *pdev)
236 struct ntb_device *ndev = pci_get_drvdata(pdev);
237 return ndev->ntb_transport;
241 * ntb_register_transport() - Register NTB transport with NTB HW driver
242 * @transport: transport identifier
244 * This function allows a transport to reserve the hardware driver for
247 * RETURNS: pointer to ntb_device, NULL on error.
249 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
251 struct ntb_device *ndev = pci_get_drvdata(pdev);
253 if (ndev->ntb_transport)
256 ndev->ntb_transport = transport;
261 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
262 * @ndev - ntb_device of the transport to be freed
264 * This function unregisters the transport from the HW driver and performs any
265 * necessary cleanups.
267 void ntb_unregister_transport(struct ntb_device *ndev)
271 if (!ndev->ntb_transport)
274 for (i = 0; i < ndev->max_cbs; i++)
275 ntb_unregister_db_callback(ndev, i);
277 ntb_unregister_event_callback(ndev);
278 ndev->ntb_transport = NULL;
282 * ntb_write_local_spad() - write to the secondary scratchpad register
283 * @ndev: pointer to ntb_device instance
284 * @idx: index to the scratchpad register, 0 based
285 * @val: the data value to put into the register
287 * This function allows writing of a 32bit value to the indexed scratchpad
288 * register. This writes over the data mirrored to the local scratchpad register
289 * by the remote system.
291 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
293 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
295 if (idx >= ndev->limits.max_spads)
298 dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
300 writel(val, ndev->reg_ofs.spad_read + idx * 4);
306 * ntb_read_local_spad() - read from the primary scratchpad register
307 * @ndev: pointer to ntb_device instance
308 * @idx: index to scratchpad register, 0 based
309 * @val: pointer to 32bit integer for storing the register value
311 * This function allows reading of the 32bit scratchpad register on
312 * the primary (internal) side. This allows the local system to read data
313 * written and mirrored to the scratchpad register by the remote system.
315 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
317 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
319 if (idx >= ndev->limits.max_spads)
322 *val = readl(ndev->reg_ofs.spad_write + idx * 4);
323 dev_dbg(&ndev->pdev->dev,
324 "Reading %x from local scratch pad index %d\n", *val, idx);
330 * ntb_write_remote_spad() - write to the secondary scratchpad register
331 * @ndev: pointer to ntb_device instance
332 * @idx: index to the scratchpad register, 0 based
333 * @val: the data value to put into the register
335 * This function allows writing of a 32bit value to the indexed scratchpad
336 * register. The register resides on the secondary (external) side. This allows
337 * the local system to write data to be mirrored to the remote systems
338 * scratchpad register.
340 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
342 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
344 if (idx >= ndev->limits.max_spads)
347 dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
349 writel(val, ndev->reg_ofs.spad_write + idx * 4);
355 * ntb_read_remote_spad() - read from the primary scratchpad register
356 * @ndev: pointer to ntb_device instance
357 * @idx: index to scratchpad register, 0 based
358 * @val: pointer to 32bit integer for storing the register value
360 * This function allows reading of the 32bit scratchpad register on
361 * the primary (internal) side. This alloows the local system to read the data
362 * it wrote to be mirrored on the remote system.
364 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
366 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
368 if (idx >= ndev->limits.max_spads)
371 *val = readl(ndev->reg_ofs.spad_read + idx * 4);
372 dev_dbg(&ndev->pdev->dev,
373 "Reading %x from remote scratch pad index %d\n", *val, idx);
379 * ntb_get_mw_base() - get addr for the NTB memory window
380 * @ndev: pointer to ntb_device instance
381 * @mw: memory window number
383 * This function provides the base address of the memory window specified.
385 * RETURNS: address, or NULL on error.
387 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
389 if (mw >= ntb_max_mw(ndev))
392 return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
396 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
397 * @ndev: pointer to ntb_device instance
398 * @mw: memory window number
400 * This function provides the base virtual address of the memory window
403 * RETURNS: pointer to virtual address, or NULL on error.
405 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
407 if (mw >= ntb_max_mw(ndev))
410 return ndev->mw[mw].vbase;
414 * ntb_get_mw_size() - return size of NTB memory window
415 * @ndev: pointer to ntb_device instance
416 * @mw: memory window number
418 * This function provides the physical size of the memory window specified
420 * RETURNS: the size of the memory window or zero on error
422 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
424 if (mw >= ntb_max_mw(ndev))
427 return ndev->mw[mw].bar_sz;
431 * ntb_set_mw_addr - set the memory window address
432 * @ndev: pointer to ntb_device instance
433 * @mw: memory window number
434 * @addr: base address for data
436 * This function sets the base physical address of the memory window. This
437 * memory address is where data from the remote system will be transfered into
438 * or out of depending on how the transport is configured.
440 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
442 if (mw >= ntb_max_mw(ndev))
445 dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
448 ndev->mw[mw].phys_addr = addr;
450 switch (MW_TO_BAR(mw)) {
452 writeq(addr, ndev->reg_ofs.bar2_xlat);
455 writeq(addr, ndev->reg_ofs.bar4_xlat);
461 * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
462 * @ndev: pointer to ntb_device instance
463 * @db: doorbell to ring
465 * This function allows triggering of a doorbell on the secondary/external
466 * side that will initiate an interrupt on the remote host
468 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
470 void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db)
472 dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
474 if (ndev->hw_type == BWD_HW)
475 writeq((u64) 1 << db, ndev->reg_ofs.rdb);
477 writew(((1 << ndev->bits_per_vector) - 1) <<
478 (db * ndev->bits_per_vector), ndev->reg_ofs.rdb);
481 static void bwd_recover_link(struct ntb_device *ndev)
485 /* Driver resets the NTB ModPhy lanes - magic! */
486 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
487 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
488 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
489 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
491 /* Driver waits 100ms to allow the NTB ModPhy to settle */
494 /* Clear AER Errors, write to clear */
495 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
496 dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
497 status &= PCI_ERR_COR_REP_ROLL;
498 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
500 /* Clear unexpected electrical idle event in LTSSM, write to clear */
501 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
502 dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
503 status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
504 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
506 /* Clear DeSkew Buffer error, write to clear */
507 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
508 dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
509 status |= BWD_DESKEWSTS_DBERR;
510 writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
512 status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
513 dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
514 status &= BWD_IBIST_ERR_OFLOW;
515 writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
517 /* Releases the NTB state machine to allow the link to retrain */
518 status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
519 dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
520 status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
521 writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
524 static void ntb_link_event(struct ntb_device *ndev, int link_state)
528 if (ndev->link_status == link_state)
531 if (link_state == NTB_LINK_UP) {
534 dev_info(&ndev->pdev->dev, "Link Up\n");
535 ndev->link_status = NTB_LINK_UP;
536 event = NTB_EVENT_HW_LINK_UP;
538 if (ndev->hw_type == BWD_HW ||
539 ndev->conn_type == NTB_CONN_TRANSPARENT)
540 status = readw(ndev->reg_ofs.lnk_stat);
542 int rc = pci_read_config_word(ndev->pdev,
543 SNB_LINK_STATUS_OFFSET,
549 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
550 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
551 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
552 ndev->link_width, ndev->link_speed);
554 dev_info(&ndev->pdev->dev, "Link Down\n");
555 ndev->link_status = NTB_LINK_DOWN;
556 event = NTB_EVENT_HW_LINK_DOWN;
557 /* Don't modify link width/speed, we need it in link recovery */
560 /* notify the upper layer if we have an event change */
562 ndev->event_cb(ndev->ntb_transport, event);
565 static int ntb_link_status(struct ntb_device *ndev)
569 if (ndev->hw_type == BWD_HW) {
572 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
573 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
574 link_state = NTB_LINK_DOWN;
576 link_state = NTB_LINK_UP;
581 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
586 if (status & NTB_LINK_STATUS_ACTIVE)
587 link_state = NTB_LINK_UP;
589 link_state = NTB_LINK_DOWN;
592 ntb_link_event(ndev, link_state);
597 static void bwd_link_recovery(struct work_struct *work)
599 struct ntb_device *ndev = container_of(work, struct ntb_device,
603 bwd_recover_link(ndev);
604 /* There is a potential race between the 2 NTB devices recovering at the
605 * same time. If the times are the same, the link will not recover and
606 * the driver will be stuck in this loop forever. Add a random interval
607 * to the recovery time to prevent this race.
609 msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
611 status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
612 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
615 status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
616 if (status32 & BWD_IBIST_ERR_OFLOW)
619 status32 = readl(ndev->reg_ofs.lnk_cntl);
620 if (!(status32 & BWD_CNTL_LINK_DOWN)) {
621 unsigned char speed, width;
624 status16 = readw(ndev->reg_ofs.lnk_stat);
625 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
626 speed = (status16 & NTB_LINK_SPEED_MASK);
627 if (ndev->link_width != width || ndev->link_speed != speed)
631 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
635 schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
638 /* BWD doesn't have link status interrupt, poll on that platform */
639 static void bwd_link_poll(struct work_struct *work)
641 struct ntb_device *ndev = container_of(work, struct ntb_device,
643 unsigned long ts = jiffies;
645 /* If we haven't gotten an interrupt in a while, check the BWD link
648 if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
649 int rc = ntb_link_status(ndev);
651 dev_err(&ndev->pdev->dev,
652 "Error determining link status\n");
654 /* Check to see if a link error is the cause of the link down */
655 if (ndev->link_status == NTB_LINK_DOWN) {
656 u32 status32 = readl(ndev->reg_base +
657 BWD_LTSSMSTATEJMP_OFFSET);
658 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
659 schedule_delayed_work(&ndev->lr_timer, 0);
665 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
668 static int ntb_xeon_setup(struct ntb_device *ndev)
673 ndev->hw_type = SNB_HW;
675 rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
679 if (val & SNB_PPD_DEV_TYPE)
680 ndev->dev_type = NTB_DEV_USD;
682 ndev->dev_type = NTB_DEV_DSD;
684 switch (val & SNB_PPD_CONN_TYPE) {
686 dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
687 ndev->conn_type = NTB_CONN_B2B;
688 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
689 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
690 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
691 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
692 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
693 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
695 /* There is a Xeon hardware errata related to writes to
696 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
697 * to NTB MMIO Space, which may hang the system. To workaround
698 * this use the second memory window to access the interrupt and
699 * scratch pad registers on the remote system.
701 if (xeon_errata_workaround) {
702 if (!ndev->mw[1].bar_sz)
705 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
706 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
707 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
709 ndev->reg_ofs.rdb = ndev->mw[1].vbase +
710 SNB_PDOORBELL_OFFSET;
712 /* Set the Limit register to 4k, the minimum size, to
713 * prevent an illegal access
715 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
716 SNB_PBAR4LMT_OFFSET);
717 /* HW errata on the Limit registers. They can only be
718 * written when the base register is 4GB aligned and
719 * < 32bit. This should already be the case based on
720 * the driver defaults, but write the Limit registers
721 * first just in case.
724 ndev->limits.max_mw = SNB_MAX_MW;
726 /* HW Errata on bit 14 of b2bdoorbell register. Writes
727 * will not be mirrored to the remote system. Shrink
728 * the number of bits by one, since bit 14 is the last
731 ndev->limits.max_db_bits = SNB_MAX_DB_BITS - 1;
732 ndev->reg_ofs.spad_write = ndev->reg_base +
734 ndev->reg_ofs.rdb = ndev->reg_base +
735 SNB_B2B_DOORBELL_OFFSET;
737 /* Disable the Limit register, just incase it is set to
740 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
741 /* HW errata on the Limit registers. They can only be
742 * written when the base register is 4GB aligned and
743 * < 32bit. This should already be the case based on
744 * the driver defaults, but write the Limit registers
745 * first just in case.
749 /* The Xeon errata workaround requires setting SBAR Base
750 * addresses to known values, so that the PBAR XLAT can be
751 * pointed at SBAR0 of the remote system.
753 if (ndev->dev_type == NTB_DEV_USD) {
754 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
755 SNB_PBAR2XLAT_OFFSET);
756 if (xeon_errata_workaround)
757 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
758 SNB_PBAR4XLAT_OFFSET);
760 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
761 SNB_PBAR4XLAT_OFFSET);
762 /* B2B_XLAT_OFFSET is a 64bit register, but can
763 * only take 32bit writes
765 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
766 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
767 writel(SNB_MBAR01_DSD_ADDR >> 32,
768 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
771 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
772 SNB_SBAR0BASE_OFFSET);
773 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
774 SNB_SBAR2BASE_OFFSET);
775 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
776 SNB_SBAR4BASE_OFFSET);
778 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
779 SNB_PBAR2XLAT_OFFSET);
780 if (xeon_errata_workaround)
781 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
782 SNB_PBAR4XLAT_OFFSET);
784 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
785 SNB_PBAR4XLAT_OFFSET);
786 /* B2B_XLAT_OFFSET is a 64bit register, but can
787 * only take 32bit writes
789 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
790 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
791 writel(SNB_MBAR01_USD_ADDR >> 32,
792 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
794 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
795 SNB_SBAR0BASE_OFFSET);
796 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
797 SNB_SBAR2BASE_OFFSET);
798 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
799 SNB_SBAR4BASE_OFFSET);
803 dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
804 ndev->conn_type = NTB_CONN_RP;
806 if (xeon_errata_workaround) {
807 dev_err(&ndev->pdev->dev,
808 "NTB-RP disabled due to hardware errata. To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
812 /* Scratch pads need to have exclusive access from the primary
813 * or secondary side. Halve the num spads so that each side can
814 * have an equal amount.
816 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
817 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
818 /* Note: The SDOORBELL is the cause of the errata. You REALLY
819 * don't want to touch it.
821 ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
822 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
823 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
824 /* Offset the start of the spads to correspond to whether it is
825 * primary or secondary
827 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
828 ndev->limits.max_spads * 4;
829 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
830 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
831 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
832 ndev->limits.max_mw = SNB_MAX_MW;
834 case NTB_CONN_TRANSPARENT:
835 dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
836 ndev->conn_type = NTB_CONN_TRANSPARENT;
837 /* Scratch pads need to have exclusive access from the primary
838 * or secondary side. Halve the num spads so that each side can
839 * have an equal amount.
841 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
842 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
843 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
844 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
845 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
846 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
847 /* Offset the start of the spads to correspond to whether it is
848 * primary or secondary
850 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
851 ndev->limits.max_spads * 4;
852 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
853 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
855 ndev->limits.max_mw = SNB_MAX_MW;
858 /* Most likely caused by the remote NTB-RP device not being
861 dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
865 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
866 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
867 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
869 ndev->limits.msix_cnt = SNB_MSIX_CNT;
870 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
875 static int ntb_bwd_setup(struct ntb_device *ndev)
880 ndev->hw_type = BWD_HW;
882 rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
886 switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
888 ndev->conn_type = NTB_CONN_B2B;
892 dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n");
896 if (val & BWD_PPD_DEV_TYPE)
897 ndev->dev_type = NTB_DEV_DSD;
899 ndev->dev_type = NTB_DEV_USD;
901 /* Initiate PCI-E link training */
902 rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
903 val | BWD_PPD_INIT_LINK);
907 ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
908 ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
909 ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
910 ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
911 ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
912 ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
913 ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
914 ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
915 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
916 ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
917 ndev->limits.max_mw = BWD_MAX_MW;
918 ndev->limits.max_spads = BWD_MAX_SPADS;
919 ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
920 ndev->limits.msix_cnt = BWD_MSIX_CNT;
921 ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
923 /* Since bwd doesn't have a link interrupt, setup a poll timer */
924 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
925 INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
926 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
931 static int ntb_device_setup(struct ntb_device *ndev)
935 switch (ndev->pdev->device) {
936 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
937 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
938 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
939 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
940 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
941 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
942 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
943 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
944 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
945 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
946 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
947 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
948 rc = ntb_xeon_setup(ndev);
950 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
951 rc = ntb_bwd_setup(ndev);
960 dev_info(&ndev->pdev->dev, "Device Type = %s\n",
961 ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
963 if (ndev->conn_type == NTB_CONN_B2B)
964 /* Enable Bus Master and Memory Space on the secondary side */
965 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
966 ndev->reg_ofs.spci_cmd);
971 static void ntb_device_free(struct ntb_device *ndev)
973 if (ndev->hw_type == BWD_HW) {
974 cancel_delayed_work_sync(&ndev->hb_timer);
975 cancel_delayed_work_sync(&ndev->lr_timer);
979 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
981 struct ntb_db_cb *db_cb = data;
982 struct ntb_device *ndev = db_cb->ndev;
985 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
988 mask = readw(ndev->reg_ofs.ldb_mask);
989 set_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
990 writew(mask, ndev->reg_ofs.ldb_mask);
992 tasklet_schedule(&db_cb->irq_work);
994 /* No need to check for the specific HB irq, any interrupt means
997 ndev->last_ts = jiffies;
999 writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb);
1004 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
1006 struct ntb_db_cb *db_cb = data;
1007 struct ntb_device *ndev = db_cb->ndev;
1010 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
1013 mask = readw(ndev->reg_ofs.ldb_mask);
1014 set_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
1015 writew(mask, ndev->reg_ofs.ldb_mask);
1017 tasklet_schedule(&db_cb->irq_work);
1019 /* On Sandybridge, there are 16 bits in the interrupt register
1020 * but only 4 vectors. So, 5 bits are assigned to the first 3
1021 * vectors, with the 4th having a single bit for link
1024 writew(((1 << ndev->bits_per_vector) - 1) <<
1025 (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb);
1030 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
1031 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
1033 struct ntb_device *ndev = dev;
1036 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
1038 rc = ntb_link_status(ndev);
1040 dev_err(&ndev->pdev->dev, "Error determining link status\n");
1042 /* bit 15 is always the link bit */
1043 writew(1 << SNB_LINK_DB, ndev->reg_ofs.ldb);
1048 static irqreturn_t ntb_interrupt(int irq, void *dev)
1050 struct ntb_device *ndev = dev;
1053 if (ndev->hw_type == BWD_HW) {
1054 u64 ldb = readq(ndev->reg_ofs.ldb);
1056 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb);
1061 bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
1064 u16 ldb = readw(ndev->reg_ofs.ldb);
1066 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb);
1068 if (ldb & SNB_DB_HW_LINK) {
1069 xeon_event_msix_irq(irq, dev);
1070 ldb &= ~SNB_DB_HW_LINK;
1076 xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
1083 static int ntb_setup_snb_msix(struct ntb_device *ndev, int msix_entries)
1085 struct pci_dev *pdev = ndev->pdev;
1086 struct msix_entry *msix;
1089 if (msix_entries < ndev->limits.msix_cnt)
1092 rc = pci_enable_msix_exact(pdev, ndev->msix_entries, msix_entries);
1096 for (i = 0; i < msix_entries; i++) {
1097 msix = &ndev->msix_entries[i];
1098 WARN_ON(!msix->vector);
1100 if (i == msix_entries - 1) {
1101 rc = request_irq(msix->vector,
1102 xeon_event_msix_irq, 0,
1103 "ntb-event-msix", ndev);
1107 rc = request_irq(msix->vector,
1108 xeon_callback_msix_irq, 0,
1109 "ntb-callback-msix",
1116 ndev->num_msix = msix_entries;
1117 ndev->max_cbs = msix_entries - 1;
1123 /* Code never reaches here for entry nr 'ndev->num_msix - 1' */
1124 msix = &ndev->msix_entries[i];
1125 free_irq(msix->vector, &ndev->db_cb[i]);
1128 pci_disable_msix(pdev);
1134 static int ntb_setup_bwd_msix(struct ntb_device *ndev, int msix_entries)
1136 struct pci_dev *pdev = ndev->pdev;
1137 struct msix_entry *msix;
1140 msix_entries = pci_enable_msix_range(pdev, ndev->msix_entries,
1142 if (msix_entries < 0)
1143 return msix_entries;
1145 for (i = 0; i < msix_entries; i++) {
1146 msix = &ndev->msix_entries[i];
1147 WARN_ON(!msix->vector);
1149 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1150 "ntb-callback-msix", &ndev->db_cb[i]);
1155 ndev->num_msix = msix_entries;
1156 ndev->max_cbs = msix_entries;
1162 free_irq(msix->vector, &ndev->db_cb[i]);
1164 pci_disable_msix(pdev);
1170 static int ntb_setup_msix(struct ntb_device *ndev)
1172 struct pci_dev *pdev = ndev->pdev;
1176 msix_entries = pci_msix_vec_count(pdev);
1177 if (msix_entries < 0) {
1180 } else if (msix_entries > ndev->limits.msix_cnt) {
1185 ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1187 if (!ndev->msix_entries) {
1192 for (i = 0; i < msix_entries; i++)
1193 ndev->msix_entries[i].entry = i;
1195 if (ndev->hw_type == BWD_HW)
1196 rc = ntb_setup_bwd_msix(ndev, msix_entries);
1198 rc = ntb_setup_snb_msix(ndev, msix_entries);
1205 kfree(ndev->msix_entries);
1207 dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1211 static int ntb_setup_msi(struct ntb_device *ndev)
1213 struct pci_dev *pdev = ndev->pdev;
1216 rc = pci_enable_msi(pdev);
1220 rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1222 pci_disable_msi(pdev);
1223 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1230 static int ntb_setup_intx(struct ntb_device *ndev)
1232 struct pci_dev *pdev = ndev->pdev;
1237 /* Verify intx is enabled */
1240 rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1248 static int ntb_setup_interrupts(struct ntb_device *ndev)
1252 /* On BWD, disable all interrupts. On SNB, disable all but Link
1253 * Interrupt. The rest will be unmasked as callbacks are registered.
1255 if (ndev->hw_type == BWD_HW)
1256 writeq(~0, ndev->reg_ofs.ldb_mask);
1258 u16 var = 1 << SNB_LINK_DB;
1259 writew(~var, ndev->reg_ofs.ldb_mask);
1262 rc = ntb_setup_msix(ndev);
1266 ndev->bits_per_vector = 1;
1267 ndev->max_cbs = ndev->limits.max_db_bits;
1269 rc = ntb_setup_msi(ndev);
1273 rc = ntb_setup_intx(ndev);
1275 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1283 static void ntb_free_interrupts(struct ntb_device *ndev)
1285 struct pci_dev *pdev = ndev->pdev;
1287 /* mask interrupts */
1288 if (ndev->hw_type == BWD_HW)
1289 writeq(~0, ndev->reg_ofs.ldb_mask);
1291 writew(~0, ndev->reg_ofs.ldb_mask);
1293 if (ndev->num_msix) {
1294 struct msix_entry *msix;
1297 for (i = 0; i < ndev->num_msix; i++) {
1298 msix = &ndev->msix_entries[i];
1299 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1300 free_irq(msix->vector, ndev);
1302 free_irq(msix->vector, &ndev->db_cb[i]);
1304 pci_disable_msix(pdev);
1305 kfree(ndev->msix_entries);
1307 free_irq(pdev->irq, ndev);
1309 if (pci_dev_msi_enabled(pdev))
1310 pci_disable_msi(pdev);
1314 static int ntb_create_callbacks(struct ntb_device *ndev)
1318 /* Chicken-egg issue. We won't know how many callbacks are necessary
1319 * until we see how many MSI-X vectors we get, but these pointers need
1320 * to be passed into the MSI-X register function. So, we allocate the
1321 * max, knowing that they might not all be used, to work around this.
1323 ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1324 sizeof(struct ntb_db_cb),
1329 for (i = 0; i < ndev->limits.max_db_bits; i++) {
1330 ndev->db_cb[i].db_num = i;
1331 ndev->db_cb[i].ndev = ndev;
1337 static void ntb_free_callbacks(struct ntb_device *ndev)
1341 for (i = 0; i < ndev->limits.max_db_bits; i++)
1342 ntb_unregister_db_callback(ndev, i);
1347 static void ntb_setup_debugfs(struct ntb_device *ndev)
1349 if (!debugfs_initialized())
1353 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1355 ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1359 static void ntb_free_debugfs(struct ntb_device *ndev)
1361 debugfs_remove_recursive(ndev->debugfs_dir);
1363 if (debugfs_dir && simple_empty(debugfs_dir)) {
1364 debugfs_remove_recursive(debugfs_dir);
1369 static void ntb_hw_link_up(struct ntb_device *ndev)
1371 if (ndev->conn_type == NTB_CONN_TRANSPARENT)
1372 ntb_link_event(ndev, NTB_LINK_UP);
1376 /* Let's bring the NTB link up */
1377 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1378 ntb_cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
1379 ntb_cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
1380 ntb_cntl |= NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP;
1381 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1385 static void ntb_hw_link_down(struct ntb_device *ndev)
1389 if (ndev->conn_type == NTB_CONN_TRANSPARENT) {
1390 ntb_link_event(ndev, NTB_LINK_DOWN);
1394 /* Bring NTB link down */
1395 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1396 ntb_cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
1397 ntb_cntl &= ~(NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP);
1398 ntb_cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
1399 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1402 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1404 struct ntb_device *ndev;
1407 ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1412 ndev->link_status = NTB_LINK_DOWN;
1413 pci_set_drvdata(pdev, ndev);
1414 ntb_setup_debugfs(ndev);
1416 rc = pci_enable_device(pdev);
1420 pci_set_master(ndev->pdev);
1422 rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1426 ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1427 if (!ndev->reg_base) {
1428 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1433 for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1434 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1436 ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1437 ndev->mw[i].bar_sz);
1438 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1439 (unsigned long long) ndev->mw[i].bar_sz);
1440 if (!ndev->mw[i].vbase) {
1441 dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1448 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1450 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1454 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1457 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1459 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1463 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1466 rc = ntb_device_setup(ndev);
1470 rc = ntb_create_callbacks(ndev);
1474 rc = ntb_setup_interrupts(ndev);
1478 /* The scratchpad registers keep the values between rmmod/insmod,
1481 for (i = 0; i < ndev->limits.max_spads; i++) {
1482 ntb_write_local_spad(ndev, i, 0);
1483 ntb_write_remote_spad(ndev, i, 0);
1486 rc = ntb_transport_init(pdev);
1490 ntb_hw_link_up(ndev);
1495 ntb_free_interrupts(ndev);
1497 ntb_free_callbacks(ndev);
1499 ntb_device_free(ndev);
1501 for (i--; i >= 0; i--)
1502 iounmap(ndev->mw[i].vbase);
1503 iounmap(ndev->reg_base);
1505 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1507 pci_disable_device(pdev);
1509 ntb_free_debugfs(ndev);
1512 dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1516 static void ntb_pci_remove(struct pci_dev *pdev)
1518 struct ntb_device *ndev = pci_get_drvdata(pdev);
1521 ntb_hw_link_down(ndev);
1523 ntb_transport_free(ndev->ntb_transport);
1525 ntb_free_interrupts(ndev);
1526 ntb_free_callbacks(ndev);
1527 ntb_device_free(ndev);
1529 for (i = 0; i < NTB_MAX_NUM_MW; i++)
1530 iounmap(ndev->mw[i].vbase);
1532 iounmap(ndev->reg_base);
1533 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1534 pci_disable_device(pdev);
1535 ntb_free_debugfs(ndev);
1539 static struct pci_driver ntb_pci_driver = {
1540 .name = KBUILD_MODNAME,
1541 .id_table = ntb_pci_tbl,
1542 .probe = ntb_pci_probe,
1543 .remove = ntb_pci_remove,
1545 module_pci_driver(ntb_pci_driver);