2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Intel PCIe NTB Linux driver
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
48 #include <linux/debugfs.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/random.h>
55 #include <linux/slab.h>
59 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
60 #define NTB_VER "0.25"
62 MODULE_DESCRIPTION(NTB_NAME);
63 MODULE_VERSION(NTB_VER);
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_AUTHOR("Intel Corporation");
67 static bool xeon_errata_workaround = true;
68 module_param(xeon_errata_workaround, bool, 0644);
69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
87 static struct dentry *debugfs_dir;
89 #define BWD_LINK_RECOVERY_TIME 500
91 /* Translate memory window 0,1 to BAR 2,4 */
92 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
95 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
96 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
97 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_CLASSIC_JSF)},
98 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_RP_JSF)},
99 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_RP_SNB)},
100 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
101 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_CLASSIC_SNB)},
104 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
107 * ntb_register_event_callback() - register event callback
108 * @ndev: pointer to ntb_device instance
109 * @func: callback function to register
111 * This function registers a callback for any HW driver events such as link
112 * up/down, power management notices and etc.
114 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
116 int ntb_register_event_callback(struct ntb_device *ndev,
117 void (*func)(void *handle, enum ntb_hw_event event))
122 ndev->event_cb = func;
128 * ntb_unregister_event_callback() - unregisters the event callback
129 * @ndev: pointer to ntb_device instance
131 * This function unregisters the existing callback from transport
133 void ntb_unregister_event_callback(struct ntb_device *ndev)
135 ndev->event_cb = NULL;
139 * ntb_register_db_callback() - register a callback for doorbell interrupt
140 * @ndev: pointer to ntb_device instance
141 * @idx: doorbell index to register callback, zero based
142 * @func: callback function to register
144 * This function registers a callback function for the doorbell interrupt
145 * on the primary side. The function will unmask the doorbell as well to
148 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
150 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
151 void *data, void (*func)(void *data, int db_num))
155 if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
156 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
160 ndev->db_cb[idx].callback = func;
161 ndev->db_cb[idx].data = data;
163 /* unmask interrupt */
164 mask = readw(ndev->reg_ofs.pdb_mask);
165 clear_bit(idx * ndev->bits_per_vector, &mask);
166 writew(mask, ndev->reg_ofs.pdb_mask);
172 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
173 * @ndev: pointer to ntb_device instance
174 * @idx: doorbell index to register callback, zero based
176 * This function unregisters a callback function for the doorbell interrupt
177 * on the primary side. The function will also mask the said doorbell.
179 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
183 if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
186 mask = readw(ndev->reg_ofs.pdb_mask);
187 set_bit(idx * ndev->bits_per_vector, &mask);
188 writew(mask, ndev->reg_ofs.pdb_mask);
190 ndev->db_cb[idx].callback = NULL;
194 * ntb_find_transport() - find the transport pointer
195 * @transport: pointer to pci device
197 * Given the pci device pointer, return the transport pointer passed in when
198 * the transport attached when it was inited.
200 * RETURNS: pointer to transport.
202 void *ntb_find_transport(struct pci_dev *pdev)
204 struct ntb_device *ndev = pci_get_drvdata(pdev);
205 return ndev->ntb_transport;
209 * ntb_register_transport() - Register NTB transport with NTB HW driver
210 * @transport: transport identifier
212 * This function allows a transport to reserve the hardware driver for
215 * RETURNS: pointer to ntb_device, NULL on error.
217 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
219 struct ntb_device *ndev = pci_get_drvdata(pdev);
221 if (ndev->ntb_transport)
224 ndev->ntb_transport = transport;
229 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
230 * @ndev - ntb_device of the transport to be freed
232 * This function unregisters the transport from the HW driver and performs any
233 * necessary cleanups.
235 void ntb_unregister_transport(struct ntb_device *ndev)
239 if (!ndev->ntb_transport)
242 for (i = 0; i < ndev->max_cbs; i++)
243 ntb_unregister_db_callback(ndev, i);
245 ntb_unregister_event_callback(ndev);
246 ndev->ntb_transport = NULL;
250 * ntb_write_local_spad() - write to the secondary scratchpad register
251 * @ndev: pointer to ntb_device instance
252 * @idx: index to the scratchpad register, 0 based
253 * @val: the data value to put into the register
255 * This function allows writing of a 32bit value to the indexed scratchpad
256 * register. This writes over the data mirrored to the local scratchpad register
257 * by the remote system.
259 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
261 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
263 if (idx >= ndev->limits.max_spads)
266 dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
268 writel(val, ndev->reg_ofs.spad_read + idx * 4);
274 * ntb_read_local_spad() - read from the primary scratchpad register
275 * @ndev: pointer to ntb_device instance
276 * @idx: index to scratchpad register, 0 based
277 * @val: pointer to 32bit integer for storing the register value
279 * This function allows reading of the 32bit scratchpad register on
280 * the primary (internal) side. This allows the local system to read data
281 * written and mirrored to the scratchpad register by the remote system.
283 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
285 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
287 if (idx >= ndev->limits.max_spads)
290 *val = readl(ndev->reg_ofs.spad_write + idx * 4);
291 dev_dbg(&ndev->pdev->dev,
292 "Reading %x from local scratch pad index %d\n", *val, idx);
298 * ntb_write_remote_spad() - write to the secondary scratchpad register
299 * @ndev: pointer to ntb_device instance
300 * @idx: index to the scratchpad register, 0 based
301 * @val: the data value to put into the register
303 * This function allows writing of a 32bit value to the indexed scratchpad
304 * register. The register resides on the secondary (external) side. This allows
305 * the local system to write data to be mirrored to the remote systems
306 * scratchpad register.
308 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
310 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
312 if (idx >= ndev->limits.max_spads)
315 dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
317 writel(val, ndev->reg_ofs.spad_write + idx * 4);
323 * ntb_read_remote_spad() - read from the primary scratchpad register
324 * @ndev: pointer to ntb_device instance
325 * @idx: index to scratchpad register, 0 based
326 * @val: pointer to 32bit integer for storing the register value
328 * This function allows reading of the 32bit scratchpad register on
329 * the primary (internal) side. This alloows the local system to read the data
330 * it wrote to be mirrored on the remote system.
332 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
334 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
336 if (idx >= ndev->limits.max_spads)
339 *val = readl(ndev->reg_ofs.spad_read + idx * 4);
340 dev_dbg(&ndev->pdev->dev,
341 "Reading %x from remote scratch pad index %d\n", *val, idx);
347 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
348 * @ndev: pointer to ntb_device instance
349 * @mw: memory window number
351 * This function provides the base virtual address of the memory window
354 * RETURNS: pointer to virtual address, or NULL on error.
356 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
358 if (mw >= ntb_max_mw(ndev))
361 return ndev->mw[mw].vbase;
365 * ntb_get_mw_size() - return size of NTB memory window
366 * @ndev: pointer to ntb_device instance
367 * @mw: memory window number
369 * This function provides the physical size of the memory window specified
371 * RETURNS: the size of the memory window or zero on error
373 resource_size_t ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
375 if (mw >= ntb_max_mw(ndev))
378 return ndev->mw[mw].bar_sz;
382 * ntb_set_mw_addr - set the memory window address
383 * @ndev: pointer to ntb_device instance
384 * @mw: memory window number
385 * @addr: base address for data
387 * This function sets the base physical address of the memory window. This
388 * memory address is where data from the remote system will be transfered into
389 * or out of depending on how the transport is configured.
391 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
393 if (mw >= ntb_max_mw(ndev))
396 dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
399 ndev->mw[mw].phys_addr = addr;
401 switch (MW_TO_BAR(mw)) {
403 writeq(addr, ndev->reg_ofs.sbar2_xlat);
406 writeq(addr, ndev->reg_ofs.sbar4_xlat);
412 * ntb_ring_sdb() - Set the doorbell on the secondary/external side
413 * @ndev: pointer to ntb_device instance
414 * @db: doorbell to ring
416 * This function allows triggering of a doorbell on the secondary/external
417 * side that will initiate an interrupt on the remote host
419 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
421 void ntb_ring_sdb(struct ntb_device *ndev, unsigned int db)
423 dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
425 if (ndev->hw_type == BWD_HW)
426 writeq((u64) 1 << db, ndev->reg_ofs.sdb);
428 writew(((1 << ndev->bits_per_vector) - 1) <<
429 (db * ndev->bits_per_vector), ndev->reg_ofs.sdb);
432 static void bwd_recover_link(struct ntb_device *ndev)
436 /* Driver resets the NTB ModPhy lanes - magic! */
437 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
438 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
439 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
440 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
442 /* Driver waits 100ms to allow the NTB ModPhy to settle */
445 /* Clear AER Errors, write to clear */
446 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
447 dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
448 status &= PCI_ERR_COR_REP_ROLL;
449 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
451 /* Clear unexpected electrical idle event in LTSSM, write to clear */
452 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
453 dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
454 status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
455 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
457 /* Clear DeSkew Buffer error, write to clear */
458 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
459 dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
460 status |= BWD_DESKEWSTS_DBERR;
461 writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
463 status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
464 dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
465 status &= BWD_IBIST_ERR_OFLOW;
466 writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
468 /* Releases the NTB state machine to allow the link to retrain */
469 status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
470 dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
471 status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
472 writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
475 static void ntb_link_event(struct ntb_device *ndev, int link_state)
479 if (ndev->link_status == link_state)
482 if (link_state == NTB_LINK_UP) {
485 dev_info(&ndev->pdev->dev, "Link Up\n");
486 ndev->link_status = NTB_LINK_UP;
487 event = NTB_EVENT_HW_LINK_UP;
489 if (ndev->hw_type == BWD_HW)
490 status = readw(ndev->reg_ofs.lnk_stat);
492 int rc = pci_read_config_word(ndev->pdev,
493 SNB_LINK_STATUS_OFFSET,
499 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
500 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
501 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
502 ndev->link_width, ndev->link_speed);
504 dev_info(&ndev->pdev->dev, "Link Down\n");
505 ndev->link_status = NTB_LINK_DOWN;
506 event = NTB_EVENT_HW_LINK_DOWN;
507 /* Don't modify link width/speed, we need it in link recovery */
510 /* notify the upper layer if we have an event change */
512 ndev->event_cb(ndev->ntb_transport, event);
515 static int ntb_link_status(struct ntb_device *ndev)
519 if (ndev->hw_type == BWD_HW) {
522 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
523 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
524 link_state = NTB_LINK_DOWN;
526 link_state = NTB_LINK_UP;
531 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
536 if (status & NTB_LINK_STATUS_ACTIVE)
537 link_state = NTB_LINK_UP;
539 link_state = NTB_LINK_DOWN;
542 ntb_link_event(ndev, link_state);
547 static void bwd_link_recovery(struct work_struct *work)
549 struct ntb_device *ndev = container_of(work, struct ntb_device,
553 bwd_recover_link(ndev);
554 /* There is a potential race between the 2 NTB devices recovering at the
555 * same time. If the times are the same, the link will not recover and
556 * the driver will be stuck in this loop forever. Add a random interval
557 * to the recovery time to prevent this race.
559 msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
561 status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
562 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
565 status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
566 if (status32 & BWD_IBIST_ERR_OFLOW)
569 status32 = readl(ndev->reg_ofs.lnk_cntl);
570 if (!(status32 & BWD_CNTL_LINK_DOWN)) {
571 unsigned char speed, width;
574 status16 = readw(ndev->reg_ofs.lnk_stat);
575 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
576 speed = (status16 & NTB_LINK_SPEED_MASK);
577 if (ndev->link_width != width || ndev->link_speed != speed)
581 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
585 schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
588 /* BWD doesn't have link status interrupt, poll on that platform */
589 static void bwd_link_poll(struct work_struct *work)
591 struct ntb_device *ndev = container_of(work, struct ntb_device,
593 unsigned long ts = jiffies;
595 /* If we haven't gotten an interrupt in a while, check the BWD link
598 if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
599 int rc = ntb_link_status(ndev);
601 dev_err(&ndev->pdev->dev,
602 "Error determining link status\n");
604 /* Check to see if a link error is the cause of the link down */
605 if (ndev->link_status == NTB_LINK_DOWN) {
606 u32 status32 = readl(ndev->reg_base +
607 BWD_LTSSMSTATEJMP_OFFSET);
608 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
609 schedule_delayed_work(&ndev->lr_timer, 0);
615 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
618 static int ntb_xeon_setup(struct ntb_device *ndev)
623 ndev->hw_type = SNB_HW;
625 rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
629 switch (val & SNB_PPD_CONN_TYPE) {
631 ndev->conn_type = NTB_CONN_B2B;
633 case NTB_CONN_CLASSIC:
636 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
640 if (val & SNB_PPD_DEV_TYPE)
641 ndev->dev_type = NTB_DEV_USD;
643 ndev->dev_type = NTB_DEV_DSD;
645 ndev->reg_ofs.pdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
646 ndev->reg_ofs.pdb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
647 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
648 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
649 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
650 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_LINK_STATUS_OFFSET;
651 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
652 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
654 /* There is a Xeon hardware errata related to writes to
655 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
656 * to NTB MMIO Space, which may hang the system. To workaround
657 * this use the second memory window to access the interrupt and
658 * scratch pad registers on the remote system.
660 if (xeon_errata_workaround) {
661 if (!ndev->mw[1].bar_sz)
664 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
665 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
667 ndev->reg_ofs.sdb = ndev->mw[1].vbase +
668 SNB_PDOORBELL_OFFSET;
670 /* Set the Limit register to 4k, the minimum size, to
671 * prevent an illegal access
673 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
674 SNB_PBAR4LMT_OFFSET);
676 ndev->limits.max_mw = SNB_MAX_MW;
677 ndev->reg_ofs.spad_write = ndev->reg_base +
679 ndev->reg_ofs.sdb = ndev->reg_base +
680 SNB_B2B_DOORBELL_OFFSET;
682 /* Disable the Limit register, just incase it is set to
685 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
688 /* The Xeon errata workaround requires setting SBAR Base
689 * addresses to known values, so that the PBAR XLAT can be
690 * pointed at SBAR0 of the remote system.
692 if (ndev->dev_type == NTB_DEV_USD) {
693 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
694 SNB_PBAR2XLAT_OFFSET);
695 if (xeon_errata_workaround)
696 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
697 SNB_PBAR4XLAT_OFFSET);
699 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
700 SNB_PBAR4XLAT_OFFSET);
701 /* B2B_XLAT_OFFSET is a 64bit register, but can
702 * only take 32bit writes
704 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
705 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
706 writel(SNB_MBAR01_DSD_ADDR >> 32,
707 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
710 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
711 SNB_SBAR0BASE_OFFSET);
712 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
713 SNB_SBAR2BASE_OFFSET);
714 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
715 SNB_SBAR4BASE_OFFSET);
717 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
718 SNB_PBAR2XLAT_OFFSET);
719 if (xeon_errata_workaround)
720 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
721 SNB_PBAR4XLAT_OFFSET);
723 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
724 SNB_PBAR4XLAT_OFFSET);
725 /* B2B_XLAT_OFFSET is a 64bit register, but can
726 * only take 32bit writes
728 writel(SNB_MBAR01_USD_ADDR & 0xffffffff,
729 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
730 writel(SNB_MBAR01_USD_ADDR >> 32,
731 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
733 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
734 SNB_SBAR0BASE_OFFSET);
735 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
736 SNB_SBAR2BASE_OFFSET);
737 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
738 SNB_SBAR4BASE_OFFSET);
741 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
742 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
743 ndev->limits.msix_cnt = SNB_MSIX_CNT;
744 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
749 static int ntb_bwd_setup(struct ntb_device *ndev)
754 ndev->hw_type = BWD_HW;
756 rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
760 switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
762 ndev->conn_type = NTB_CONN_B2B;
766 dev_err(&ndev->pdev->dev, "Only B2B supported at this time\n");
770 if (val & BWD_PPD_DEV_TYPE)
771 ndev->dev_type = NTB_DEV_DSD;
773 ndev->dev_type = NTB_DEV_USD;
775 /* Initiate PCI-E link training */
776 rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
777 val | BWD_PPD_INIT_LINK);
781 ndev->reg_ofs.pdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
782 ndev->reg_ofs.pdb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
783 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
784 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
785 ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
786 ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
787 ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
788 ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
790 if (ndev->conn_type == NTB_CONN_B2B) {
791 ndev->reg_ofs.sdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
792 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
793 ndev->limits.max_spads = BWD_MAX_SPADS;
795 ndev->reg_ofs.sdb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
796 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_SPAD_OFFSET;
797 ndev->limits.max_spads = BWD_MAX_COMPAT_SPADS;
800 ndev->limits.max_mw = BWD_MAX_MW;
801 ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
802 ndev->limits.msix_cnt = BWD_MSIX_CNT;
803 ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
805 /* Since bwd doesn't have a link interrupt, setup a poll timer */
806 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
807 INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
808 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
813 static int ntb_device_setup(struct ntb_device *ndev)
817 switch (ndev->pdev->device) {
818 case PCI_DEVICE_ID_INTEL_NTB_2ND_SNB:
819 case PCI_DEVICE_ID_INTEL_NTB_RP_JSF:
820 case PCI_DEVICE_ID_INTEL_NTB_RP_SNB:
821 case PCI_DEVICE_ID_INTEL_NTB_CLASSIC_JSF:
822 case PCI_DEVICE_ID_INTEL_NTB_CLASSIC_SNB:
823 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
824 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
825 rc = ntb_xeon_setup(ndev);
827 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
828 rc = ntb_bwd_setup(ndev);
837 dev_info(&ndev->pdev->dev, "Device Type = %s\n",
838 ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
840 /* Enable Bus Master and Memory Space on the secondary side */
841 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, ndev->reg_ofs.spci_cmd);
846 static void ntb_device_free(struct ntb_device *ndev)
848 if (ndev->hw_type == BWD_HW) {
849 cancel_delayed_work_sync(&ndev->hb_timer);
850 cancel_delayed_work_sync(&ndev->lr_timer);
854 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
856 struct ntb_db_cb *db_cb = data;
857 struct ntb_device *ndev = db_cb->ndev;
859 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
863 db_cb->callback(db_cb->data, db_cb->db_num);
865 /* No need to check for the specific HB irq, any interrupt means
868 ndev->last_ts = jiffies;
870 writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.pdb);
875 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
877 struct ntb_db_cb *db_cb = data;
878 struct ntb_device *ndev = db_cb->ndev;
880 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
884 db_cb->callback(db_cb->data, db_cb->db_num);
886 /* On Sandybridge, there are 16 bits in the interrupt register
887 * but only 4 vectors. So, 5 bits are assigned to the first 3
888 * vectors, with the 4th having a single bit for link
891 writew(((1 << ndev->bits_per_vector) - 1) <<
892 (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.pdb);
897 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
898 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
900 struct ntb_device *ndev = dev;
903 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
905 rc = ntb_link_status(ndev);
907 dev_err(&ndev->pdev->dev, "Error determining link status\n");
909 /* bit 15 is always the link bit */
910 writew(1 << ndev->limits.max_db_bits, ndev->reg_ofs.pdb);
915 static irqreturn_t ntb_interrupt(int irq, void *dev)
917 struct ntb_device *ndev = dev;
920 if (ndev->hw_type == BWD_HW) {
921 u64 pdb = readq(ndev->reg_ofs.pdb);
923 dev_dbg(&ndev->pdev->dev, "irq %d - pdb = %Lx\n", irq, pdb);
928 bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
931 u16 pdb = readw(ndev->reg_ofs.pdb);
933 dev_dbg(&ndev->pdev->dev, "irq %d - pdb = %x sdb %x\n", irq,
934 pdb, readw(ndev->reg_ofs.sdb));
936 if (pdb & SNB_DB_HW_LINK) {
937 xeon_event_msix_irq(irq, dev);
938 pdb &= ~SNB_DB_HW_LINK;
944 xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
951 static int ntb_setup_msix(struct ntb_device *ndev)
953 struct pci_dev *pdev = ndev->pdev;
954 struct msix_entry *msix;
959 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
965 rc = pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &val);
969 msix_entries = msix_table_size(val);
970 if (msix_entries > ndev->limits.msix_cnt) {
975 ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
977 if (!ndev->msix_entries) {
982 for (i = 0; i < msix_entries; i++)
983 ndev->msix_entries[i].entry = i;
985 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
989 /* On SNB, the link interrupt is always tied to 4th vector. If
990 * we can't get all 4, then we can't use MSI-X.
992 if (ndev->hw_type != BWD_HW) {
998 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
1003 for (i = 0; i < msix_entries; i++) {
1004 msix = &ndev->msix_entries[i];
1005 WARN_ON(!msix->vector);
1007 /* Use the last MSI-X vector for Link status */
1008 if (ndev->hw_type == BWD_HW) {
1009 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1010 "ntb-callback-msix", &ndev->db_cb[i]);
1014 if (i == msix_entries - 1) {
1015 rc = request_irq(msix->vector,
1016 xeon_event_msix_irq, 0,
1017 "ntb-event-msix", ndev);
1021 rc = request_irq(msix->vector,
1022 xeon_callback_msix_irq, 0,
1023 "ntb-callback-msix",
1031 ndev->num_msix = msix_entries;
1032 if (ndev->hw_type == BWD_HW)
1033 ndev->max_cbs = msix_entries;
1035 ndev->max_cbs = msix_entries - 1;
1041 msix = &ndev->msix_entries[i];
1042 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1043 free_irq(msix->vector, ndev);
1045 free_irq(msix->vector, &ndev->db_cb[i]);
1047 pci_disable_msix(pdev);
1049 kfree(ndev->msix_entries);
1050 dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1056 static int ntb_setup_msi(struct ntb_device *ndev)
1058 struct pci_dev *pdev = ndev->pdev;
1061 rc = pci_enable_msi(pdev);
1065 rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1067 pci_disable_msi(pdev);
1068 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1075 static int ntb_setup_intx(struct ntb_device *ndev)
1077 struct pci_dev *pdev = ndev->pdev;
1082 /* Verify intx is enabled */
1085 rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1093 static int ntb_setup_interrupts(struct ntb_device *ndev)
1097 /* On BWD, disable all interrupts. On SNB, disable all but Link
1098 * Interrupt. The rest will be unmasked as callbacks are registered.
1100 if (ndev->hw_type == BWD_HW)
1101 writeq(~0, ndev->reg_ofs.pdb_mask);
1103 writew(~(1 << ndev->limits.max_db_bits),
1104 ndev->reg_ofs.pdb_mask);
1106 rc = ntb_setup_msix(ndev);
1110 ndev->bits_per_vector = 1;
1111 ndev->max_cbs = ndev->limits.max_db_bits;
1113 rc = ntb_setup_msi(ndev);
1117 rc = ntb_setup_intx(ndev);
1119 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1127 static void ntb_free_interrupts(struct ntb_device *ndev)
1129 struct pci_dev *pdev = ndev->pdev;
1131 /* mask interrupts */
1132 if (ndev->hw_type == BWD_HW)
1133 writeq(~0, ndev->reg_ofs.pdb_mask);
1135 writew(~0, ndev->reg_ofs.pdb_mask);
1137 if (ndev->num_msix) {
1138 struct msix_entry *msix;
1141 for (i = 0; i < ndev->num_msix; i++) {
1142 msix = &ndev->msix_entries[i];
1143 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1144 free_irq(msix->vector, ndev);
1146 free_irq(msix->vector, &ndev->db_cb[i]);
1148 pci_disable_msix(pdev);
1150 free_irq(pdev->irq, ndev);
1152 if (pci_dev_msi_enabled(pdev))
1153 pci_disable_msi(pdev);
1157 static int ntb_create_callbacks(struct ntb_device *ndev)
1161 /* Checken-egg issue. We won't know how many callbacks are necessary
1162 * until we see how many MSI-X vectors we get, but these pointers need
1163 * to be passed into the MSI-X register fucntion. So, we allocate the
1164 * max, knowing that they might not all be used, to work around this.
1166 ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1167 sizeof(struct ntb_db_cb),
1172 for (i = 0; i < ndev->limits.max_db_bits; i++) {
1173 ndev->db_cb[i].db_num = i;
1174 ndev->db_cb[i].ndev = ndev;
1180 static void ntb_free_callbacks(struct ntb_device *ndev)
1184 for (i = 0; i < ndev->limits.max_db_bits; i++)
1185 ntb_unregister_db_callback(ndev, i);
1190 static void ntb_setup_debugfs(struct ntb_device *ndev)
1192 if (!debugfs_initialized())
1196 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1198 ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1202 static void ntb_free_debugfs(struct ntb_device *ndev)
1204 debugfs_remove_recursive(ndev->debugfs_dir);
1206 if (debugfs_dir && simple_empty(debugfs_dir)) {
1207 debugfs_remove_recursive(debugfs_dir);
1212 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1214 struct ntb_device *ndev;
1217 ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1222 ndev->link_status = NTB_LINK_DOWN;
1223 pci_set_drvdata(pdev, ndev);
1224 ntb_setup_debugfs(ndev);
1226 rc = pci_enable_device(pdev);
1230 pci_set_master(ndev->pdev);
1232 rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1236 ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1237 if (!ndev->reg_base) {
1238 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1243 for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1244 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1246 ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1247 ndev->mw[i].bar_sz);
1248 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1249 pci_resource_len(pdev, MW_TO_BAR(i)));
1250 if (!ndev->mw[i].vbase) {
1251 dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1258 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1260 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1264 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1267 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1269 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1273 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1276 rc = ntb_device_setup(ndev);
1280 rc = ntb_create_callbacks(ndev);
1284 rc = ntb_setup_interrupts(ndev);
1288 /* The scratchpad registers keep the values between rmmod/insmod,
1291 for (i = 0; i < ndev->limits.max_spads; i++) {
1292 ntb_write_local_spad(ndev, i, 0);
1293 ntb_write_remote_spad(ndev, i, 0);
1296 rc = ntb_transport_init(pdev);
1300 /* Let's bring the NTB link up */
1301 writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1302 ndev->reg_ofs.lnk_cntl);
1307 ntb_free_interrupts(ndev);
1309 ntb_free_callbacks(ndev);
1311 ntb_device_free(ndev);
1313 for (i--; i >= 0; i--)
1314 iounmap(ndev->mw[i].vbase);
1315 iounmap(ndev->reg_base);
1317 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1319 pci_disable_device(pdev);
1321 ntb_free_debugfs(ndev);
1324 dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1328 static void ntb_pci_remove(struct pci_dev *pdev)
1330 struct ntb_device *ndev = pci_get_drvdata(pdev);
1334 /* Bring NTB link down */
1335 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1336 ntb_cntl |= NTB_LINK_DISABLE;
1337 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1339 ntb_transport_free(ndev->ntb_transport);
1341 ntb_free_interrupts(ndev);
1342 ntb_free_callbacks(ndev);
1343 ntb_device_free(ndev);
1345 for (i = 0; i < NTB_MAX_NUM_MW; i++)
1346 iounmap(ndev->mw[i].vbase);
1348 iounmap(ndev->reg_base);
1349 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1350 pci_disable_device(pdev);
1351 ntb_free_debugfs(ndev);
1355 static struct pci_driver ntb_pci_driver = {
1356 .name = KBUILD_MODNAME,
1357 .id_table = ntb_pci_tbl,
1358 .probe = ntb_pci_probe,
1359 .remove = ntb_pci_remove,
1361 module_pci_driver(ntb_pci_driver);