2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2015 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2015 Intel Corporation. All rights reserved.
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18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
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41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * PCIe NTB Perf Linux driver
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/kthread.h>
50 #include <linux/time.h>
51 #include <linux/timer.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/pci.h>
54 #include <linux/slab.h>
55 #include <linux/spinlock.h>
56 #include <linux/debugfs.h>
57 #include <linux/dmaengine.h>
58 #include <linux/delay.h>
59 #include <linux/sizes.h>
60 #include <linux/ntb.h>
62 #define DRIVER_NAME "ntb_perf"
63 #define DRIVER_DESCRIPTION "PCIe NTB Performance Measurement Tool"
65 #define DRIVER_LICENSE "Dual BSD/GPL"
66 #define DRIVER_VERSION "1.0"
67 #define DRIVER_AUTHOR "Dave Jiang <dave.jiang@intel.com>"
69 #define PERF_LINK_DOWN_TIMEOUT 10
70 #define PERF_VERSION 0xffff0001
71 #define MAX_THREADS 32
72 #define MAX_TEST_SIZE SZ_1M
74 #define DMA_OUT_RESOURCE_TO 50
75 #define DMA_RETRIES 20
76 #define SZ_4G (1ULL << 32)
77 #define MAX_SEG_ORDER 20 /* no larger than 1M for kmalloc buffer */
79 MODULE_LICENSE(DRIVER_LICENSE);
80 MODULE_VERSION(DRIVER_VERSION);
81 MODULE_AUTHOR(DRIVER_AUTHOR);
82 MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
84 static struct dentry *perf_debugfs_dir;
86 static unsigned long max_mw_size;
87 module_param(max_mw_size, ulong, 0644);
88 MODULE_PARM_DESC(max_mw_size, "Limit size of large memory windows");
90 static unsigned int seg_order = 19; /* 512K */
91 module_param(seg_order, uint, 0644);
92 MODULE_PARM_DESC(seg_order, "size order [n^2] of buffer segment for testing");
94 static unsigned int run_order = 32; /* 4G */
95 module_param(run_order, uint, 0644);
96 MODULE_PARM_DESC(run_order, "size order [n^2] of total data to transfer");
98 static bool use_dma; /* default to 0 */
99 module_param(use_dma, bool, 0644);
100 MODULE_PARM_DESC(use_dma, "Using DMA engine to measure performance");
103 phys_addr_t phys_addr;
104 resource_size_t phys_size;
105 resource_size_t xlat_align;
106 resource_size_t xlat_align_size;
117 struct task_struct *thread;
118 struct perf_ctx *perf;
120 struct dma_chan *dma_chan;
123 void *srcs[MAX_SRCS];
131 struct work_struct link_cleanup;
132 struct delayed_work link_work;
133 struct dentry *debugfs_node_dir;
134 struct dentry *debugfs_run;
135 struct dentry *debugfs_threads;
138 struct pthr_ctx pthr_ctx[MAX_THREADS];
151 static void perf_link_event(void *ctx)
153 struct perf_ctx *perf = ctx;
155 if (ntb_link_is_up(perf->ntb, NULL, NULL) == 1)
156 schedule_delayed_work(&perf->link_work, 2*HZ);
158 schedule_work(&perf->link_cleanup);
161 static void perf_db_event(void *ctx, int vec)
163 struct perf_ctx *perf = ctx;
164 u64 db_bits, db_mask;
166 db_mask = ntb_db_vector_mask(perf->ntb, vec);
167 db_bits = ntb_db_read(perf->ntb);
169 dev_dbg(&perf->ntb->dev, "doorbell vec %d mask %#llx bits %#llx\n",
170 vec, db_mask, db_bits);
173 static const struct ntb_ctx_ops perf_ops = {
174 .link_event = perf_link_event,
175 .db_event = perf_db_event,
178 static void perf_copy_callback(void *data)
180 struct pthr_ctx *pctx = data;
182 atomic_dec(&pctx->dma_sync);
185 static ssize_t perf_copy(struct pthr_ctx *pctx, char __iomem *dst,
186 char *src, size_t size)
188 struct perf_ctx *perf = pctx->perf;
189 struct dma_async_tx_descriptor *txd;
190 struct dma_chan *chan = pctx->dma_chan;
191 struct dma_device *device;
192 struct dmaengine_unmap_data *unmap;
194 size_t src_off, dst_off;
195 struct perf_mw *mw = &perf->mw;
197 void __iomem *dst_vaddr;
202 memcpy_toio(dst, src, size);
207 dev_err(&perf->ntb->dev, "DMA engine does not exist\n");
211 device = chan->device;
212 src_off = (uintptr_t)src & ~PAGE_MASK;
213 dst_off = (uintptr_t __force)dst & ~PAGE_MASK;
215 if (!is_dma_copy_aligned(device, src_off, dst_off, size))
220 dst_phys = mw->phys_addr + (dst_vaddr - vbase);
222 unmap = dmaengine_get_unmap_data(device->dev, 1, GFP_NOWAIT);
227 unmap->addr[0] = dma_map_page(device->dev, virt_to_page(src),
228 src_off, size, DMA_TO_DEVICE);
229 if (dma_mapping_error(device->dev, unmap->addr[0]))
235 txd = device->device_prep_dma_memcpy(chan, dst_phys,
237 size, DMA_PREP_INTERRUPT);
239 set_current_state(TASK_INTERRUPTIBLE);
240 schedule_timeout(DMA_OUT_RESOURCE_TO);
242 } while (!txd && (++retries < DMA_RETRIES));
245 pctx->dma_prep_err++;
249 txd->callback = perf_copy_callback;
250 txd->callback_param = pctx;
251 dma_set_unmap(txd, unmap);
253 cookie = dmaengine_submit(txd);
254 if (dma_submit_error(cookie))
257 atomic_inc(&pctx->dma_sync);
258 dma_async_issue_pending(chan);
263 dmaengine_unmap_put(unmap);
265 dmaengine_unmap_put(unmap);
269 static int perf_move_data(struct pthr_ctx *pctx, char __iomem *dst, char *src,
270 u64 buf_size, u64 win_size, u64 total)
272 int chunks, total_chunks, i;
273 int copied_chunks = 0;
274 u64 copied = 0, result;
275 char __iomem *tmp = dst;
277 ktime_t kstart, kstop, kdiff;
279 chunks = div64_u64(win_size, buf_size);
280 total_chunks = div64_u64(total, buf_size);
281 kstart = ktime_get();
283 for (i = 0; i < total_chunks; i++) {
284 result = perf_copy(pctx, tmp, src, buf_size);
287 if (copied_chunks == chunks) {
293 /* Probably should schedule every 4GB to prevent soft hang. */
294 if (((copied % SZ_4G) == 0) && !use_dma) {
295 set_current_state(TASK_INTERRUPTIBLE);
301 pr_info("%s: All DMA descriptors submitted\n", current->comm);
302 while (atomic_read(&pctx->dma_sync) != 0)
307 kdiff = ktime_sub(kstop, kstart);
308 diff_us = ktime_to_us(kdiff);
310 pr_info("%s: copied %llu bytes\n", current->comm, copied);
312 pr_info("%s: lasted %llu usecs\n", current->comm, diff_us);
314 perf = div64_u64(copied, diff_us);
316 pr_info("%s: MBytes/s: %llu\n", current->comm, perf);
321 static bool perf_dma_filter_fn(struct dma_chan *chan, void *node)
323 return dev_to_node(&chan->dev->device) == (int)(unsigned long)node;
326 static int ntb_perf_thread(void *data)
328 struct pthr_ctx *pctx = data;
329 struct perf_ctx *perf = pctx->perf;
330 struct pci_dev *pdev = perf->ntb->pdev;
331 struct perf_mw *mw = &perf->mw;
333 u64 win_size, buf_size, total;
336 struct dma_chan *dma_chan = NULL;
338 pr_info("kthread %s starting...\n", current->comm);
340 node = dev_to_node(&pdev->dev);
342 if (use_dma && !pctx->dma_chan) {
343 dma_cap_mask_t dma_mask;
345 dma_cap_zero(dma_mask);
346 dma_cap_set(DMA_MEMCPY, dma_mask);
347 dma_chan = dma_request_channel(dma_mask, perf_dma_filter_fn,
348 (void *)(unsigned long)node);
350 pr_warn("%s: cannot acquire DMA channel, quitting\n",
354 pctx->dma_chan = dma_chan;
357 for (i = 0; i < MAX_SRCS; i++) {
358 pctx->srcs[i] = kmalloc_node(MAX_TEST_SIZE, GFP_KERNEL, node);
359 if (!pctx->srcs[i]) {
365 win_size = mw->phys_size;
366 buf_size = 1ULL << seg_order;
367 total = 1ULL << run_order;
369 if (buf_size > MAX_TEST_SIZE)
370 buf_size = MAX_TEST_SIZE;
372 dst = (char __iomem *)mw->vbase;
374 atomic_inc(&perf->tsync);
375 while (atomic_read(&perf->tsync) != perf->perf_threads)
378 src = pctx->srcs[pctx->src_idx];
379 pctx->src_idx = (pctx->src_idx + 1) & (MAX_SRCS - 1);
381 rc = perf_move_data(pctx, dst, src, buf_size, win_size, total);
383 atomic_dec(&perf->tsync);
386 pr_err("%s: failed\n", current->comm);
391 for (i = 0; i < MAX_SRCS; i++) {
392 kfree(pctx->srcs[i]);
393 pctx->srcs[i] = NULL;
399 for (i = 0; i < MAX_SRCS; i++) {
400 kfree(pctx->srcs[i]);
401 pctx->srcs[i] = NULL;
405 dma_release_channel(dma_chan);
406 pctx->dma_chan = NULL;
412 static void perf_free_mw(struct perf_ctx *perf)
414 struct perf_mw *mw = &perf->mw;
415 struct pci_dev *pdev = perf->ntb->pdev;
420 ntb_mw_clear_trans(perf->ntb, 0);
421 dma_free_coherent(&pdev->dev, mw->buf_size,
422 mw->virt_addr, mw->dma_addr);
425 mw->virt_addr = NULL;
428 static int perf_set_mw(struct perf_ctx *perf, resource_size_t size)
430 struct perf_mw *mw = &perf->mw;
431 size_t xlat_size, buf_size;
437 xlat_size = round_up(size, mw->xlat_align_size);
438 buf_size = round_up(size, mw->xlat_align);
440 if (mw->xlat_size == xlat_size)
446 mw->xlat_size = xlat_size;
447 mw->buf_size = buf_size;
449 mw->virt_addr = dma_alloc_coherent(&perf->ntb->pdev->dev, buf_size,
450 &mw->dma_addr, GFP_KERNEL);
451 if (!mw->virt_addr) {
456 rc = ntb_mw_set_trans(perf->ntb, 0, mw->dma_addr, mw->xlat_size);
458 dev_err(&perf->ntb->dev, "Unable to set mw0 translation\n");
466 static void perf_link_work(struct work_struct *work)
468 struct perf_ctx *perf =
469 container_of(work, struct perf_ctx, link_work.work);
470 struct ntb_dev *ndev = perf->ntb;
471 struct pci_dev *pdev = ndev->pdev;
476 dev_dbg(&perf->ntb->pdev->dev, "%s called\n", __func__);
478 size = perf->mw.phys_size;
480 if (max_mw_size && size > max_mw_size)
483 ntb_peer_spad_write(ndev, MW_SZ_HIGH, upper_32_bits(size));
484 ntb_peer_spad_write(ndev, MW_SZ_LOW, lower_32_bits(size));
485 ntb_peer_spad_write(ndev, VERSION, PERF_VERSION);
487 /* now read what peer wrote */
488 val = ntb_spad_read(ndev, VERSION);
489 if (val != PERF_VERSION) {
490 dev_dbg(&pdev->dev, "Remote version = %#x\n", val);
494 val = ntb_spad_read(ndev, MW_SZ_HIGH);
495 size = (u64)val << 32;
497 val = ntb_spad_read(ndev, MW_SZ_LOW);
500 dev_dbg(&pdev->dev, "Remote MW size = %#llx\n", size);
502 rc = perf_set_mw(perf, size);
506 perf->link_is_up = true;
514 if (ntb_link_is_up(ndev, NULL, NULL) == 1)
515 schedule_delayed_work(&perf->link_work,
516 msecs_to_jiffies(PERF_LINK_DOWN_TIMEOUT));
519 static void perf_link_cleanup(struct work_struct *work)
521 struct perf_ctx *perf = container_of(work,
525 dev_dbg(&perf->ntb->pdev->dev, "%s called\n", __func__);
527 if (!perf->link_is_up)
528 cancel_delayed_work_sync(&perf->link_work);
531 static int perf_setup_mw(struct ntb_dev *ntb, struct perf_ctx *perf)
538 rc = ntb_mw_get_range(ntb, 0, &mw->phys_addr, &mw->phys_size,
539 &mw->xlat_align, &mw->xlat_align_size);
543 perf->mw.vbase = ioremap_wc(mw->phys_addr, mw->phys_size);
550 static ssize_t debugfs_run_read(struct file *filp, char __user *ubuf,
551 size_t count, loff_t *offp)
553 struct perf_ctx *perf = filp->private_data;
555 ssize_t ret, out_offset;
560 buf = kmalloc(64, GFP_KERNEL);
563 out_offset = snprintf(buf, 64, "%d\n", perf->run);
564 ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset);
570 static void threads_cleanup(struct perf_ctx *perf)
572 struct pthr_ctx *pctx;
576 for (i = 0; i < MAX_THREADS; i++) {
577 pctx = &perf->pthr_ctx[i];
579 kthread_stop(pctx->thread);
585 static ssize_t debugfs_run_write(struct file *filp, const char __user *ubuf,
586 size_t count, loff_t *offp)
588 struct perf_ctx *perf = filp->private_data;
591 if (!perf->link_is_up)
594 if (perf->perf_threads == 0)
597 if (atomic_read(&perf->tsync) == 0)
601 threads_cleanup(perf);
605 if (perf->perf_threads > MAX_THREADS) {
606 perf->perf_threads = MAX_THREADS;
607 pr_info("Reset total threads to: %u\n", MAX_THREADS);
610 /* no greater than 1M */
611 if (seg_order > MAX_SEG_ORDER) {
612 seg_order = MAX_SEG_ORDER;
613 pr_info("Fix seg_order to %u\n", seg_order);
616 if (run_order < seg_order) {
617 run_order = seg_order;
618 pr_info("Fix run_order to %u\n", run_order);
621 node = dev_to_node(&perf->ntb->pdev->dev);
622 /* launch kernel thread */
623 for (i = 0; i < perf->perf_threads; i++) {
624 struct pthr_ctx *pctx;
626 pctx = &perf->pthr_ctx[i];
627 atomic_set(&pctx->dma_sync, 0);
630 kthread_create_on_node(ntb_perf_thread,
632 node, "ntb_perf %d", i);
633 if (IS_ERR(pctx->thread)) {
637 wake_up_process(pctx->thread);
639 if (perf->run == false)
648 threads_cleanup(perf);
652 static const struct file_operations ntb_perf_debugfs_run = {
653 .owner = THIS_MODULE,
655 .read = debugfs_run_read,
656 .write = debugfs_run_write,
659 static int perf_debugfs_setup(struct perf_ctx *perf)
661 struct pci_dev *pdev = perf->ntb->pdev;
663 if (!debugfs_initialized())
666 if (!perf_debugfs_dir) {
667 perf_debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
668 if (!perf_debugfs_dir)
672 perf->debugfs_node_dir = debugfs_create_dir(pci_name(pdev),
674 if (!perf->debugfs_node_dir)
677 perf->debugfs_run = debugfs_create_file("run", S_IRUSR | S_IWUSR,
678 perf->debugfs_node_dir, perf,
679 &ntb_perf_debugfs_run);
680 if (!perf->debugfs_run)
683 perf->debugfs_threads = debugfs_create_u8("threads", S_IRUSR | S_IWUSR,
684 perf->debugfs_node_dir,
685 &perf->perf_threads);
686 if (!perf->debugfs_threads)
692 static int perf_probe(struct ntb_client *client, struct ntb_dev *ntb)
694 struct pci_dev *pdev = ntb->pdev;
695 struct perf_ctx *perf;
699 node = dev_to_node(&pdev->dev);
701 perf = kzalloc_node(sizeof(*perf), GFP_KERNEL, node);
708 perf->perf_threads = 1;
709 atomic_set(&perf->tsync, 0);
711 spin_lock_init(&perf->db_lock);
712 perf_setup_mw(ntb, perf);
713 INIT_DELAYED_WORK(&perf->link_work, perf_link_work);
714 INIT_WORK(&perf->link_cleanup, perf_link_cleanup);
716 rc = ntb_set_ctx(ntb, perf, &perf_ops);
720 perf->link_is_up = false;
721 ntb_link_enable(ntb, NTB_SPEED_AUTO, NTB_WIDTH_AUTO);
724 rc = perf_debugfs_setup(perf);
731 cancel_delayed_work_sync(&perf->link_work);
732 cancel_work_sync(&perf->link_cleanup);
738 static void perf_remove(struct ntb_client *client, struct ntb_dev *ntb)
740 struct perf_ctx *perf = ntb->ctx;
743 dev_dbg(&perf->ntb->dev, "%s called\n", __func__);
745 cancel_delayed_work_sync(&perf->link_work);
746 cancel_work_sync(&perf->link_cleanup);
749 ntb_link_disable(ntb);
751 debugfs_remove_recursive(perf_debugfs_dir);
752 perf_debugfs_dir = NULL;
755 for (i = 0; i < MAX_THREADS; i++) {
756 struct pthr_ctx *pctx = &perf->pthr_ctx[i];
759 dma_release_channel(pctx->dma_chan);
766 static struct ntb_client perf_client = {
769 .remove = perf_remove,
772 module_ntb_client(perf_client);