drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kthread.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_NR_AEN_COMMANDS    1
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static LIST_HEAD(dev_list);
  68 static struct task_struct *nvme_thread;
  69 static struct workqueue_struct *nvme_workq;
  70 static wait_queue_head_t nvme_kthread_wait;
  71
  72 struct nvme_dev;
  73 struct nvme_queue;
  74
  75 static int nvme_reset(struct nvme_dev *dev);
  76 static void nvme_process_cq(struct nvme_queue *nvmeq);
  77 static void nvme_remove_dead_ctrl(struct nvme_dev *dev);
  78 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  79
  80 /*
  81  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  82  */
  83 struct nvme_dev {
  84         struct list_head node;
  85         struct nvme_queue **queues;
  86         struct blk_mq_tag_set tagset;
  87         struct blk_mq_tag_set admin_tagset;
  88         u32 __iomem *dbs;
  89         struct device *dev;
  90         struct dma_pool *prp_page_pool;
  91         struct dma_pool *prp_small_pool;
  92         unsigned queue_count;
  93         unsigned online_queues;
  94         unsigned max_qid;
  95         int q_depth;
  96         u32 db_stride;
  97         struct msix_entry *entry;
  98         void __iomem *bar;
  99         struct work_struct reset_work;
 100         struct work_struct scan_work;
 101         struct work_struct remove_work;
 102         struct mutex shutdown_lock;
 103         bool subsystem;
 104         void __iomem *cmb;
 105         dma_addr_t cmb_dma_addr;
 106         u64 cmb_size;
 107         u32 cmbsz;
 108         unsigned long flags;
 109
 110 #define NVME_CTRL_RESETTING    0
 111
 112         struct nvme_ctrl ctrl;
 113         struct completion ioq_wait;
 114 };
 115
 116 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 117 {
 118         return container_of(ctrl, struct nvme_dev, ctrl);
 119 }
 120
 121 /*
 122  * An NVM Express queue.  Each device has at least two (one for admin
 123  * commands and one for I/O commands).
 124  */
 125 struct nvme_queue {
 126         struct device *q_dmadev;
 127         struct nvme_dev *dev;
 128         char irqname[24];       /* nvme4294967295-65535\0 */
 129         spinlock_t q_lock;
 130         struct nvme_command *sq_cmds;
 131         struct nvme_command __iomem *sq_cmds_io;
 132         volatile struct nvme_completion *cqes;
 133         struct blk_mq_tags **tags;
 134         dma_addr_t sq_dma_addr;
 135         dma_addr_t cq_dma_addr;
 136         u32 __iomem *q_db;
 137         u16 q_depth;
 138         s16 cq_vector;
 139         u16 sq_head;
 140         u16 sq_tail;
 141         u16 cq_head;
 142         u16 qid;
 143         u8 cq_phase;
 144         u8 cqe_seen;
 145 };
 146
 147 /*
 148  * The nvme_iod describes the data in an I/O, including the list of PRP
 149  * entries.  You can't see it in this data structure because C doesn't let
 150  * me express that.  Use nvme_init_iod to ensure there's enough space
 151  * allocated to store the PRP list.
 152  */
 153 struct nvme_iod {
 154         struct nvme_queue *nvmeq;
 155         int aborted;
 156         int npages;             /* In the PRP list. 0 means small pool in use */
 157         int nents;              /* Used in scatterlist */
 158         int length;             /* Of data, in bytes */
 159         dma_addr_t first_dma;
 160         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 161         struct scatterlist *sg;
 162         struct scatterlist inline_sg[0];
 163 };
 164
 165 /*
 166  * Check we didin't inadvertently grow the command struct
 167  */
 168 static inline void _nvme_check_size(void)
 169 {
 170         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 171         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 174         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 175         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 176         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 177         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 178         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 179         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 180         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 181         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 182 }
 183
 184 /*
 185  * Max size of iod being embedded in the request payload
 186  */
 187 #define NVME_INT_PAGES          2
 188 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 189
 190 /*
 191  * Will slightly overestimate the number of pages needed.  This is OK
 192  * as it only leads to a small amount of wasted memory for the lifetime of
 193  * the I/O.
 194  */
 195 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 196 {
 197         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 198                                       dev->ctrl.page_size);
 199         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 200 }
 201
 202 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 203                 unsigned int size, unsigned int nseg)
 204 {
 205         return sizeof(__le64 *) * nvme_npages(size, dev) +
 206                         sizeof(struct scatterlist) * nseg;
 207 }
 208
 209 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 210 {
 211         return sizeof(struct nvme_iod) +
 212                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 213 }
 214
 215 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 216                                 unsigned int hctx_idx)
 217 {
 218         struct nvme_dev *dev = data;
 219         struct nvme_queue *nvmeq = dev->queues[0];
 220
 221         WARN_ON(hctx_idx != 0);
 222         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 223         WARN_ON(nvmeq->tags);
 224
 225         hctx->driver_data = nvmeq;
 226         nvmeq->tags = &dev->admin_tagset.tags[0];
 227         return 0;
 228 }
 229
 230 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 231 {
 232         struct nvme_queue *nvmeq = hctx->driver_data;
 233
 234         nvmeq->tags = NULL;
 235 }
 236
 237 static int nvme_admin_init_request(void *data, struct request *req,
 238                                 unsigned int hctx_idx, unsigned int rq_idx,
 239                                 unsigned int numa_node)
 240 {
 241         struct nvme_dev *dev = data;
 242         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 243         struct nvme_queue *nvmeq = dev->queues[0];
 244
 245         BUG_ON(!nvmeq);
 246         iod->nvmeq = nvmeq;
 247         return 0;
 248 }
 249
 250 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 251                           unsigned int hctx_idx)
 252 {
 253         struct nvme_dev *dev = data;
 254         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 255
 256         if (!nvmeq->tags)
 257                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 258
 259         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 260         hctx->driver_data = nvmeq;
 261         return 0;
 262 }
 263
 264 static int nvme_init_request(void *data, struct request *req,
 265                                 unsigned int hctx_idx, unsigned int rq_idx,
 266                                 unsigned int numa_node)
 267 {
 268         struct nvme_dev *dev = data;
 269         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 270         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 271
 272         BUG_ON(!nvmeq);
 273         iod->nvmeq = nvmeq;
 274         return 0;
 275 }
 276
 277 static void nvme_complete_async_event(struct nvme_dev *dev,
 278                 struct nvme_completion *cqe)
 279 {
 280         u16 status = le16_to_cpu(cqe->status) >> 1;
 281         u32 result = le32_to_cpu(cqe->result);
 282
 283         if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
 284                 ++dev->ctrl.event_limit;
 285         if (status != NVME_SC_SUCCESS)
 286                 return;
 287
 288         switch (result & 0xff07) {
 289         case NVME_AER_NOTICE_NS_CHANGED:
 290                 dev_info(dev->ctrl.device, "rescanning\n");
 291                 queue_work(nvme_workq, &dev->scan_work);
 292         default:
 293                 dev_warn(dev->ctrl.device, "async event result %08x\n", result);
 294         }
 295 }
 296
 297 /**
 298  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 299  * @nvmeq: The queue to use
 300  * @cmd: The command to send
 301  *
 302  * Safe to use from interrupt context
 303  */
 304 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 305                                                 struct nvme_command *cmd)
 306 {
 307         u16 tail = nvmeq->sq_tail;
 308
 309         if (nvmeq->sq_cmds_io)
 310                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 311         else
 312                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 313
 314         if (++tail == nvmeq->q_depth)
 315                 tail = 0;
 316         writel(tail, nvmeq->q_db);
 317         nvmeq->sq_tail = tail;
 318 }
 319
 320 static __le64 **iod_list(struct request *req)
 321 {
 322         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 323         return (__le64 **)(iod->sg + req->nr_phys_segments);
 324 }
 325
 326 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 327 {
 328         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 329         int nseg = rq->nr_phys_segments;
 330         unsigned size;
 331
 332         if (rq->cmd_flags & REQ_DISCARD)
 333                 size = sizeof(struct nvme_dsm_range);
 334         else
 335                 size = blk_rq_bytes(rq);
 336
 337         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 338                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 339                 if (!iod->sg)
 340                         return BLK_MQ_RQ_QUEUE_BUSY;
 341         } else {
 342                 iod->sg = iod->inline_sg;
 343         }
 344
 345         iod->aborted = 0;
 346         iod->npages = -1;
 347         iod->nents = 0;
 348         iod->length = size;
 349         return 0;
 350 }
 351
 352 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 353 {
 354         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 355         const int last_prp = dev->ctrl.page_size / 8 - 1;
 356         int i;
 357         __le64 **list = iod_list(req);
 358         dma_addr_t prp_dma = iod->first_dma;
 359
 360         if (iod->npages == 0)
 361                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 362         for (i = 0; i < iod->npages; i++) {
 363                 __le64 *prp_list = list[i];
 364                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 365                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 366                 prp_dma = next_prp_dma;
 367         }
 368
 369         if (iod->sg != iod->inline_sg)
 370                 kfree(iod->sg);
 371 }
 372
 373 #ifdef CONFIG_BLK_DEV_INTEGRITY
 374 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 375 {
 376         if (be32_to_cpu(pi->ref_tag) == v)
 377                 pi->ref_tag = cpu_to_be32(p);
 378 }
 379
 380 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 381 {
 382         if (be32_to_cpu(pi->ref_tag) == p)
 383                 pi->ref_tag = cpu_to_be32(v);
 384 }
 385
 386 /**
 387  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 388  *
 389  * The virtual start sector is the one that was originally submitted by the
 390  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 391  * start sector may be different. Remap protection information to match the
 392  * physical LBA on writes, and back to the original seed on reads.
 393  *
 394  * Type 0 and 3 do not have a ref tag, so no remapping required.
 395  */
 396 static void nvme_dif_remap(struct request *req,
 397                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 398 {
 399         struct nvme_ns *ns = req->rq_disk->private_data;
 400         struct bio_integrity_payload *bip;
 401         struct t10_pi_tuple *pi;
 402         void *p, *pmap;
 403         u32 i, nlb, ts, phys, virt;
 404
 405         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 406                 return;
 407
 408         bip = bio_integrity(req->bio);
 409         if (!bip)
 410                 return;
 411
 412         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 413
 414         p = pmap;
 415         virt = bip_get_seed(bip);
 416         phys = nvme_block_nr(ns, blk_rq_pos(req));
 417         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 418         ts = ns->disk->queue->integrity.tuple_size;
 419
 420         for (i = 0; i < nlb; i++, virt++, phys++) {
 421                 pi = (struct t10_pi_tuple *)p;
 422                 dif_swap(phys, virt, pi);
 423                 p += ts;
 424         }
 425         kunmap_atomic(pmap);
 426 }
 427 #else /* CONFIG_BLK_DEV_INTEGRITY */
 428 static void nvme_dif_remap(struct request *req,
 429                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 430 {
 431 }
 432 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 433 {
 434 }
 435 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 436 {
 437 }
 438 #endif
 439
 440 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 441                 int total_len)
 442 {
 443         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 444         struct dma_pool *pool;
 445         int length = total_len;
 446         struct scatterlist *sg = iod->sg;
 447         int dma_len = sg_dma_len(sg);
 448         u64 dma_addr = sg_dma_address(sg);
 449         u32 page_size = dev->ctrl.page_size;
 450         int offset = dma_addr & (page_size - 1);
 451         __le64 *prp_list;
 452         __le64 **list = iod_list(req);
 453         dma_addr_t prp_dma;
 454         int nprps, i;
 455
 456         length -= (page_size - offset);
 457         if (length <= 0)
 458                 return true;
 459
 460         dma_len -= (page_size - offset);
 461         if (dma_len) {
 462                 dma_addr += (page_size - offset);
 463         } else {
 464                 sg = sg_next(sg);
 465                 dma_addr = sg_dma_address(sg);
 466                 dma_len = sg_dma_len(sg);
 467         }
 468
 469         if (length <= page_size) {
 470                 iod->first_dma = dma_addr;
 471                 return true;
 472         }
 473
 474         nprps = DIV_ROUND_UP(length, page_size);
 475         if (nprps <= (256 / 8)) {
 476                 pool = dev->prp_small_pool;
 477                 iod->npages = 0;
 478         } else {
 479                 pool = dev->prp_page_pool;
 480                 iod->npages = 1;
 481         }
 482
 483         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 484         if (!prp_list) {
 485                 iod->first_dma = dma_addr;
 486                 iod->npages = -1;
 487                 return false;
 488         }
 489         list[0] = prp_list;
 490         iod->first_dma = prp_dma;
 491         i = 0;
 492         for (;;) {
 493                 if (i == page_size >> 3) {
 494                         __le64 *old_prp_list = prp_list;
 495                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 496                         if (!prp_list)
 497                                 return false;
 498                         list[iod->npages++] = prp_list;
 499                         prp_list[0] = old_prp_list[i - 1];
 500                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 501                         i = 1;
 502                 }
 503                 prp_list[i++] = cpu_to_le64(dma_addr);
 504                 dma_len -= page_size;
 505                 dma_addr += page_size;
 506                 length -= page_size;
 507                 if (length <= 0)
 508                         break;
 509                 if (dma_len > 0)
 510                         continue;
 511                 BUG_ON(dma_len < 0);
 512                 sg = sg_next(sg);
 513                 dma_addr = sg_dma_address(sg);
 514                 dma_len = sg_dma_len(sg);
 515         }
 516
 517         return true;
 518 }
 519
 520 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 521                 struct nvme_command *cmnd)
 522 {
 523         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 524         struct request_queue *q = req->q;
 525         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 526                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 527         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 528
 529         sg_init_table(iod->sg, req->nr_phys_segments);
 530         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 531         if (!iod->nents)
 532                 goto out;
 533
 534         ret = BLK_MQ_RQ_QUEUE_BUSY;
 535         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 536                 goto out;
 537
 538         if (!nvme_setup_prps(dev, req, blk_rq_bytes(req)))
 539                 goto out_unmap;
 540
 541         ret = BLK_MQ_RQ_QUEUE_ERROR;
 542         if (blk_integrity_rq(req)) {
 543                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 544                         goto out_unmap;
 545
 546                 sg_init_table(&iod->meta_sg, 1);
 547                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 548                         goto out_unmap;
 549
 550                 if (rq_data_dir(req))
 551                         nvme_dif_remap(req, nvme_dif_prep);
 552
 553                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 554                         goto out_unmap;
 555         }
 556
 557         cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 558         cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
 559         if (blk_integrity_rq(req))
 560                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 561         return BLK_MQ_RQ_QUEUE_OK;
 562
 563 out_unmap:
 564         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 565 out:
 566         return ret;
 567 }
 568
 569 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 570 {
 571         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 572         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 573                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 574
 575         if (iod->nents) {
 576                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 577                 if (blk_integrity_rq(req)) {
 578                         if (!rq_data_dir(req))
 579                                 nvme_dif_remap(req, nvme_dif_complete);
 580                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 581                 }
 582         }
 583
 584         nvme_free_iod(dev, req);
 585 }
 586
 587 /*
 588  * We reuse the small pool to allocate the 16-byte range here as it is not
 589  * worth having a special pool for these or additional cases to handle freeing
 590  * the iod.
 591  */
 592 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 593                 struct request *req, struct nvme_command *cmnd)
 594 {
 595         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 596         struct nvme_dsm_range *range;
 597
 598         range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
 599                                                 &iod->first_dma);
 600         if (!range)
 601                 return BLK_MQ_RQ_QUEUE_BUSY;
 602         iod_list(req)[0] = (__le64 *)range;
 603         iod->npages = 0;
 604
 605         range->cattr = cpu_to_le32(0);
 606         range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
 607         range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
 608
 609         memset(cmnd, 0, sizeof(*cmnd));
 610         cmnd->dsm.opcode = nvme_cmd_dsm;
 611         cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
 612         cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
 613         cmnd->dsm.nr = 0;
 614         cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
 615         return BLK_MQ_RQ_QUEUE_OK;
 616 }
 617
 618 /*
 619  * NOTE: ns is NULL when called on the admin queue.
 620  */
 621 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 622                          const struct blk_mq_queue_data *bd)
 623 {
 624         struct nvme_ns *ns = hctx->queue->queuedata;
 625         struct nvme_queue *nvmeq = hctx->driver_data;
 626         struct nvme_dev *dev = nvmeq->dev;
 627         struct request *req = bd->rq;
 628         struct nvme_command cmnd;
 629         int ret = BLK_MQ_RQ_QUEUE_OK;
 630
 631         /*
 632          * If formated with metadata, require the block layer provide a buffer
 633          * unless this namespace is formated such that the metadata can be
 634          * stripped/generated by the controller with PRACT=1.
 635          */
 636         if (ns && ns->ms && !blk_integrity_rq(req)) {
 637                 if (!(ns->pi_type && ns->ms == 8) &&
 638                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 639                         blk_mq_end_request(req, -EFAULT);
 640                         return BLK_MQ_RQ_QUEUE_OK;
 641                 }
 642         }
 643
 644         ret = nvme_init_iod(req, dev);
 645         if (ret)
 646                 return ret;
 647
 648         if (req->cmd_flags & REQ_DISCARD) {
 649                 ret = nvme_setup_discard(nvmeq, ns, req, &cmnd);
 650         } else {
 651                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 652                         memcpy(&cmnd, req->cmd, sizeof(cmnd));
 653                 else if (req->cmd_flags & REQ_FLUSH)
 654                         nvme_setup_flush(ns, &cmnd);
 655                 else
 656                         nvme_setup_rw(ns, req, &cmnd);
 657
 658                 if (req->nr_phys_segments)
 659                         ret = nvme_map_data(dev, req, &cmnd);
 660         }
 661
 662         if (ret)
 663                 goto out;
 664
 665         cmnd.common.command_id = req->tag;
 666         blk_mq_start_request(req);
 667
 668         spin_lock_irq(&nvmeq->q_lock);
 669         __nvme_submit_cmd(nvmeq, &cmnd);
 670         nvme_process_cq(nvmeq);
 671         spin_unlock_irq(&nvmeq->q_lock);
 672         return BLK_MQ_RQ_QUEUE_OK;
 673 out:
 674         nvme_free_iod(dev, req);
 675         return ret;
 676 }
 677
 678 static void nvme_complete_rq(struct request *req)
 679 {
 680         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 681         struct nvme_dev *dev = iod->nvmeq->dev;
 682         int error = 0;
 683
 684         nvme_unmap_data(dev, req);
 685
 686         if (unlikely(req->errors)) {
 687                 if (nvme_req_needs_retry(req, req->errors)) {
 688                         nvme_requeue_req(req);
 689                         return;
 690                 }
 691
 692                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 693                         error = req->errors;
 694                 else
 695                         error = nvme_error_status(req->errors);
 696         }
 697
 698         if (unlikely(iod->aborted)) {
 699                 dev_warn(dev->ctrl.device,
 700                         "completing aborted command with status: %04x\n",
 701                         req->errors);
 702         }
 703
 704         blk_mq_end_request(req, error);
 705 }
 706
 707 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 708 {
 709         u16 head, phase;
 710
 711         head = nvmeq->cq_head;
 712         phase = nvmeq->cq_phase;
 713
 714         for (;;) {
 715                 struct nvme_completion cqe = nvmeq->cqes[head];
 716                 u16 status = le16_to_cpu(cqe.status);
 717                 struct request *req;
 718
 719                 if ((status & 1) != phase)
 720                         break;
 721                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 722                 if (++head == nvmeq->q_depth) {
 723                         head = 0;
 724                         phase = !phase;
 725                 }
 726
 727                 if (tag && *tag == cqe.command_id)
 728                         *tag = -1;
 729
 730                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 731                         dev_warn(nvmeq->dev->ctrl.device,
 732                                 "invalid id %d completed on queue %d\n",
 733                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 734                         continue;
 735                 }
 736
 737                 /*
 738                  * AEN requests are special as they don't time out and can
 739                  * survive any kind of queue freeze and often don't respond to
 740                  * aborts.  We don't even bother to allocate a struct request
 741                  * for them but rather special case them here.
 742                  */
 743                 if (unlikely(nvmeq->qid == 0 &&
 744                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 745                         nvme_complete_async_event(nvmeq->dev, &cqe);
 746                         continue;
 747                 }
 748
 749                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 750                 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
 751                         u32 result = le32_to_cpu(cqe.result);
 752                         req->special = (void *)(uintptr_t)result;
 753                 }
 754                 blk_mq_complete_request(req, status >> 1);
 755
 756         }
 757
 758         /* If the controller ignores the cq head doorbell and continuously
 759          * writes to the queue, it is theoretically possible to wrap around
 760          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 761          * requires that 0.1% of your interrupts are handled, so this isn't
 762          * a big problem.
 763          */
 764         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 765                 return;
 766
 767         if (likely(nvmeq->cq_vector >= 0))
 768                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 769         nvmeq->cq_head = head;
 770         nvmeq->cq_phase = phase;
 771
 772         nvmeq->cqe_seen = 1;
 773 }
 774
 775 static void nvme_process_cq(struct nvme_queue *nvmeq)
 776 {
 777         __nvme_process_cq(nvmeq, NULL);
 778 }
 779
 780 static irqreturn_t nvme_irq(int irq, void *data)
 781 {
 782         irqreturn_t result;
 783         struct nvme_queue *nvmeq = data;
 784         spin_lock(&nvmeq->q_lock);
 785         nvme_process_cq(nvmeq);
 786         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 787         nvmeq->cqe_seen = 0;
 788         spin_unlock(&nvmeq->q_lock);
 789         return result;
 790 }
 791
 792 static irqreturn_t nvme_irq_check(int irq, void *data)
 793 {
 794         struct nvme_queue *nvmeq = data;
 795         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 796         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 797                 return IRQ_NONE;
 798         return IRQ_WAKE_THREAD;
 799 }
 800
 801 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 802 {
 803         struct nvme_queue *nvmeq = hctx->driver_data;
 804
 805         if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
 806             nvmeq->cq_phase) {
 807                 spin_lock_irq(&nvmeq->q_lock);
 808                 __nvme_process_cq(nvmeq, &tag);
 809                 spin_unlock_irq(&nvmeq->q_lock);
 810
 811                 if (tag == -1)
 812                         return 1;
 813         }
 814
 815         return 0;
 816 }
 817
 818 static void nvme_submit_async_event(struct nvme_dev *dev)
 819 {
 820         struct nvme_command c;
 821
 822         memset(&c, 0, sizeof(c));
 823         c.common.opcode = nvme_admin_async_event;
 824         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + --dev->ctrl.event_limit;
 825
 826         __nvme_submit_cmd(dev->queues[0], &c);
 827 }
 828
 829 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 830 {
 831         struct nvme_command c;
 832
 833         memset(&c, 0, sizeof(c));
 834         c.delete_queue.opcode = opcode;
 835         c.delete_queue.qid = cpu_to_le16(id);
 836
 837         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 838 }
 839
 840 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 841                                                 struct nvme_queue *nvmeq)
 842 {
 843         struct nvme_command c;
 844         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 845
 846         /*
 847          * Note: we (ab)use the fact the the prp fields survive if no data
 848          * is attached to the request.
 849          */
 850         memset(&c, 0, sizeof(c));
 851         c.create_cq.opcode = nvme_admin_create_cq;
 852         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 853         c.create_cq.cqid = cpu_to_le16(qid);
 854         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 855         c.create_cq.cq_flags = cpu_to_le16(flags);
 856         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 857
 858         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 859 }
 860
 861 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 862                                                 struct nvme_queue *nvmeq)
 863 {
 864         struct nvme_command c;
 865         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 866
 867         /*
 868          * Note: we (ab)use the fact the the prp fields survive if no data
 869          * is attached to the request.
 870          */
 871         memset(&c, 0, sizeof(c));
 872         c.create_sq.opcode = nvme_admin_create_sq;
 873         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 874         c.create_sq.sqid = cpu_to_le16(qid);
 875         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 876         c.create_sq.sq_flags = cpu_to_le16(flags);
 877         c.create_sq.cqid = cpu_to_le16(qid);
 878
 879         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 880 }
 881
 882 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 883 {
 884         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 885 }
 886
 887 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 888 {
 889         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 890 }
 891
 892 static void abort_endio(struct request *req, int error)
 893 {
 894         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 895         struct nvme_queue *nvmeq = iod->nvmeq;
 896         u32 result = (u32)(uintptr_t)req->special;
 897         u16 status = req->errors;
 898
 899         dev_warn(nvmeq->dev->ctrl.device,
 900                 "Abort status:%x result:%x", status, result);
 901         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 902
 903         blk_mq_free_request(req);
 904 }
 905
 906 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 907 {
 908         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 909         struct nvme_queue *nvmeq = iod->nvmeq;
 910         struct nvme_dev *dev = nvmeq->dev;
 911         struct request *abort_req;
 912         struct nvme_command cmd;
 913
 914         /*
 915          * Shutdown immediately if controller times out while starting. The
 916          * reset work will see the pci device disabled when it gets the forced
 917          * cancellation error. All outstanding requests are completed on
 918          * shutdown, so we return BLK_EH_HANDLED.
 919          */
 920         if (test_bit(NVME_CTRL_RESETTING, &dev->flags)) {
 921                 dev_warn(dev->ctrl.device,
 922                          "I/O %d QID %d timeout, disable controller\n",
 923                          req->tag, nvmeq->qid);
 924                 nvme_dev_disable(dev, false);
 925                 req->errors = NVME_SC_CANCELLED;
 926                 return BLK_EH_HANDLED;
 927         }
 928
 929         /*
 930          * Shutdown the controller immediately and schedule a reset if the
 931          * command was already aborted once before and still hasn't been
 932          * returned to the driver, or if this is the admin queue.
 933          */
 934         if (!nvmeq->qid || iod->aborted) {
 935                 dev_warn(dev->ctrl.device,
 936                          "I/O %d QID %d timeout, reset controller\n",
 937                          req->tag, nvmeq->qid);
 938                 nvme_dev_disable(dev, false);
 939                 queue_work(nvme_workq, &dev->reset_work);
 940
 941                 /*
 942                  * Mark the request as handled, since the inline shutdown
 943                  * forces all outstanding requests to complete.
 944                  */
 945                 req->errors = NVME_SC_CANCELLED;
 946                 return BLK_EH_HANDLED;
 947         }
 948
 949         iod->aborted = 1;
 950
 951         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 952                 atomic_inc(&dev->ctrl.abort_limit);
 953                 return BLK_EH_RESET_TIMER;
 954         }
 955
 956         memset(&cmd, 0, sizeof(cmd));
 957         cmd.abort.opcode = nvme_admin_abort_cmd;
 958         cmd.abort.cid = req->tag;
 959         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 960
 961         dev_warn(nvmeq->dev->ctrl.device,
 962                 "I/O %d QID %d timeout, aborting\n",
 963                  req->tag, nvmeq->qid);
 964
 965         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 966                         BLK_MQ_REQ_NOWAIT);
 967         if (IS_ERR(abort_req)) {
 968                 atomic_inc(&dev->ctrl.abort_limit);
 969                 return BLK_EH_RESET_TIMER;
 970         }
 971
 972         abort_req->timeout = ADMIN_TIMEOUT;
 973         abort_req->end_io_data = NULL;
 974         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 975
 976         /*
 977          * The aborted req will be completed on receiving the abort req.
 978          * We enable the timer again. If hit twice, it'll cause a device reset,
 979          * as the device then is in a faulty state.
 980          */
 981         return BLK_EH_RESET_TIMER;
 982 }
 983
 984 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
 985 {
 986         struct nvme_queue *nvmeq = data;
 987         int status;
 988
 989         if (!blk_mq_request_started(req))
 990                 return;
 991
 992         dev_warn(nvmeq->dev->ctrl.device,
 993                  "Cancelling I/O %d QID %d\n", req->tag, nvmeq->qid);
 994
 995         status = NVME_SC_ABORT_REQ;
 996         if (blk_queue_dying(req->q))
 997                 status |= NVME_SC_DNR;
 998         blk_mq_complete_request(req, status);
 999 }
1000
1001 static void nvme_free_queue(struct nvme_queue *nvmeq)
1002 {
1003         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1004                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1005         if (nvmeq->sq_cmds)
1006                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1007                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1008         kfree(nvmeq);
1009 }
1010
1011 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1012 {
1013         int i;
1014
1015         for (i = dev->queue_count - 1; i >= lowest; i--) {
1016                 struct nvme_queue *nvmeq = dev->queues[i];
1017                 dev->queue_count--;
1018                 dev->queues[i] = NULL;
1019                 nvme_free_queue(nvmeq);
1020         }
1021 }
1022
1023 /**
1024  * nvme_suspend_queue - put queue into suspended state
1025  * @nvmeq - queue to suspend
1026  */
1027 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1028 {
1029         int vector;
1030
1031         spin_lock_irq(&nvmeq->q_lock);
1032         if (nvmeq->cq_vector == -1) {
1033                 spin_unlock_irq(&nvmeq->q_lock);
1034                 return 1;
1035         }
1036         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1037         nvmeq->dev->online_queues--;
1038         nvmeq->cq_vector = -1;
1039         spin_unlock_irq(&nvmeq->q_lock);
1040
1041         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1042                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1043
1044         irq_set_affinity_hint(vector, NULL);
1045         free_irq(vector, nvmeq);
1046
1047         return 0;
1048 }
1049
1050 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1051 {
1052         spin_lock_irq(&nvmeq->q_lock);
1053         if (nvmeq->tags && *nvmeq->tags)
1054                 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1055         spin_unlock_irq(&nvmeq->q_lock);
1056 }
1057
1058 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1059 {
1060         struct nvme_queue *nvmeq = dev->queues[0];
1061
1062         if (!nvmeq)
1063                 return;
1064         if (nvme_suspend_queue(nvmeq))
1065                 return;
1066
1067         if (shutdown)
1068                 nvme_shutdown_ctrl(&dev->ctrl);
1069         else
1070                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1071                                                 dev->bar + NVME_REG_CAP));
1072
1073         spin_lock_irq(&nvmeq->q_lock);
1074         nvme_process_cq(nvmeq);
1075         spin_unlock_irq(&nvmeq->q_lock);
1076 }
1077
1078 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1079                                 int entry_size)
1080 {
1081         int q_depth = dev->q_depth;
1082         unsigned q_size_aligned = roundup(q_depth * entry_size,
1083                                           dev->ctrl.page_size);
1084
1085         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1086                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1087                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1088                 q_depth = div_u64(mem_per_q, entry_size);
1089
1090                 /*
1091                  * Ensure the reduced q_depth is above some threshold where it
1092                  * would be better to map queues in system memory with the
1093                  * original depth
1094                  */
1095                 if (q_depth < 64)
1096                         return -ENOMEM;
1097         }
1098
1099         return q_depth;
1100 }
1101
1102 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1103                                 int qid, int depth)
1104 {
1105         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1106                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1107                                                       dev->ctrl.page_size);
1108                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1109                 nvmeq->sq_cmds_io = dev->cmb + offset;
1110         } else {
1111                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1112                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1113                 if (!nvmeq->sq_cmds)
1114                         return -ENOMEM;
1115         }
1116
1117         return 0;
1118 }
1119
1120 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1121                                                         int depth)
1122 {
1123         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1124         if (!nvmeq)
1125                 return NULL;
1126
1127         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1128                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1129         if (!nvmeq->cqes)
1130                 goto free_nvmeq;
1131
1132         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1133                 goto free_cqdma;
1134
1135         nvmeq->q_dmadev = dev->dev;
1136         nvmeq->dev = dev;
1137         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1138                         dev->ctrl.instance, qid);
1139         spin_lock_init(&nvmeq->q_lock);
1140         nvmeq->cq_head = 0;
1141         nvmeq->cq_phase = 1;
1142         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1143         nvmeq->q_depth = depth;
1144         nvmeq->qid = qid;
1145         nvmeq->cq_vector = -1;
1146         dev->queues[qid] = nvmeq;
1147
1148         /* make sure queue descriptor is set before queue count, for kthread */
1149         mb();
1150         dev->queue_count++;
1151
1152         return nvmeq;
1153
1154  free_cqdma:
1155         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1156                                                         nvmeq->cq_dma_addr);
1157  free_nvmeq:
1158         kfree(nvmeq);
1159         return NULL;
1160 }
1161
1162 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1163                                                         const char *name)
1164 {
1165         if (use_threaded_interrupts)
1166                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1167                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1168                                         name, nvmeq);
1169         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1170                                 IRQF_SHARED, name, nvmeq);
1171 }
1172
1173 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1174 {
1175         struct nvme_dev *dev = nvmeq->dev;
1176
1177         spin_lock_irq(&nvmeq->q_lock);
1178         nvmeq->sq_tail = 0;
1179         nvmeq->cq_head = 0;
1180         nvmeq->cq_phase = 1;
1181         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1182         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1183         dev->online_queues++;
1184         spin_unlock_irq(&nvmeq->q_lock);
1185 }
1186
1187 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1188 {
1189         struct nvme_dev *dev = nvmeq->dev;
1190         int result;
1191
1192         nvmeq->cq_vector = qid - 1;
1193         result = adapter_alloc_cq(dev, qid, nvmeq);
1194         if (result < 0)
1195                 return result;
1196
1197         result = adapter_alloc_sq(dev, qid, nvmeq);
1198         if (result < 0)
1199                 goto release_cq;
1200
1201         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1202         if (result < 0)
1203                 goto release_sq;
1204
1205         nvme_init_queue(nvmeq, qid);
1206         return result;
1207
1208  release_sq:
1209         adapter_delete_sq(dev, qid);
1210  release_cq:
1211         adapter_delete_cq(dev, qid);
1212         return result;
1213 }
1214
1215 static struct blk_mq_ops nvme_mq_admin_ops = {
1216         .queue_rq       = nvme_queue_rq,
1217         .complete       = nvme_complete_rq,
1218         .map_queue      = blk_mq_map_queue,
1219         .init_hctx      = nvme_admin_init_hctx,
1220         .exit_hctx      = nvme_admin_exit_hctx,
1221         .init_request   = nvme_admin_init_request,
1222         .timeout        = nvme_timeout,
1223 };
1224
1225 static struct blk_mq_ops nvme_mq_ops = {
1226         .queue_rq       = nvme_queue_rq,
1227         .complete       = nvme_complete_rq,
1228         .map_queue      = blk_mq_map_queue,
1229         .init_hctx      = nvme_init_hctx,
1230         .init_request   = nvme_init_request,
1231         .timeout        = nvme_timeout,
1232         .poll           = nvme_poll,
1233 };
1234
1235 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1236 {
1237         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1238                 blk_cleanup_queue(dev->ctrl.admin_q);
1239                 blk_mq_free_tag_set(&dev->admin_tagset);
1240         }
1241 }
1242
1243 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1244 {
1245         if (!dev->ctrl.admin_q) {
1246                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1247                 dev->admin_tagset.nr_hw_queues = 1;
1248
1249                 /*
1250                  * Subtract one to leave an empty queue entry for 'Full Queue'
1251                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1252                  */
1253                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1254                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1255                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1256                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1257                 dev->admin_tagset.driver_data = dev;
1258
1259                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1260                         return -ENOMEM;
1261
1262                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1263                 if (IS_ERR(dev->ctrl.admin_q)) {
1264                         blk_mq_free_tag_set(&dev->admin_tagset);
1265                         return -ENOMEM;
1266                 }
1267                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1268                         nvme_dev_remove_admin(dev);
1269                         dev->ctrl.admin_q = NULL;
1270                         return -ENODEV;
1271                 }
1272         } else
1273                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1274
1275         return 0;
1276 }
1277
1278 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1279 {
1280         int result;
1281         u32 aqa;
1282         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1283         struct nvme_queue *nvmeq;
1284
1285         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1286                                                 NVME_CAP_NSSRC(cap) : 0;
1287
1288         if (dev->subsystem &&
1289             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1290                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1291
1292         result = nvme_disable_ctrl(&dev->ctrl, cap);
1293         if (result < 0)
1294                 return result;
1295
1296         nvmeq = dev->queues[0];
1297         if (!nvmeq) {
1298                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1299                 if (!nvmeq)
1300                         return -ENOMEM;
1301         }
1302
1303         aqa = nvmeq->q_depth - 1;
1304         aqa |= aqa << 16;
1305
1306         writel(aqa, dev->bar + NVME_REG_AQA);
1307         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1308         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1309
1310         result = nvme_enable_ctrl(&dev->ctrl, cap);
1311         if (result)
1312                 goto free_nvmeq;
1313
1314         nvmeq->cq_vector = 0;
1315         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1316         if (result) {
1317                 nvmeq->cq_vector = -1;
1318                 goto free_nvmeq;
1319         }
1320
1321         return result;
1322
1323  free_nvmeq:
1324         nvme_free_queues(dev, 0);
1325         return result;
1326 }
1327
1328 static int nvme_kthread(void *data)
1329 {
1330         struct nvme_dev *dev, *next;
1331
1332         while (!kthread_should_stop()) {
1333                 set_current_state(TASK_INTERRUPTIBLE);
1334                 spin_lock(&dev_list_lock);
1335                 list_for_each_entry_safe(dev, next, &dev_list, node) {
1336                         int i;
1337                         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1338
1339                         /*
1340                          * Skip controllers currently under reset.
1341                          */
1342                         if (work_pending(&dev->reset_work) || work_busy(&dev->reset_work))
1343                                 continue;
1344
1345                         if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
1346                                                         csts & NVME_CSTS_CFS) {
1347                                 if (queue_work(nvme_workq, &dev->reset_work)) {
1348                                         dev_warn(dev->ctrl.device,
1349                                                 "Failed status: %x, reset controller\n",
1350                                                 readl(dev->bar + NVME_REG_CSTS));
1351                                 }
1352                                 continue;
1353                         }
1354                         for (i = 0; i < dev->queue_count; i++) {
1355                                 struct nvme_queue *nvmeq = dev->queues[i];
1356                                 if (!nvmeq)
1357                                         continue;
1358                                 spin_lock_irq(&nvmeq->q_lock);
1359                                 nvme_process_cq(nvmeq);
1360
1361                                 while (i == 0 && dev->ctrl.event_limit > 0)
1362                                         nvme_submit_async_event(dev);
1363                                 spin_unlock_irq(&nvmeq->q_lock);
1364                         }
1365                 }
1366                 spin_unlock(&dev_list_lock);
1367                 schedule_timeout(round_jiffies_relative(HZ));
1368         }
1369         return 0;
1370 }
1371
1372 static int nvme_create_io_queues(struct nvme_dev *dev)
1373 {
1374         unsigned i, max;
1375         int ret = 0;
1376
1377         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1378                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1379                         ret = -ENOMEM;
1380                         break;
1381                 }
1382         }
1383
1384         max = min(dev->max_qid, dev->queue_count - 1);
1385         for (i = dev->online_queues; i <= max; i++) {
1386                 ret = nvme_create_queue(dev->queues[i], i);
1387                 if (ret) {
1388                         nvme_free_queues(dev, i);
1389                         break;
1390                 }
1391         }
1392
1393         /*
1394          * Ignore failing Create SQ/CQ commands, we can continue with less
1395          * than the desired aount of queues, and even a controller without
1396          * I/O queues an still be used to issue admin commands.  This might
1397          * be useful to upgrade a buggy firmware for example.
1398          */
1399         return ret >= 0 ? 0 : ret;
1400 }
1401
1402 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1403 {
1404         u64 szu, size, offset;
1405         u32 cmbloc;
1406         resource_size_t bar_size;
1407         struct pci_dev *pdev = to_pci_dev(dev->dev);
1408         void __iomem *cmb;
1409         dma_addr_t dma_addr;
1410
1411         if (!use_cmb_sqes)
1412                 return NULL;
1413
1414         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1415         if (!(NVME_CMB_SZ(dev->cmbsz)))
1416                 return NULL;
1417
1418         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1419
1420         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1421         size = szu * NVME_CMB_SZ(dev->cmbsz);
1422         offset = szu * NVME_CMB_OFST(cmbloc);
1423         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1424
1425         if (offset > bar_size)
1426                 return NULL;
1427
1428         /*
1429          * Controllers may support a CMB size larger than their BAR,
1430          * for example, due to being behind a bridge. Reduce the CMB to
1431          * the reported size of the BAR
1432          */
1433         if (size > bar_size - offset)
1434                 size = bar_size - offset;
1435
1436         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1437         cmb = ioremap_wc(dma_addr, size);
1438         if (!cmb)
1439                 return NULL;
1440
1441         dev->cmb_dma_addr = dma_addr;
1442         dev->cmb_size = size;
1443         return cmb;
1444 }
1445
1446 static inline void nvme_release_cmb(struct nvme_dev *dev)
1447 {
1448         if (dev->cmb) {
1449                 iounmap(dev->cmb);
1450                 dev->cmb = NULL;
1451         }
1452 }
1453
1454 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1455 {
1456         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1457 }
1458
1459 static int nvme_setup_io_queues(struct nvme_dev *dev)
1460 {
1461         struct nvme_queue *adminq = dev->queues[0];
1462         struct pci_dev *pdev = to_pci_dev(dev->dev);
1463         int result, i, vecs, nr_io_queues, size;
1464
1465         nr_io_queues = num_possible_cpus();
1466         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1467         if (result < 0)
1468                 return result;
1469
1470         /*
1471          * Degraded controllers might return an error when setting the queue
1472          * count.  We still want to be able to bring them online and offer
1473          * access to the admin queue, as that might be only way to fix them up.
1474          */
1475         if (result > 0) {
1476                 dev_err(dev->ctrl.device,
1477                         "Could not set queue count (%d)\n", result);
1478                 nr_io_queues = 0;
1479                 result = 0;
1480         }
1481
1482         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1483                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1484                                 sizeof(struct nvme_command));
1485                 if (result > 0)
1486                         dev->q_depth = result;
1487                 else
1488                         nvme_release_cmb(dev);
1489         }
1490
1491         size = db_bar_size(dev, nr_io_queues);
1492         if (size > 8192) {
1493                 iounmap(dev->bar);
1494                 do {
1495                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1496                         if (dev->bar)
1497                                 break;
1498                         if (!--nr_io_queues)
1499                                 return -ENOMEM;
1500                         size = db_bar_size(dev, nr_io_queues);
1501                 } while (1);
1502                 dev->dbs = dev->bar + 4096;
1503                 adminq->q_db = dev->dbs;
1504         }
1505
1506         /* Deregister the admin queue's interrupt */
1507         free_irq(dev->entry[0].vector, adminq);
1508
1509         /*
1510          * If we enable msix early due to not intx, disable it again before
1511          * setting up the full range we need.
1512          */
1513         if (!pdev->irq)
1514                 pci_disable_msix(pdev);
1515
1516         for (i = 0; i < nr_io_queues; i++)
1517                 dev->entry[i].entry = i;
1518         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1519         if (vecs < 0) {
1520                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1521                 if (vecs < 0) {
1522                         vecs = 1;
1523                 } else {
1524                         for (i = 0; i < vecs; i++)
1525                                 dev->entry[i].vector = i + pdev->irq;
1526                 }
1527         }
1528
1529         /*
1530          * Should investigate if there's a performance win from allocating
1531          * more queues than interrupt vectors; it might allow the submission
1532          * path to scale better, even if the receive path is limited by the
1533          * number of interrupts.
1534          */
1535         nr_io_queues = vecs;
1536         dev->max_qid = nr_io_queues;
1537
1538         result = queue_request_irq(dev, adminq, adminq->irqname);
1539         if (result) {
1540                 adminq->cq_vector = -1;
1541                 goto free_queues;
1542         }
1543         return nvme_create_io_queues(dev);
1544
1545  free_queues:
1546         nvme_free_queues(dev, 1);
1547         return result;
1548 }
1549
1550 static void nvme_set_irq_hints(struct nvme_dev *dev)
1551 {
1552         struct nvme_queue *nvmeq;
1553         int i;
1554
1555         for (i = 0; i < dev->online_queues; i++) {
1556                 nvmeq = dev->queues[i];
1557
1558                 if (!nvmeq->tags || !(*nvmeq->tags))
1559                         continue;
1560
1561                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1562                                         blk_mq_tags_cpumask(*nvmeq->tags));
1563         }
1564 }
1565
1566 static void nvme_dev_scan(struct work_struct *work)
1567 {
1568         struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
1569
1570         if (!dev->tagset.tags)
1571                 return;
1572         nvme_scan_namespaces(&dev->ctrl);
1573         nvme_set_irq_hints(dev);
1574 }
1575
1576 static void nvme_del_queue_end(struct request *req, int error)
1577 {
1578         struct nvme_queue *nvmeq = req->end_io_data;
1579
1580         blk_mq_free_request(req);
1581         complete(&nvmeq->dev->ioq_wait);
1582 }
1583
1584 static void nvme_del_cq_end(struct request *req, int error)
1585 {
1586         struct nvme_queue *nvmeq = req->end_io_data;
1587
1588         if (!error) {
1589                 unsigned long flags;
1590
1591                 spin_lock_irqsave(&nvmeq->q_lock, flags);
1592                 nvme_process_cq(nvmeq);
1593                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1594         }
1595
1596         nvme_del_queue_end(req, error);
1597 }
1598
1599 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1600 {
1601         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1602         struct request *req;
1603         struct nvme_command cmd;
1604
1605         memset(&cmd, 0, sizeof(cmd));
1606         cmd.delete_queue.opcode = opcode;
1607         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1608
1609         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
1610         if (IS_ERR(req))
1611                 return PTR_ERR(req);
1612
1613         req->timeout = ADMIN_TIMEOUT;
1614         req->end_io_data = nvmeq;
1615
1616         blk_execute_rq_nowait(q, NULL, req, false,
1617                         opcode == nvme_admin_delete_cq ?
1618                                 nvme_del_cq_end : nvme_del_queue_end);
1619         return 0;
1620 }
1621
1622 static void nvme_disable_io_queues(struct nvme_dev *dev)
1623 {
1624         int pass;
1625         unsigned long timeout;
1626         u8 opcode = nvme_admin_delete_sq;
1627
1628         for (pass = 0; pass < 2; pass++) {
1629                 int sent = 0, i = dev->queue_count - 1;
1630
1631                 reinit_completion(&dev->ioq_wait);
1632  retry:
1633                 timeout = ADMIN_TIMEOUT;
1634                 for (; i > 0; i--) {
1635                         struct nvme_queue *nvmeq = dev->queues[i];
1636
1637                         if (!pass)
1638                                 nvme_suspend_queue(nvmeq);
1639                         if (nvme_delete_queue(nvmeq, opcode))
1640                                 break;
1641                         ++sent;
1642                 }
1643                 while (sent--) {
1644                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1645                         if (timeout == 0)
1646                                 return;
1647                         if (i)
1648                                 goto retry;
1649                 }
1650                 opcode = nvme_admin_delete_cq;
1651         }
1652 }
1653
1654 /*
1655  * Return: error value if an error occurred setting up the queues or calling
1656  * Identify Device.  0 if these succeeded, even if adding some of the
1657  * namespaces failed.  At the moment, these failures are silent.  TBD which
1658  * failures should be reported.
1659  */
1660 static int nvme_dev_add(struct nvme_dev *dev)
1661 {
1662         if (!dev->ctrl.tagset) {
1663                 dev->tagset.ops = &nvme_mq_ops;
1664                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1665                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1666                 dev->tagset.numa_node = dev_to_node(dev->dev);
1667                 dev->tagset.queue_depth =
1668                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1669                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1670                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1671                 dev->tagset.driver_data = dev;
1672
1673                 if (blk_mq_alloc_tag_set(&dev->tagset))
1674                         return 0;
1675                 dev->ctrl.tagset = &dev->tagset;
1676         } else {
1677                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1678
1679                 /* Free previously allocated queues that are no longer usable */
1680                 nvme_free_queues(dev, dev->online_queues);
1681         }
1682
1683         queue_work(nvme_workq, &dev->scan_work);
1684         return 0;
1685 }
1686
1687 static int nvme_dev_map(struct nvme_dev *dev)
1688 {
1689         u64 cap;
1690         int bars, result = -ENOMEM;
1691         struct pci_dev *pdev = to_pci_dev(dev->dev);
1692
1693         if (pci_enable_device_mem(pdev))
1694                 return result;
1695
1696         dev->entry[0].vector = pdev->irq;
1697         pci_set_master(pdev);
1698         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1699         if (!bars)
1700                 goto disable_pci;
1701
1702         if (pci_request_selected_regions(pdev, bars, "nvme"))
1703                 goto disable_pci;
1704
1705         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1706             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1707                 goto disable;
1708
1709         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1710         if (!dev->bar)
1711                 goto disable;
1712
1713         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1714                 result = -ENODEV;
1715                 goto unmap;
1716         }
1717
1718         /*
1719          * Some devices don't advertse INTx interrupts, pre-enable a single
1720          * MSIX vec for setup. We'll adjust this later.
1721          */
1722         if (!pdev->irq) {
1723                 result = pci_enable_msix(pdev, dev->entry, 1);
1724                 if (result < 0)
1725                         goto unmap;
1726         }
1727
1728         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1729
1730         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1731         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1732         dev->dbs = dev->bar + 4096;
1733
1734         /*
1735          * Temporary fix for the Apple controller found in the MacBook8,1 and
1736          * some MacBook7,1 to avoid controller resets and data loss.
1737          */
1738         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1739                 dev->q_depth = 2;
1740                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1741                         "queue depth=%u to work around controller resets\n",
1742                         dev->q_depth);
1743         }
1744
1745         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1746                 dev->cmb = nvme_map_cmb(dev);
1747
1748         pci_enable_pcie_error_reporting(pdev);
1749         pci_save_state(pdev);
1750         return 0;
1751
1752  unmap:
1753         iounmap(dev->bar);
1754         dev->bar = NULL;
1755  disable:
1756         pci_release_regions(pdev);
1757  disable_pci:
1758         pci_disable_device(pdev);
1759         return result;
1760 }
1761
1762 static void nvme_dev_unmap(struct nvme_dev *dev)
1763 {
1764         struct pci_dev *pdev = to_pci_dev(dev->dev);
1765
1766         if (pdev->msi_enabled)
1767                 pci_disable_msi(pdev);
1768         else if (pdev->msix_enabled)
1769                 pci_disable_msix(pdev);
1770
1771         if (dev->bar) {
1772                 iounmap(dev->bar);
1773                 dev->bar = NULL;
1774                 pci_release_regions(pdev);
1775         }
1776
1777         if (pci_is_enabled(pdev)) {
1778                 pci_disable_pcie_error_reporting(pdev);
1779                 pci_disable_device(pdev);
1780         }
1781 }
1782
1783 static int nvme_dev_list_add(struct nvme_dev *dev)
1784 {
1785         bool start_thread = false;
1786
1787         spin_lock(&dev_list_lock);
1788         if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
1789                 start_thread = true;
1790                 nvme_thread = NULL;
1791         }
1792         list_add(&dev->node, &dev_list);
1793         spin_unlock(&dev_list_lock);
1794
1795         if (start_thread) {
1796                 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1797                 wake_up_all(&nvme_kthread_wait);
1798         } else
1799                 wait_event_killable(nvme_kthread_wait, nvme_thread);
1800
1801         if (IS_ERR_OR_NULL(nvme_thread))
1802                 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
1803
1804         return 0;
1805 }
1806
1807 /*
1808 * Remove the node from the device list and check
1809 * for whether or not we need to stop the nvme_thread.
1810 */
1811 static void nvme_dev_list_remove(struct nvme_dev *dev)
1812 {
1813         struct task_struct *tmp = NULL;
1814
1815         spin_lock(&dev_list_lock);
1816         list_del_init(&dev->node);
1817         if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
1818                 tmp = nvme_thread;
1819                 nvme_thread = NULL;
1820         }
1821         spin_unlock(&dev_list_lock);
1822
1823         if (tmp)
1824                 kthread_stop(tmp);
1825 }
1826
1827 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1828 {
1829         int i;
1830         u32 csts = -1;
1831
1832         nvme_dev_list_remove(dev);
1833
1834         mutex_lock(&dev->shutdown_lock);
1835         if (dev->bar) {
1836                 nvme_stop_queues(&dev->ctrl);
1837                 csts = readl(dev->bar + NVME_REG_CSTS);
1838         }
1839         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1840                 for (i = dev->queue_count - 1; i >= 0; i--) {
1841                         struct nvme_queue *nvmeq = dev->queues[i];
1842                         nvme_suspend_queue(nvmeq);
1843                 }
1844         } else {
1845                 nvme_disable_io_queues(dev);
1846                 nvme_disable_admin_queue(dev, shutdown);
1847         }
1848         nvme_dev_unmap(dev);
1849
1850         for (i = dev->queue_count - 1; i >= 0; i--)
1851                 nvme_clear_queue(dev->queues[i]);
1852         mutex_unlock(&dev->shutdown_lock);
1853 }
1854
1855 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1856 {
1857         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1858                                                 PAGE_SIZE, PAGE_SIZE, 0);
1859         if (!dev->prp_page_pool)
1860                 return -ENOMEM;
1861
1862         /* Optimisation for I/Os between 4k and 128k */
1863         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1864                                                 256, 256, 0);
1865         if (!dev->prp_small_pool) {
1866                 dma_pool_destroy(dev->prp_page_pool);
1867                 return -ENOMEM;
1868         }
1869         return 0;
1870 }
1871
1872 static void nvme_release_prp_pools(struct nvme_dev *dev)
1873 {
1874         dma_pool_destroy(dev->prp_page_pool);
1875         dma_pool_destroy(dev->prp_small_pool);
1876 }
1877
1878 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1879 {
1880         struct nvme_dev *dev = to_nvme_dev(ctrl);
1881
1882         put_device(dev->dev);
1883         if (dev->tagset.tags)
1884                 blk_mq_free_tag_set(&dev->tagset);
1885         if (dev->ctrl.admin_q)
1886                 blk_put_queue(dev->ctrl.admin_q);
1887         kfree(dev->queues);
1888         kfree(dev->entry);
1889         kfree(dev);
1890 }
1891
1892 static void nvme_reset_work(struct work_struct *work)
1893 {
1894         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1895         int result;
1896
1897         if (WARN_ON(test_bit(NVME_CTRL_RESETTING, &dev->flags)))
1898                 goto out;
1899
1900         /*
1901          * If we're called to reset a live controller first shut it down before
1902          * moving on.
1903          */
1904         if (dev->bar)
1905                 nvme_dev_disable(dev, false);
1906
1907         set_bit(NVME_CTRL_RESETTING, &dev->flags);
1908
1909         result = nvme_dev_map(dev);
1910         if (result)
1911                 goto out;
1912
1913         result = nvme_configure_admin_queue(dev);
1914         if (result)
1915                 goto unmap;
1916
1917         nvme_init_queue(dev->queues[0], 0);
1918         result = nvme_alloc_admin_tags(dev);
1919         if (result)
1920                 goto disable;
1921
1922         result = nvme_init_identify(&dev->ctrl);
1923         if (result)
1924                 goto free_tags;
1925
1926         result = nvme_setup_io_queues(dev);
1927         if (result)
1928                 goto free_tags;
1929
1930         dev->ctrl.event_limit = NVME_NR_AEN_COMMANDS;
1931
1932         result = nvme_dev_list_add(dev);
1933         if (result)
1934                 goto remove;
1935
1936         /*
1937          * Keep the controller around but remove all namespaces if we don't have
1938          * any working I/O queue.
1939          */
1940         if (dev->online_queues < 2) {
1941                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1942                 nvme_remove_namespaces(&dev->ctrl);
1943         } else {
1944                 nvme_start_queues(&dev->ctrl);
1945                 nvme_dev_add(dev);
1946         }
1947
1948         clear_bit(NVME_CTRL_RESETTING, &dev->flags);
1949         return;
1950
1951  remove:
1952         nvme_dev_list_remove(dev);
1953  free_tags:
1954         nvme_dev_remove_admin(dev);
1955         blk_put_queue(dev->ctrl.admin_q);
1956         dev->ctrl.admin_q = NULL;
1957         dev->queues[0]->tags = NULL;
1958  disable:
1959         nvme_disable_admin_queue(dev, false);
1960  unmap:
1961         nvme_dev_unmap(dev);
1962  out:
1963         nvme_remove_dead_ctrl(dev);
1964 }
1965
1966 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1967 {
1968         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1969         struct pci_dev *pdev = to_pci_dev(dev->dev);
1970
1971         if (pci_get_drvdata(pdev))
1972                 pci_stop_and_remove_bus_device_locked(pdev);
1973         nvme_put_ctrl(&dev->ctrl);
1974 }
1975
1976 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
1977 {
1978         dev_warn(dev->ctrl.device, "Removing after probe failure\n");
1979         kref_get(&dev->ctrl.kref);
1980         if (!schedule_work(&dev->remove_work))
1981                 nvme_put_ctrl(&dev->ctrl);
1982 }
1983
1984 static int nvme_reset(struct nvme_dev *dev)
1985 {
1986         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1987                 return -ENODEV;
1988
1989         if (!queue_work(nvme_workq, &dev->reset_work))
1990                 return -EBUSY;
1991
1992         flush_work(&dev->reset_work);
1993         return 0;
1994 }
1995
1996 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1997 {
1998         *val = readl(to_nvme_dev(ctrl)->bar + off);
1999         return 0;
2000 }
2001
2002 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2003 {
2004         writel(val, to_nvme_dev(ctrl)->bar + off);
2005         return 0;
2006 }
2007
2008 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2009 {
2010         *val = readq(to_nvme_dev(ctrl)->bar + off);
2011         return 0;
2012 }
2013
2014 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl)
2015 {
2016         struct nvme_dev *dev = to_nvme_dev(ctrl);
2017
2018         return !dev->bar || dev->online_queues < 2;
2019 }
2020
2021 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
2022 {
2023         return nvme_reset(to_nvme_dev(ctrl));
2024 }
2025
2026 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2027         .module                 = THIS_MODULE,
2028         .reg_read32             = nvme_pci_reg_read32,
2029         .reg_write32            = nvme_pci_reg_write32,
2030         .reg_read64             = nvme_pci_reg_read64,
2031         .io_incapable           = nvme_pci_io_incapable,
2032         .reset_ctrl             = nvme_pci_reset_ctrl,
2033         .free_ctrl              = nvme_pci_free_ctrl,
2034 };
2035
2036 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2037 {
2038         int node, result = -ENOMEM;
2039         struct nvme_dev *dev;
2040
2041         node = dev_to_node(&pdev->dev);
2042         if (node == NUMA_NO_NODE)
2043                 set_dev_node(&pdev->dev, 0);
2044
2045         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2046         if (!dev)
2047                 return -ENOMEM;
2048         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2049                                                         GFP_KERNEL, node);
2050         if (!dev->entry)
2051                 goto free;
2052         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2053                                                         GFP_KERNEL, node);
2054         if (!dev->queues)
2055                 goto free;
2056
2057         dev->dev = get_device(&pdev->dev);
2058         pci_set_drvdata(pdev, dev);
2059
2060         INIT_LIST_HEAD(&dev->node);
2061         INIT_WORK(&dev->scan_work, nvme_dev_scan);
2062         INIT_WORK(&dev->reset_work, nvme_reset_work);
2063         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2064         mutex_init(&dev->shutdown_lock);
2065         init_completion(&dev->ioq_wait);
2066
2067         result = nvme_setup_prp_pools(dev);
2068         if (result)
2069                 goto put_pci;
2070
2071         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2072                         id->driver_data);
2073         if (result)
2074                 goto release_pools;
2075
2076         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2077
2078         queue_work(nvme_workq, &dev->reset_work);
2079         return 0;
2080
2081  release_pools:
2082         nvme_release_prp_pools(dev);
2083  put_pci:
2084         put_device(dev->dev);
2085  free:
2086         kfree(dev->queues);
2087         kfree(dev->entry);
2088         kfree(dev);
2089         return result;
2090 }
2091
2092 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2093 {
2094         struct nvme_dev *dev = pci_get_drvdata(pdev);
2095
2096         if (prepare)
2097                 nvme_dev_disable(dev, false);
2098         else
2099                 queue_work(nvme_workq, &dev->reset_work);
2100 }
2101
2102 static void nvme_shutdown(struct pci_dev *pdev)
2103 {
2104         struct nvme_dev *dev = pci_get_drvdata(pdev);
2105         nvme_dev_disable(dev, true);
2106 }
2107
2108 static void nvme_remove(struct pci_dev *pdev)
2109 {
2110         struct nvme_dev *dev = pci_get_drvdata(pdev);
2111
2112         spin_lock(&dev_list_lock);
2113         list_del_init(&dev->node);
2114         spin_unlock(&dev_list_lock);
2115
2116         pci_set_drvdata(pdev, NULL);
2117         flush_work(&dev->reset_work);
2118         flush_work(&dev->scan_work);
2119         nvme_remove_namespaces(&dev->ctrl);
2120         nvme_uninit_ctrl(&dev->ctrl);
2121         nvme_dev_disable(dev, true);
2122         nvme_dev_remove_admin(dev);
2123         nvme_free_queues(dev, 0);
2124         nvme_release_cmb(dev);
2125         nvme_release_prp_pools(dev);
2126         nvme_put_ctrl(&dev->ctrl);
2127 }
2128
2129 #ifdef CONFIG_PM_SLEEP
2130 static int nvme_suspend(struct device *dev)
2131 {
2132         struct pci_dev *pdev = to_pci_dev(dev);
2133         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2134
2135         nvme_dev_disable(ndev, true);
2136         return 0;
2137 }
2138
2139 static int nvme_resume(struct device *dev)
2140 {
2141         struct pci_dev *pdev = to_pci_dev(dev);
2142         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2143
2144         queue_work(nvme_workq, &ndev->reset_work);
2145         return 0;
2146 }
2147 #endif
2148
2149 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2150
2151 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2152                                                 pci_channel_state_t state)
2153 {
2154         struct nvme_dev *dev = pci_get_drvdata(pdev);
2155
2156         /*
2157          * A frozen channel requires a reset. When detected, this method will
2158          * shutdown the controller to quiesce. The controller will be restarted
2159          * after the slot reset through driver's slot_reset callback.
2160          */
2161         dev_warn(dev->ctrl.device, "error detected: state:%d\n", state);
2162         switch (state) {
2163         case pci_channel_io_normal:
2164                 return PCI_ERS_RESULT_CAN_RECOVER;
2165         case pci_channel_io_frozen:
2166                 nvme_dev_disable(dev, false);
2167                 return PCI_ERS_RESULT_NEED_RESET;
2168         case pci_channel_io_perm_failure:
2169                 return PCI_ERS_RESULT_DISCONNECT;
2170         }
2171         return PCI_ERS_RESULT_NEED_RESET;
2172 }
2173
2174 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2175 {
2176         struct nvme_dev *dev = pci_get_drvdata(pdev);
2177
2178         dev_info(dev->ctrl.device, "restart after slot reset\n");
2179         pci_restore_state(pdev);
2180         queue_work(nvme_workq, &dev->reset_work);
2181         return PCI_ERS_RESULT_RECOVERED;
2182 }
2183
2184 static void nvme_error_resume(struct pci_dev *pdev)
2185 {
2186         pci_cleanup_aer_uncorrect_error_status(pdev);
2187 }
2188
2189 static const struct pci_error_handlers nvme_err_handler = {
2190         .error_detected = nvme_error_detected,
2191         .slot_reset     = nvme_slot_reset,
2192         .resume         = nvme_error_resume,
2193         .reset_notify   = nvme_reset_notify,
2194 };
2195
2196 /* Move to pci_ids.h later */
2197 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2198
2199 static const struct pci_device_id nvme_id_table[] = {
2200         { PCI_VDEVICE(INTEL, 0x0953),
2201                 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
2202         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2203                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2204         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2205         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2206         { 0, }
2207 };
2208 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2209
2210 static struct pci_driver nvme_driver = {
2211         .name           = "nvme",
2212         .id_table       = nvme_id_table,
2213         .probe          = nvme_probe,
2214         .remove         = nvme_remove,
2215         .shutdown       = nvme_shutdown,
2216         .driver         = {
2217                 .pm     = &nvme_dev_pm_ops,
2218         },
2219         .err_handler    = &nvme_err_handler,
2220 };
2221
2222 static int __init nvme_init(void)
2223 {
2224         int result;
2225
2226         init_waitqueue_head(&nvme_kthread_wait);
2227
2228         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2229         if (!nvme_workq)
2230                 return -ENOMEM;
2231
2232         result = nvme_core_init();
2233         if (result < 0)
2234                 goto kill_workq;
2235
2236         result = pci_register_driver(&nvme_driver);
2237         if (result)
2238                 goto core_exit;
2239         return 0;
2240
2241  core_exit:
2242         nvme_core_exit();
2243  kill_workq:
2244         destroy_workqueue(nvme_workq);
2245         return result;
2246 }
2247
2248 static void __exit nvme_exit(void)
2249 {
2250         pci_unregister_driver(&nvme_driver);
2251         nvme_core_exit();
2252         destroy_workqueue(nvme_workq);
2253         BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
2254         _nvme_check_size();
2255 }
2256
2257 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2258 MODULE_LICENSE("GPL");
2259 MODULE_VERSION("1.0");
2260 module_init(nvme_init);
2261 module_exit(nvme_exit);