2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
31 #include <linux/list_sort.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
47 #include <uapi/linux/nvme_ioctl.h>
50 #define NVME_MINORS (1U << MINORBITS)
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55 #define ADMIN_TIMEOUT (admin_timeout * HZ)
56 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
58 static unsigned char admin_timeout = 60;
59 module_param(admin_timeout, byte, 0644);
60 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
62 unsigned char nvme_io_timeout = 30;
63 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
64 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
66 static unsigned char shutdown_timeout = 5;
67 module_param(shutdown_timeout, byte, 0644);
68 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
70 static int nvme_major;
71 module_param(nvme_major, int, 0);
73 static int nvme_char_major;
74 module_param(nvme_char_major, int, 0);
76 static int use_threaded_interrupts;
77 module_param(use_threaded_interrupts, int, 0);
79 static bool use_cmb_sqes = true;
80 module_param(use_cmb_sqes, bool, 0644);
81 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
83 static DEFINE_SPINLOCK(dev_list_lock);
84 static LIST_HEAD(dev_list);
85 static struct task_struct *nvme_thread;
86 static struct workqueue_struct *nvme_workq;
87 static wait_queue_head_t nvme_kthread_wait;
89 static struct class *nvme_class;
91 static int __nvme_reset(struct nvme_dev *dev);
92 static int nvme_reset(struct nvme_dev *dev);
93 static void nvme_process_cq(struct nvme_queue *nvmeq);
94 static void nvme_dead_ctrl(struct nvme_dev *dev);
96 struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
110 struct device *q_dmadev;
111 struct nvme_dev *dev;
112 char irqname[24]; /* nvme4294967295-65535\0 */
114 struct nvme_command *sq_cmds;
115 struct nvme_command __iomem *sq_cmds_io;
116 volatile struct nvme_completion *cqes;
117 struct blk_mq_tags **tags;
118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
129 struct async_cmd_info cmdinfo;
133 * Check we didin't inadvertently grow the command struct
135 static inline void _nvme_check_size(void)
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
151 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
152 struct nvme_completion *);
154 struct nvme_cmd_info {
155 nvme_completion_fn fn;
158 struct nvme_queue *nvmeq;
159 struct nvme_iod iod[0];
163 * Max size of iod being embedded in the request payload
165 #define NVME_INT_PAGES 2
166 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
167 #define NVME_INT_MASK 0x01
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
174 static int nvme_npages(unsigned size, struct nvme_dev *dev)
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
180 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
182 unsigned int ret = sizeof(struct nvme_cmd_info);
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
191 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
201 hctx->driver_data = nvmeq;
202 nvmeq->tags = &dev->admin_tagset.tags[0];
206 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
208 struct nvme_queue *nvmeq = hctx->driver_data;
213 static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
226 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
229 struct nvme_dev *dev = data;
230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
236 hctx->driver_data = nvmeq;
240 static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
253 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
262 static void *iod_get_private(struct nvme_iod *iod)
264 return (void *) (iod->private & ~0x1UL);
268 * If bit 0 is set, the iod is embedded in the request payload.
270 static bool iod_should_kfree(struct nvme_iod *iod)
272 return (iod->private & NVME_INT_MASK) == 0;
275 /* Special values must be less than 0x1000 */
276 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
277 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
281 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
282 struct nvme_completion *cqe)
284 if (ctx == CMD_CTX_CANCELLED)
286 if (ctx == CMD_CTX_COMPLETED) {
287 dev_warn(nvmeq->q_dmadev,
288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
292 if (ctx == CMD_CTX_INVALID) {
293 dev_warn(nvmeq->q_dmadev,
294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
301 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
313 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
321 if (status != NVME_SC_SUCCESS)
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
333 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
336 struct request *req = ctx;
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
341 blk_mq_free_request(req);
343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
347 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
354 blk_mq_free_request(cmdinfo->req);
357 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
362 return blk_mq_rq_to_pdu(req);
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
368 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
387 * @nvmeq: The queue to use
388 * @cmd: The command to send
390 * Safe to use from interrupt context
392 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
395 u16 tail = nvmeq->sq_tail;
397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
402 if (++tail == nvmeq->q_depth)
404 writel(tail, nvmeq->q_db);
405 nvmeq->sq_tail = tail;
408 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
411 spin_lock_irqsave(&nvmeq->q_lock, flags);
412 __nvme_submit_cmd(nvmeq, cmd);
413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
416 static __le64 **iod_list(struct nvme_iod *iod)
418 return ((void *)iod) + iod->offset;
421 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
427 iod->length = nbytes;
431 static struct nvme_iod *
432 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
437 sizeof(struct scatterlist) * nseg, gfp);
440 iod_init(iod, bytes, nseg, priv);
445 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
450 struct nvme_iod *iod;
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
457 iod_init(iod, size, rq->nr_phys_segments,
458 (unsigned long) rq | NVME_INT_MASK);
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
466 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
468 const int last_prp = dev->page_size / 8 - 1;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
482 if (iod_should_kfree(iod))
486 static int nvme_error_status(u16 status)
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
491 case NVME_SC_CAP_EXCEEDED:
498 #ifdef CONFIG_BLK_DEV_INTEGRITY
499 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
505 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
521 static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
528 u32 i, nlb, ts, phys, virt;
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
533 bip = bio_integrity(req->bio);
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
543 ts = ns->disk->queue->integrity.tuple_size;
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
553 static void nvme_init_integrity(struct nvme_ns *ns)
555 struct blk_integrity integrity;
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
559 integrity.profile = &t10_pi_type3_crc;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
563 integrity.profile = &t10_pi_type1_crc;
566 integrity.profile = NULL;
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
573 #else /* CONFIG_BLK_DEV_INTEGRITY */
574 static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
578 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
581 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
584 static void nvme_init_integrity(struct nvme_ns *ns)
589 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
590 struct nvme_completion *cqe)
592 struct nvme_iod *iod = ctx;
593 struct request *req = iod_get_private(iod);
594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
595 u16 status = le16_to_cpup(&cqe->status) >> 1;
596 bool requeue = false;
599 if (unlikely(status)) {
600 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
601 && (jiffies - req->start_time) < req->timeout) {
605 blk_mq_requeue_request(req);
606 spin_lock_irqsave(req->q->queue_lock, flags);
607 if (!blk_queue_stopped(req->q))
608 blk_mq_kick_requeue_list(req->q);
609 spin_unlock_irqrestore(req->q->queue_lock, flags);
613 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
614 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
619 error = nvme_error_status(status);
623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
624 u32 result = le32_to_cpup(&cqe->result);
625 req->special = (void *)(uintptr_t)result;
629 dev_warn(nvmeq->dev->dev,
630 "completing aborted command with status:%04x\n",
635 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
636 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
637 if (blk_integrity_rq(req)) {
638 if (!rq_data_dir(req))
639 nvme_dif_remap(req, nvme_dif_complete);
640 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
641 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
644 nvme_free_iod(nvmeq->dev, iod);
646 if (likely(!requeue))
647 blk_mq_complete_request(req, error);
650 /* length is in bytes. gfp flags indicates whether we may sleep. */
651 static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
654 struct dma_pool *pool;
655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
662 __le64 **list = iod_list(iod);
666 length -= (page_size - offset);
670 dma_len -= (page_size - offset);
672 dma_addr += (page_size - offset);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
679 if (length <= page_size) {
680 iod->first_dma = dma_addr;
684 nprps = DIV_ROUND_UP(length, page_size);
685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
689 pool = dev->prp_page_pool;
693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
695 iod->first_dma = dma_addr;
697 return (total_len - length) + page_size;
700 iod->first_dma = prp_dma;
703 if (i == page_size >> 3) {
704 __le64 *old_prp_list = prp_list;
705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
707 return total_len - length;
708 list[iod->npages++] = prp_list;
709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
713 prp_list[i++] = cpu_to_le64(dma_addr);
714 dma_len -= page_size;
715 dma_addr += page_size;
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
730 static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
733 struct nvme_command cmnd;
735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
737 if (req->nr_phys_segments) {
738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
742 __nvme_submit_cmd(nvmeq, &cmnd);
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
750 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
755 struct nvme_command cmnd;
757 range->cattr = cpu_to_le32(0);
758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
769 __nvme_submit_cmd(nvmeq, &cmnd);
772 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
775 struct nvme_command cmnd;
777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
782 __nvme_submit_cmd(nvmeq, &cmnd);
785 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
788 struct request *req = iod_get_private(iod);
789 struct nvme_command cmnd;
793 if (req->cmd_flags & REQ_FUA)
794 control |= NVME_RW_FUA;
795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
796 control |= NVME_RW_LR;
798 if (req->cmd_flags & REQ_RAHEAD)
799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
811 switch (ns->pi_type) {
812 case NVME_NS_DPS_PI_TYPE3:
813 control |= NVME_RW_PRINFO_PRCHK_GUARD;
815 case NVME_NS_DPS_PI_TYPE1:
816 case NVME_NS_DPS_PI_TYPE2:
817 control |= NVME_RW_PRINFO_PRCHK_GUARD |
818 NVME_RW_PRINFO_PRCHK_REF;
819 cmnd.rw.reftag = cpu_to_le32(
820 nvme_block_nr(ns, blk_rq_pos(req)));
823 if (blk_integrity_rq(req))
825 cpu_to_le64(sg_dma_address(iod->meta_sg));
827 control |= NVME_RW_PRINFO_PRACT;
830 cmnd.rw.control = cpu_to_le16(control);
831 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
833 __nvme_submit_cmd(nvmeq, &cmnd);
839 * NOTE: ns is NULL when called on the admin queue.
841 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
842 const struct blk_mq_queue_data *bd)
844 struct nvme_ns *ns = hctx->queue->queuedata;
845 struct nvme_queue *nvmeq = hctx->driver_data;
846 struct nvme_dev *dev = nvmeq->dev;
847 struct request *req = bd->rq;
848 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
849 struct nvme_iod *iod;
850 enum dma_data_direction dma_dir;
853 * If formated with metadata, require the block layer provide a buffer
854 * unless this namespace is formated such that the metadata can be
855 * stripped/generated by the controller with PRACT=1.
857 if (ns && ns->ms && !blk_integrity_rq(req)) {
858 if (!(ns->pi_type && ns->ms == 8) &&
859 req->cmd_type != REQ_TYPE_DRV_PRIV) {
860 blk_mq_complete_request(req, -EFAULT);
861 return BLK_MQ_RQ_QUEUE_OK;
865 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
867 return BLK_MQ_RQ_QUEUE_BUSY;
869 if (req->cmd_flags & REQ_DISCARD) {
872 * We reuse the small pool to allocate the 16-byte range here
873 * as it is not worth having a special pool for these or
874 * additional cases to handle freeing the iod.
876 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
880 iod_list(iod)[0] = (__le64 *)range;
882 } else if (req->nr_phys_segments) {
883 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
885 sg_init_table(iod->sg, req->nr_phys_segments);
886 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
890 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
893 if (blk_rq_bytes(req) !=
894 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
895 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
898 if (blk_integrity_rq(req)) {
899 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) {
900 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
905 sg_init_table(iod->meta_sg, 1);
906 if (blk_rq_map_integrity_sg(
907 req->q, req->bio, iod->meta_sg) != 1) {
908 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
913 if (rq_data_dir(req))
914 nvme_dif_remap(req, nvme_dif_prep);
916 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) {
917 dma_unmap_sg(dev->dev, iod->sg, iod->nents,
924 nvme_set_info(cmd, iod, req_completion);
925 spin_lock_irq(&nvmeq->q_lock);
926 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
927 nvme_submit_priv(nvmeq, req, iod);
928 else if (req->cmd_flags & REQ_DISCARD)
929 nvme_submit_discard(nvmeq, ns, req, iod);
930 else if (req->cmd_flags & REQ_FLUSH)
931 nvme_submit_flush(nvmeq, ns, req->tag);
933 nvme_submit_iod(nvmeq, iod, ns);
935 nvme_process_cq(nvmeq);
936 spin_unlock_irq(&nvmeq->q_lock);
937 return BLK_MQ_RQ_QUEUE_OK;
940 nvme_free_iod(dev, iod);
941 return BLK_MQ_RQ_QUEUE_ERROR;
943 nvme_free_iod(dev, iod);
944 return BLK_MQ_RQ_QUEUE_BUSY;
947 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
951 head = nvmeq->cq_head;
952 phase = nvmeq->cq_phase;
956 nvme_completion_fn fn;
957 struct nvme_completion cqe = nvmeq->cqes[head];
958 if ((le16_to_cpu(cqe.status) & 1) != phase)
960 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
961 if (++head == nvmeq->q_depth) {
965 if (tag && *tag == cqe.command_id)
967 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
968 fn(nvmeq, ctx, &cqe);
971 /* If the controller ignores the cq head doorbell and continuously
972 * writes to the queue, it is theoretically possible to wrap around
973 * the queue twice and mistakenly return IRQ_NONE. Linux only
974 * requires that 0.1% of your interrupts are handled, so this isn't
977 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
980 if (likely(nvmeq->cq_vector >= 0))
981 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
982 nvmeq->cq_head = head;
983 nvmeq->cq_phase = phase;
988 static void nvme_process_cq(struct nvme_queue *nvmeq)
990 __nvme_process_cq(nvmeq, NULL);
993 static irqreturn_t nvme_irq(int irq, void *data)
996 struct nvme_queue *nvmeq = data;
997 spin_lock(&nvmeq->q_lock);
998 nvme_process_cq(nvmeq);
999 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
1000 nvmeq->cqe_seen = 0;
1001 spin_unlock(&nvmeq->q_lock);
1005 static irqreturn_t nvme_irq_check(int irq, void *data)
1007 struct nvme_queue *nvmeq = data;
1008 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1009 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1011 return IRQ_WAKE_THREAD;
1014 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
1016 struct nvme_queue *nvmeq = hctx->driver_data;
1018 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
1020 spin_lock_irq(&nvmeq->q_lock);
1021 __nvme_process_cq(nvmeq, &tag);
1022 spin_unlock_irq(&nvmeq->q_lock);
1032 * Returns 0 on success. If the result is negative, it's a Linux error code;
1033 * if the result is positive, it's an NVM Express status code
1035 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1036 void *buffer, void __user *ubuffer, unsigned bufflen,
1037 u32 *result, unsigned timeout)
1039 bool write = cmd->common.opcode & 1;
1040 struct bio *bio = NULL;
1041 struct request *req;
1044 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
1046 return PTR_ERR(req);
1048 req->cmd_type = REQ_TYPE_DRV_PRIV;
1049 req->cmd_flags |= REQ_FAILFAST_DRIVER;
1050 req->__data_len = 0;
1051 req->__sector = (sector_t) -1;
1052 req->bio = req->biotail = NULL;
1054 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1056 req->cmd = (unsigned char *)cmd;
1057 req->cmd_len = sizeof(struct nvme_command);
1058 req->special = (void *)0;
1060 if (buffer && bufflen) {
1061 ret = blk_rq_map_kern(q, req, buffer, bufflen,
1062 __GFP_DIRECT_RECLAIM);
1065 } else if (ubuffer && bufflen) {
1066 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1067 __GFP_DIRECT_RECLAIM);
1073 blk_execute_rq(req->q, NULL, req, 0);
1075 blk_rq_unmap_user(bio);
1077 *result = (u32)(uintptr_t)req->special;
1080 blk_mq_free_request(req);
1084 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1085 void *buffer, unsigned bufflen)
1087 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
1090 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1092 struct nvme_queue *nvmeq = dev->queues[0];
1093 struct nvme_command c;
1094 struct nvme_cmd_info *cmd_info;
1095 struct request *req;
1097 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
1099 return PTR_ERR(req);
1101 req->cmd_flags |= REQ_NO_TIMEOUT;
1102 cmd_info = blk_mq_rq_to_pdu(req);
1103 nvme_set_info(cmd_info, NULL, async_req_completion);
1105 memset(&c, 0, sizeof(c));
1106 c.common.opcode = nvme_admin_async_event;
1107 c.common.command_id = req->tag;
1109 blk_mq_free_request(req);
1110 __nvme_submit_cmd(nvmeq, &c);
1114 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1115 struct nvme_command *cmd,
1116 struct async_cmd_info *cmdinfo, unsigned timeout)
1118 struct nvme_queue *nvmeq = dev->queues[0];
1119 struct request *req;
1120 struct nvme_cmd_info *cmd_rq;
1122 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1124 return PTR_ERR(req);
1126 req->timeout = timeout;
1127 cmd_rq = blk_mq_rq_to_pdu(req);
1129 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1130 cmdinfo->status = -EINTR;
1132 cmd->common.command_id = req->tag;
1134 nvme_submit_cmd(nvmeq, cmd);
1138 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1140 struct nvme_command c;
1142 memset(&c, 0, sizeof(c));
1143 c.delete_queue.opcode = opcode;
1144 c.delete_queue.qid = cpu_to_le16(id);
1146 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1149 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1150 struct nvme_queue *nvmeq)
1152 struct nvme_command c;
1153 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1156 * Note: we (ab)use the fact the the prp fields survive if no data
1157 * is attached to the request.
1159 memset(&c, 0, sizeof(c));
1160 c.create_cq.opcode = nvme_admin_create_cq;
1161 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1162 c.create_cq.cqid = cpu_to_le16(qid);
1163 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1164 c.create_cq.cq_flags = cpu_to_le16(flags);
1165 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1167 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1170 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1171 struct nvme_queue *nvmeq)
1173 struct nvme_command c;
1174 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1177 * Note: we (ab)use the fact the the prp fields survive if no data
1178 * is attached to the request.
1180 memset(&c, 0, sizeof(c));
1181 c.create_sq.opcode = nvme_admin_create_sq;
1182 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1183 c.create_sq.sqid = cpu_to_le16(qid);
1184 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1185 c.create_sq.sq_flags = cpu_to_le16(flags);
1186 c.create_sq.cqid = cpu_to_le16(qid);
1188 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1191 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1193 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1196 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1198 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1201 int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
1203 struct nvme_command c = { };
1206 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1207 c.identify.opcode = nvme_admin_identify;
1208 c.identify.cns = cpu_to_le32(1);
1210 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1214 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1215 sizeof(struct nvme_id_ctrl));
1221 int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1222 struct nvme_id_ns **id)
1224 struct nvme_command c = { };
1227 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1228 c.identify.opcode = nvme_admin_identify,
1229 c.identify.nsid = cpu_to_le32(nsid),
1231 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1235 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1236 sizeof(struct nvme_id_ns));
1242 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1243 dma_addr_t dma_addr, u32 *result)
1245 struct nvme_command c;
1247 memset(&c, 0, sizeof(c));
1248 c.features.opcode = nvme_admin_get_features;
1249 c.features.nsid = cpu_to_le32(nsid);
1250 c.features.prp1 = cpu_to_le64(dma_addr);
1251 c.features.fid = cpu_to_le32(fid);
1253 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1257 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1258 dma_addr_t dma_addr, u32 *result)
1260 struct nvme_command c;
1262 memset(&c, 0, sizeof(c));
1263 c.features.opcode = nvme_admin_set_features;
1264 c.features.prp1 = cpu_to_le64(dma_addr);
1265 c.features.fid = cpu_to_le32(fid);
1266 c.features.dword11 = cpu_to_le32(dword11);
1268 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1272 int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1274 struct nvme_command c = { };
1277 c.common.opcode = nvme_admin_get_log_page,
1278 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1279 c.common.cdw10[0] = cpu_to_le32(
1280 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1283 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1287 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1288 sizeof(struct nvme_smart_log));
1295 * nvme_abort_req - Attempt aborting a request
1297 * Schedule controller reset if the command was already aborted once before and
1298 * still hasn't been returned to the driver, or if this is the admin queue.
1300 static void nvme_abort_req(struct request *req)
1302 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1303 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1304 struct nvme_dev *dev = nvmeq->dev;
1305 struct request *abort_req;
1306 struct nvme_cmd_info *abort_cmd;
1307 struct nvme_command cmd;
1309 if (!nvmeq->qid || cmd_rq->aborted) {
1310 spin_lock(&dev_list_lock);
1311 if (!__nvme_reset(dev)) {
1313 "I/O %d QID %d timeout, reset controller\n",
1314 req->tag, nvmeq->qid);
1316 spin_unlock(&dev_list_lock);
1320 if (!dev->abort_limit)
1323 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1325 if (IS_ERR(abort_req))
1328 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1329 nvme_set_info(abort_cmd, abort_req, abort_completion);
1331 memset(&cmd, 0, sizeof(cmd));
1332 cmd.abort.opcode = nvme_admin_abort_cmd;
1333 cmd.abort.cid = req->tag;
1334 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1335 cmd.abort.command_id = abort_req->tag;
1338 cmd_rq->aborted = 1;
1340 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1342 nvme_submit_cmd(dev->queues[0], &cmd);
1345 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1347 struct nvme_queue *nvmeq = data;
1349 nvme_completion_fn fn;
1350 struct nvme_cmd_info *cmd;
1351 struct nvme_completion cqe;
1353 if (!blk_mq_request_started(req))
1356 cmd = blk_mq_rq_to_pdu(req);
1358 if (cmd->ctx == CMD_CTX_CANCELLED)
1361 if (blk_queue_dying(req->q))
1362 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1364 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1367 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1368 req->tag, nvmeq->qid);
1369 ctx = cancel_cmd_info(cmd, &fn);
1370 fn(nvmeq, ctx, &cqe);
1373 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1375 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1376 struct nvme_queue *nvmeq = cmd->nvmeq;
1378 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1380 spin_lock_irq(&nvmeq->q_lock);
1381 nvme_abort_req(req);
1382 spin_unlock_irq(&nvmeq->q_lock);
1385 * The aborted req will be completed on receiving the abort req.
1386 * We enable the timer again. If hit twice, it'll cause a device reset,
1387 * as the device then is in a faulty state.
1389 return BLK_EH_RESET_TIMER;
1392 static void nvme_free_queue(struct nvme_queue *nvmeq)
1394 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1395 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1397 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1398 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1402 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1406 for (i = dev->queue_count - 1; i >= lowest; i--) {
1407 struct nvme_queue *nvmeq = dev->queues[i];
1409 dev->queues[i] = NULL;
1410 nvme_free_queue(nvmeq);
1415 * nvme_suspend_queue - put queue into suspended state
1416 * @nvmeq - queue to suspend
1418 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1422 spin_lock_irq(&nvmeq->q_lock);
1423 if (nvmeq->cq_vector == -1) {
1424 spin_unlock_irq(&nvmeq->q_lock);
1427 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1428 nvmeq->dev->online_queues--;
1429 nvmeq->cq_vector = -1;
1430 spin_unlock_irq(&nvmeq->q_lock);
1432 if (!nvmeq->qid && nvmeq->dev->admin_q)
1433 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1435 irq_set_affinity_hint(vector, NULL);
1436 free_irq(vector, nvmeq);
1441 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1443 spin_lock_irq(&nvmeq->q_lock);
1444 if (nvmeq->tags && *nvmeq->tags)
1445 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1446 spin_unlock_irq(&nvmeq->q_lock);
1449 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1451 struct nvme_queue *nvmeq = dev->queues[qid];
1455 if (nvme_suspend_queue(nvmeq))
1458 /* Don't tell the adapter to delete the admin queue.
1459 * Don't tell a removed adapter to delete IO queues. */
1460 if (qid && readl(&dev->bar->csts) != -1) {
1461 adapter_delete_sq(dev, qid);
1462 adapter_delete_cq(dev, qid);
1465 spin_lock_irq(&nvmeq->q_lock);
1466 nvme_process_cq(nvmeq);
1467 spin_unlock_irq(&nvmeq->q_lock);
1470 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1473 int q_depth = dev->q_depth;
1474 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1476 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1477 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1478 mem_per_q = round_down(mem_per_q, dev->page_size);
1479 q_depth = div_u64(mem_per_q, entry_size);
1482 * Ensure the reduced q_depth is above some threshold where it
1483 * would be better to map queues in system memory with the
1493 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1496 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1497 unsigned offset = (qid - 1) *
1498 roundup(SQ_SIZE(depth), dev->page_size);
1499 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1500 nvmeq->sq_cmds_io = dev->cmb + offset;
1502 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1503 &nvmeq->sq_dma_addr, GFP_KERNEL);
1504 if (!nvmeq->sq_cmds)
1511 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1514 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1518 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1519 &nvmeq->cq_dma_addr, GFP_KERNEL);
1523 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1526 nvmeq->q_dmadev = dev->dev;
1528 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1529 dev->instance, qid);
1530 spin_lock_init(&nvmeq->q_lock);
1532 nvmeq->cq_phase = 1;
1533 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1534 nvmeq->q_depth = depth;
1536 nvmeq->cq_vector = -1;
1537 dev->queues[qid] = nvmeq;
1539 /* make sure queue descriptor is set before queue count, for kthread */
1546 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1547 nvmeq->cq_dma_addr);
1553 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1556 if (use_threaded_interrupts)
1557 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1558 nvme_irq_check, nvme_irq, IRQF_SHARED,
1560 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1561 IRQF_SHARED, name, nvmeq);
1564 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1566 struct nvme_dev *dev = nvmeq->dev;
1568 spin_lock_irq(&nvmeq->q_lock);
1571 nvmeq->cq_phase = 1;
1572 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1573 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1574 dev->online_queues++;
1575 spin_unlock_irq(&nvmeq->q_lock);
1578 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1580 struct nvme_dev *dev = nvmeq->dev;
1583 nvmeq->cq_vector = qid - 1;
1584 result = adapter_alloc_cq(dev, qid, nvmeq);
1588 result = adapter_alloc_sq(dev, qid, nvmeq);
1592 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1596 nvme_init_queue(nvmeq, qid);
1600 adapter_delete_sq(dev, qid);
1602 adapter_delete_cq(dev, qid);
1606 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1608 unsigned long timeout;
1609 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1611 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1613 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1615 if (fatal_signal_pending(current))
1617 if (time_after(jiffies, timeout)) {
1619 "Device not ready; aborting %s\n", enabled ?
1620 "initialisation" : "reset");
1629 * If the device has been passed off to us in an enabled state, just clear
1630 * the enabled bit. The spec says we should set the 'shutdown notification
1631 * bits', but doing so may cause the device to complete commands to the
1632 * admin queue ... and we don't know what memory that might be pointing at!
1634 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1636 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1637 dev->ctrl_config &= ~NVME_CC_ENABLE;
1638 writel(dev->ctrl_config, &dev->bar->cc);
1640 return nvme_wait_ready(dev, cap, false);
1643 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1645 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1646 dev->ctrl_config |= NVME_CC_ENABLE;
1647 writel(dev->ctrl_config, &dev->bar->cc);
1649 return nvme_wait_ready(dev, cap, true);
1652 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1654 unsigned long timeout;
1656 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1657 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1659 writel(dev->ctrl_config, &dev->bar->cc);
1661 timeout = SHUTDOWN_TIMEOUT + jiffies;
1662 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1663 NVME_CSTS_SHST_CMPLT) {
1665 if (fatal_signal_pending(current))
1667 if (time_after(jiffies, timeout)) {
1669 "Device shutdown incomplete; abort shutdown\n");
1677 static struct blk_mq_ops nvme_mq_admin_ops = {
1678 .queue_rq = nvme_queue_rq,
1679 .map_queue = blk_mq_map_queue,
1680 .init_hctx = nvme_admin_init_hctx,
1681 .exit_hctx = nvme_admin_exit_hctx,
1682 .init_request = nvme_admin_init_request,
1683 .timeout = nvme_timeout,
1686 static struct blk_mq_ops nvme_mq_ops = {
1687 .queue_rq = nvme_queue_rq,
1688 .map_queue = blk_mq_map_queue,
1689 .init_hctx = nvme_init_hctx,
1690 .init_request = nvme_init_request,
1691 .timeout = nvme_timeout,
1695 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1697 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1698 blk_cleanup_queue(dev->admin_q);
1699 blk_mq_free_tag_set(&dev->admin_tagset);
1703 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1705 if (!dev->admin_q) {
1706 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1707 dev->admin_tagset.nr_hw_queues = 1;
1708 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1709 dev->admin_tagset.reserved_tags = 1;
1710 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1711 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1712 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1713 dev->admin_tagset.driver_data = dev;
1715 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1718 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1719 if (IS_ERR(dev->admin_q)) {
1720 blk_mq_free_tag_set(&dev->admin_tagset);
1723 if (!blk_get_queue(dev->admin_q)) {
1724 nvme_dev_remove_admin(dev);
1725 dev->admin_q = NULL;
1729 blk_mq_unfreeze_queue(dev->admin_q);
1734 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1738 u64 cap = lo_hi_readq(&dev->bar->cap);
1739 struct nvme_queue *nvmeq;
1741 * default to a 4K page size, with the intention to update this
1742 * path in the future to accomodate architectures with differing
1743 * kernel and IO page sizes.
1745 unsigned page_shift = 12;
1746 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1748 if (page_shift < dev_page_min) {
1750 "Minimum device page size (%u) too large for "
1751 "host (%u)\n", 1 << dev_page_min,
1756 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1757 NVME_CAP_NSSRC(cap) : 0;
1759 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1760 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1762 result = nvme_disable_ctrl(dev, cap);
1766 nvmeq = dev->queues[0];
1768 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1773 aqa = nvmeq->q_depth - 1;
1776 dev->page_size = 1 << page_shift;
1778 dev->ctrl_config = NVME_CC_CSS_NVM;
1779 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1780 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1781 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1783 writel(aqa, &dev->bar->aqa);
1784 lo_hi_writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1785 lo_hi_writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1787 result = nvme_enable_ctrl(dev, cap);
1791 nvmeq->cq_vector = 0;
1792 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1794 nvmeq->cq_vector = -1;
1801 nvme_free_queues(dev, 0);
1805 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1807 struct nvme_dev *dev = ns->dev;
1808 struct nvme_user_io io;
1809 struct nvme_command c;
1810 unsigned length, meta_len;
1812 dma_addr_t meta_dma = 0;
1814 void __user *metadata;
1816 if (copy_from_user(&io, uio, sizeof(io)))
1819 switch (io.opcode) {
1820 case nvme_cmd_write:
1822 case nvme_cmd_compare:
1828 length = (io.nblocks + 1) << ns->lba_shift;
1829 meta_len = (io.nblocks + 1) * ns->ms;
1830 metadata = (void __user *)(uintptr_t)io.metadata;
1831 write = io.opcode & 1;
1838 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1841 meta = dma_alloc_coherent(dev->dev, meta_len,
1842 &meta_dma, GFP_KERNEL);
1849 if (copy_from_user(meta, metadata, meta_len)) {
1856 memset(&c, 0, sizeof(c));
1857 c.rw.opcode = io.opcode;
1858 c.rw.flags = io.flags;
1859 c.rw.nsid = cpu_to_le32(ns->ns_id);
1860 c.rw.slba = cpu_to_le64(io.slba);
1861 c.rw.length = cpu_to_le16(io.nblocks);
1862 c.rw.control = cpu_to_le16(io.control);
1863 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1864 c.rw.reftag = cpu_to_le32(io.reftag);
1865 c.rw.apptag = cpu_to_le16(io.apptag);
1866 c.rw.appmask = cpu_to_le16(io.appmask);
1867 c.rw.metadata = cpu_to_le64(meta_dma);
1869 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1870 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
1873 if (status == NVME_SC_SUCCESS && !write) {
1874 if (copy_to_user(metadata, meta, meta_len))
1877 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
1882 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1883 struct nvme_passthru_cmd __user *ucmd)
1885 struct nvme_passthru_cmd cmd;
1886 struct nvme_command c;
1887 unsigned timeout = 0;
1890 if (!capable(CAP_SYS_ADMIN))
1892 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1895 memset(&c, 0, sizeof(c));
1896 c.common.opcode = cmd.opcode;
1897 c.common.flags = cmd.flags;
1898 c.common.nsid = cpu_to_le32(cmd.nsid);
1899 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1900 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1901 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1902 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1903 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1904 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1905 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1906 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1909 timeout = msecs_to_jiffies(cmd.timeout_ms);
1911 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1912 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1913 &cmd.result, timeout);
1915 if (put_user(cmd.result, &ucmd->result))
1922 static int nvme_subsys_reset(struct nvme_dev *dev)
1924 if (!dev->subsystem)
1927 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1931 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1934 struct nvme_ns *ns = bdev->bd_disk->private_data;
1938 force_successful_syscall_return();
1940 case NVME_IOCTL_ADMIN_CMD:
1941 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1942 case NVME_IOCTL_IO_CMD:
1943 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1944 case NVME_IOCTL_SUBMIT_IO:
1945 return nvme_submit_io(ns, (void __user *)arg);
1946 case SG_GET_VERSION_NUM:
1947 return nvme_sg_get_version_num((void __user *)arg);
1949 return nvme_sg_io(ns, (void __user *)arg);
1955 #ifdef CONFIG_COMPAT
1956 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1957 unsigned int cmd, unsigned long arg)
1961 return -ENOIOCTLCMD;
1963 return nvme_ioctl(bdev, mode, cmd, arg);
1966 #define nvme_compat_ioctl NULL
1969 static void nvme_free_dev(struct kref *kref);
1970 static void nvme_free_ns(struct kref *kref)
1972 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1974 if (ns->type == NVME_NS_LIGHTNVM)
1975 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1977 spin_lock(&dev_list_lock);
1978 ns->disk->private_data = NULL;
1979 spin_unlock(&dev_list_lock);
1981 kref_put(&ns->dev->kref, nvme_free_dev);
1986 static int nvme_open(struct block_device *bdev, fmode_t mode)
1991 spin_lock(&dev_list_lock);
1992 ns = bdev->bd_disk->private_data;
1995 else if (!kref_get_unless_zero(&ns->kref))
1997 spin_unlock(&dev_list_lock);
2002 static void nvme_release(struct gendisk *disk, fmode_t mode)
2004 struct nvme_ns *ns = disk->private_data;
2005 kref_put(&ns->kref, nvme_free_ns);
2008 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
2010 /* some standard values */
2011 geo->heads = 1 << 6;
2012 geo->sectors = 1 << 5;
2013 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
2017 static void nvme_config_discard(struct nvme_ns *ns)
2019 u32 logical_block_size = queue_logical_block_size(ns->queue);
2020 ns->queue->limits.discard_zeroes_data = 0;
2021 ns->queue->limits.discard_alignment = logical_block_size;
2022 ns->queue->limits.discard_granularity = logical_block_size;
2023 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
2024 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2027 static int nvme_revalidate_disk(struct gendisk *disk)
2029 struct nvme_ns *ns = disk->private_data;
2030 struct nvme_dev *dev = ns->dev;
2031 struct nvme_id_ns *id;
2036 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
2037 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2038 dev->instance, ns->ns_id);
2041 if (id->ncap == 0) {
2046 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2047 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2049 "%s: LightNVM init failure\n", __func__);
2053 ns->type = NVME_NS_LIGHTNVM;
2057 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2058 ns->lba_shift = id->lbaf[lbaf].ds;
2059 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2060 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
2063 * If identify namespace failed, use default 512 byte block size so
2064 * block layer can use before failing read/write for 0 capacity.
2066 if (ns->lba_shift == 0)
2068 bs = 1 << ns->lba_shift;
2070 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2071 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2072 id->dps & NVME_NS_DPS_PI_MASK : 0;
2074 blk_mq_freeze_queue(disk->queue);
2075 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2077 bs != queue_logical_block_size(disk->queue) ||
2078 (ns->ms && ns->ext)))
2079 blk_integrity_unregister(disk);
2081 ns->pi_type = pi_type;
2082 blk_queue_logical_block_size(ns->queue, bs);
2084 if (ns->ms && !ns->ext)
2085 nvme_init_integrity(ns);
2087 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2088 !blk_get_integrity(disk)) ||
2089 ns->type == NVME_NS_LIGHTNVM)
2090 set_capacity(disk, 0);
2092 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2094 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2095 nvme_config_discard(ns);
2096 blk_mq_unfreeze_queue(disk->queue);
2102 static char nvme_pr_type(enum pr_type type)
2105 case PR_WRITE_EXCLUSIVE:
2107 case PR_EXCLUSIVE_ACCESS:
2109 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2111 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2113 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2115 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2122 static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2123 u64 key, u64 sa_key, u8 op)
2125 struct nvme_ns *ns = bdev->bd_disk->private_data;
2126 struct nvme_command c;
2127 u8 data[16] = { 0, };
2129 put_unaligned_le64(key, &data[0]);
2130 put_unaligned_le64(sa_key, &data[8]);
2132 memset(&c, 0, sizeof(c));
2133 c.common.opcode = op;
2134 c.common.nsid = cpu_to_le32(ns->ns_id);
2135 c.common.cdw10[0] = cpu_to_le32(cdw10);
2137 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2140 static int nvme_pr_register(struct block_device *bdev, u64 old,
2141 u64 new, unsigned flags)
2145 if (flags & ~PR_FL_IGNORE_KEY)
2148 cdw10 = old ? 2 : 0;
2149 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2150 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2151 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2154 static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2155 enum pr_type type, unsigned flags)
2159 if (flags & ~PR_FL_IGNORE_KEY)
2162 cdw10 = nvme_pr_type(type) << 8;
2163 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2164 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2167 static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2168 enum pr_type type, bool abort)
2170 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2171 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2174 static int nvme_pr_clear(struct block_device *bdev, u64 key)
2176 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
2177 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2180 static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2182 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2183 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2186 static const struct pr_ops nvme_pr_ops = {
2187 .pr_register = nvme_pr_register,
2188 .pr_reserve = nvme_pr_reserve,
2189 .pr_release = nvme_pr_release,
2190 .pr_preempt = nvme_pr_preempt,
2191 .pr_clear = nvme_pr_clear,
2194 static const struct block_device_operations nvme_fops = {
2195 .owner = THIS_MODULE,
2196 .ioctl = nvme_ioctl,
2197 .compat_ioctl = nvme_compat_ioctl,
2199 .release = nvme_release,
2200 .getgeo = nvme_getgeo,
2201 .revalidate_disk= nvme_revalidate_disk,
2202 .pr_ops = &nvme_pr_ops,
2205 static int nvme_kthread(void *data)
2207 struct nvme_dev *dev, *next;
2209 while (!kthread_should_stop()) {
2210 set_current_state(TASK_INTERRUPTIBLE);
2211 spin_lock(&dev_list_lock);
2212 list_for_each_entry_safe(dev, next, &dev_list, node) {
2214 u32 csts = readl(&dev->bar->csts);
2216 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2217 csts & NVME_CSTS_CFS) {
2218 if (!__nvme_reset(dev)) {
2220 "Failed status: %x, reset controller\n",
2221 readl(&dev->bar->csts));
2225 for (i = 0; i < dev->queue_count; i++) {
2226 struct nvme_queue *nvmeq = dev->queues[i];
2229 spin_lock_irq(&nvmeq->q_lock);
2230 nvme_process_cq(nvmeq);
2232 while ((i == 0) && (dev->event_limit > 0)) {
2233 if (nvme_submit_async_admin_req(dev))
2237 spin_unlock_irq(&nvmeq->q_lock);
2240 spin_unlock(&dev_list_lock);
2241 schedule_timeout(round_jiffies_relative(HZ));
2246 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2249 struct gendisk *disk;
2250 int node = dev_to_node(dev->dev);
2252 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2256 ns->queue = blk_mq_init_queue(&dev->tagset);
2257 if (IS_ERR(ns->queue))
2259 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2260 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2262 ns->queue->queuedata = ns;
2264 disk = alloc_disk_node(0, node);
2266 goto out_free_queue;
2268 kref_init(&ns->kref);
2271 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2272 list_add_tail(&ns->list, &dev->namespaces);
2274 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2275 if (dev->max_hw_sectors) {
2276 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2277 blk_queue_max_segments(ns->queue,
2278 (dev->max_hw_sectors / (dev->page_size >> 9)) + 1);
2280 if (dev->stripe_size)
2281 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2282 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2283 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2284 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
2286 disk->major = nvme_major;
2287 disk->first_minor = 0;
2288 disk->fops = &nvme_fops;
2289 disk->private_data = ns;
2290 disk->queue = ns->queue;
2291 disk->driverfs_dev = dev->device;
2292 disk->flags = GENHD_FL_EXT_DEVT;
2293 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2296 * Initialize capacity to 0 until we establish the namespace format and
2297 * setup integrity extentions if necessary. The revalidate_disk after
2298 * add_disk allows the driver to register with integrity if the format
2301 set_capacity(disk, 0);
2302 if (nvme_revalidate_disk(ns->disk))
2305 kref_get(&dev->kref);
2306 if (ns->type != NVME_NS_LIGHTNVM) {
2309 struct block_device *bd = bdget_disk(ns->disk, 0);
2312 if (blkdev_get(bd, FMODE_READ, NULL)) {
2316 blkdev_reread_part(bd);
2317 blkdev_put(bd, FMODE_READ);
2323 list_del(&ns->list);
2325 blk_cleanup_queue(ns->queue);
2331 * Create I/O queues. Failing to create an I/O queue is not an issue,
2332 * we can continue with less than the desired amount of queues, and
2333 * even a controller without I/O queues an still be used to issue
2334 * admin commands. This might be useful to upgrade a buggy firmware
2337 static void nvme_create_io_queues(struct nvme_dev *dev)
2341 for (i = dev->queue_count; i <= dev->max_qid; i++)
2342 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2345 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2346 if (nvme_create_queue(dev->queues[i], i)) {
2347 nvme_free_queues(dev, i);
2352 static int set_queue_count(struct nvme_dev *dev, int count)
2356 u32 q_count = (count - 1) | ((count - 1) << 16);
2358 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2363 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
2366 return min(result & 0xffff, result >> 16) + 1;
2369 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2371 u64 szu, size, offset;
2373 resource_size_t bar_size;
2374 struct pci_dev *pdev = to_pci_dev(dev->dev);
2376 dma_addr_t dma_addr;
2381 dev->cmbsz = readl(&dev->bar->cmbsz);
2382 if (!(NVME_CMB_SZ(dev->cmbsz)))
2385 cmbloc = readl(&dev->bar->cmbloc);
2387 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2388 size = szu * NVME_CMB_SZ(dev->cmbsz);
2389 offset = szu * NVME_CMB_OFST(cmbloc);
2390 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2392 if (offset > bar_size)
2396 * Controllers may support a CMB size larger than their BAR,
2397 * for example, due to being behind a bridge. Reduce the CMB to
2398 * the reported size of the BAR
2400 if (size > bar_size - offset)
2401 size = bar_size - offset;
2403 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2404 cmb = ioremap_wc(dma_addr, size);
2408 dev->cmb_dma_addr = dma_addr;
2409 dev->cmb_size = size;
2413 static inline void nvme_release_cmb(struct nvme_dev *dev)
2421 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2423 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2426 static int nvme_setup_io_queues(struct nvme_dev *dev)
2428 struct nvme_queue *adminq = dev->queues[0];
2429 struct pci_dev *pdev = to_pci_dev(dev->dev);
2430 int result, i, vecs, nr_io_queues, size;
2432 nr_io_queues = num_possible_cpus();
2433 result = set_queue_count(dev, nr_io_queues);
2436 if (result < nr_io_queues)
2437 nr_io_queues = result;
2439 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2440 result = nvme_cmb_qdepth(dev, nr_io_queues,
2441 sizeof(struct nvme_command));
2443 dev->q_depth = result;
2445 nvme_release_cmb(dev);
2448 size = db_bar_size(dev, nr_io_queues);
2452 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2455 if (!--nr_io_queues)
2457 size = db_bar_size(dev, nr_io_queues);
2459 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2460 adminq->q_db = dev->dbs;
2463 /* Deregister the admin queue's interrupt */
2464 free_irq(dev->entry[0].vector, adminq);
2467 * If we enable msix early due to not intx, disable it again before
2468 * setting up the full range we need.
2471 pci_disable_msix(pdev);
2473 for (i = 0; i < nr_io_queues; i++)
2474 dev->entry[i].entry = i;
2475 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2477 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2481 for (i = 0; i < vecs; i++)
2482 dev->entry[i].vector = i + pdev->irq;
2487 * Should investigate if there's a performance win from allocating
2488 * more queues than interrupt vectors; it might allow the submission
2489 * path to scale better, even if the receive path is limited by the
2490 * number of interrupts.
2492 nr_io_queues = vecs;
2493 dev->max_qid = nr_io_queues;
2495 result = queue_request_irq(dev, adminq, adminq->irqname);
2497 adminq->cq_vector = -1;
2501 /* Free previously allocated queues that are no longer usable */
2502 nvme_free_queues(dev, nr_io_queues + 1);
2503 nvme_create_io_queues(dev);
2508 nvme_free_queues(dev, 1);
2512 static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2514 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2515 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2517 return nsa->ns_id - nsb->ns_id;
2520 static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2524 list_for_each_entry(ns, &dev->namespaces, list) {
2525 if (ns->ns_id == nsid)
2527 if (ns->ns_id > nsid)
2533 static inline bool nvme_io_incapable(struct nvme_dev *dev)
2535 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2536 dev->online_queues < 2);
2539 static void nvme_ns_remove(struct nvme_ns *ns)
2541 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2544 blk_set_queue_dying(ns->queue);
2545 if (ns->disk->flags & GENHD_FL_UP)
2546 del_gendisk(ns->disk);
2547 if (kill || !blk_queue_dying(ns->queue)) {
2548 blk_mq_abort_requeue_list(ns->queue);
2549 blk_cleanup_queue(ns->queue);
2551 list_del_init(&ns->list);
2552 kref_put(&ns->kref, nvme_free_ns);
2555 static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2557 struct nvme_ns *ns, *next;
2560 for (i = 1; i <= nn; i++) {
2561 ns = nvme_find_ns(dev, i);
2563 if (revalidate_disk(ns->disk))
2566 nvme_alloc_ns(dev, i);
2568 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2572 list_sort(NULL, &dev->namespaces, ns_cmp);
2575 static void nvme_set_irq_hints(struct nvme_dev *dev)
2577 struct nvme_queue *nvmeq;
2580 for (i = 0; i < dev->online_queues; i++) {
2581 nvmeq = dev->queues[i];
2583 if (!nvmeq->tags || !(*nvmeq->tags))
2586 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2587 blk_mq_tags_cpumask(*nvmeq->tags));
2591 static void nvme_dev_scan(struct work_struct *work)
2593 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2594 struct nvme_id_ctrl *ctrl;
2596 if (!dev->tagset.tags)
2598 if (nvme_identify_ctrl(dev, &ctrl))
2600 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2602 nvme_set_irq_hints(dev);
2606 * Return: error value if an error occurred setting up the queues or calling
2607 * Identify Device. 0 if these succeeded, even if adding some of the
2608 * namespaces failed. At the moment, these failures are silent. TBD which
2609 * failures should be reported.
2611 static int nvme_dev_add(struct nvme_dev *dev)
2613 struct pci_dev *pdev = to_pci_dev(dev->dev);
2615 struct nvme_id_ctrl *ctrl;
2616 int shift = NVME_CAP_MPSMIN(lo_hi_readq(&dev->bar->cap)) + 12;
2618 res = nvme_identify_ctrl(dev, &ctrl);
2620 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2624 dev->oncs = le16_to_cpup(&ctrl->oncs);
2625 dev->abort_limit = ctrl->acl + 1;
2626 dev->vwc = ctrl->vwc;
2627 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2628 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2629 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2631 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2633 dev->max_hw_sectors = UINT_MAX;
2634 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2635 (pdev->device == 0x0953) && ctrl->vs[3]) {
2636 unsigned int max_hw_sectors;
2638 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2639 max_hw_sectors = dev->stripe_size >> (shift - 9);
2640 if (dev->max_hw_sectors) {
2641 dev->max_hw_sectors = min(max_hw_sectors,
2642 dev->max_hw_sectors);
2644 dev->max_hw_sectors = max_hw_sectors;
2648 if (!dev->tagset.tags) {
2649 dev->tagset.ops = &nvme_mq_ops;
2650 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2651 dev->tagset.timeout = NVME_IO_TIMEOUT;
2652 dev->tagset.numa_node = dev_to_node(dev->dev);
2653 dev->tagset.queue_depth =
2654 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2655 dev->tagset.cmd_size = nvme_cmd_size(dev);
2656 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2657 dev->tagset.driver_data = dev;
2659 if (blk_mq_alloc_tag_set(&dev->tagset))
2662 schedule_work(&dev->scan_work);
2666 static int nvme_dev_map(struct nvme_dev *dev)
2669 int bars, result = -ENOMEM;
2670 struct pci_dev *pdev = to_pci_dev(dev->dev);
2672 if (pci_enable_device_mem(pdev))
2675 dev->entry[0].vector = pdev->irq;
2676 pci_set_master(pdev);
2677 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2681 if (pci_request_selected_regions(pdev, bars, "nvme"))
2684 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2685 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2688 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2692 if (readl(&dev->bar->csts) == -1) {
2698 * Some devices don't advertse INTx interrupts, pre-enable a single
2699 * MSIX vec for setup. We'll adjust this later.
2702 result = pci_enable_msix(pdev, dev->entry, 1);
2707 cap = lo_hi_readq(&dev->bar->cap);
2708 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2709 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2710 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2713 * Temporary fix for the Apple controller found in the MacBook8,1 and
2714 * some MacBook7,1 to avoid controller resets and data loss.
2716 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2718 dev_warn(dev->dev, "detected Apple NVMe controller, set "
2719 "queue depth=%u to work around controller resets\n",
2723 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2724 dev->cmb = nvme_map_cmb(dev);
2732 pci_release_regions(pdev);
2734 pci_disable_device(pdev);
2738 static void nvme_dev_unmap(struct nvme_dev *dev)
2740 struct pci_dev *pdev = to_pci_dev(dev->dev);
2742 if (pdev->msi_enabled)
2743 pci_disable_msi(pdev);
2744 else if (pdev->msix_enabled)
2745 pci_disable_msix(pdev);
2750 pci_release_regions(pdev);
2753 if (pci_is_enabled(pdev))
2754 pci_disable_device(pdev);
2757 struct nvme_delq_ctx {
2758 struct task_struct *waiter;
2759 struct kthread_worker *worker;
2763 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2765 dq->waiter = current;
2769 set_current_state(TASK_KILLABLE);
2770 if (!atomic_read(&dq->refcount))
2772 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2773 fatal_signal_pending(current)) {
2775 * Disable the controller first since we can't trust it
2776 * at this point, but leave the admin queue enabled
2777 * until all queue deletion requests are flushed.
2778 * FIXME: This may take a while if there are more h/w
2779 * queues than admin tags.
2781 set_current_state(TASK_RUNNING);
2782 nvme_disable_ctrl(dev, lo_hi_readq(&dev->bar->cap));
2783 nvme_clear_queue(dev->queues[0]);
2784 flush_kthread_worker(dq->worker);
2785 nvme_disable_queue(dev, 0);
2789 set_current_state(TASK_RUNNING);
2792 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2794 atomic_dec(&dq->refcount);
2796 wake_up_process(dq->waiter);
2799 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2801 atomic_inc(&dq->refcount);
2805 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2807 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2810 spin_lock_irq(&nvmeq->q_lock);
2811 nvme_process_cq(nvmeq);
2812 spin_unlock_irq(&nvmeq->q_lock);
2815 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2816 kthread_work_func_t fn)
2818 struct nvme_command c;
2820 memset(&c, 0, sizeof(c));
2821 c.delete_queue.opcode = opcode;
2822 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2824 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2825 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2829 static void nvme_del_cq_work_handler(struct kthread_work *work)
2831 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2833 nvme_del_queue_end(nvmeq);
2836 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2838 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2839 nvme_del_cq_work_handler);
2842 static void nvme_del_sq_work_handler(struct kthread_work *work)
2844 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2846 int status = nvmeq->cmdinfo.status;
2849 status = nvme_delete_cq(nvmeq);
2851 nvme_del_queue_end(nvmeq);
2854 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2856 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2857 nvme_del_sq_work_handler);
2860 static void nvme_del_queue_start(struct kthread_work *work)
2862 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2864 if (nvme_delete_sq(nvmeq))
2865 nvme_del_queue_end(nvmeq);
2868 static void nvme_disable_io_queues(struct nvme_dev *dev)
2871 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2872 struct nvme_delq_ctx dq;
2873 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2874 &worker, "nvme%d", dev->instance);
2876 if (IS_ERR(kworker_task)) {
2878 "Failed to create queue del task\n");
2879 for (i = dev->queue_count - 1; i > 0; i--)
2880 nvme_disable_queue(dev, i);
2885 atomic_set(&dq.refcount, 0);
2886 dq.worker = &worker;
2887 for (i = dev->queue_count - 1; i > 0; i--) {
2888 struct nvme_queue *nvmeq = dev->queues[i];
2890 if (nvme_suspend_queue(nvmeq))
2892 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2893 nvmeq->cmdinfo.worker = dq.worker;
2894 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2895 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2897 nvme_wait_dq(&dq, dev);
2898 kthread_stop(kworker_task);
2902 * Remove the node from the device list and check
2903 * for whether or not we need to stop the nvme_thread.
2905 static void nvme_dev_list_remove(struct nvme_dev *dev)
2907 struct task_struct *tmp = NULL;
2909 spin_lock(&dev_list_lock);
2910 list_del_init(&dev->node);
2911 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2915 spin_unlock(&dev_list_lock);
2921 static void nvme_freeze_queues(struct nvme_dev *dev)
2925 list_for_each_entry(ns, &dev->namespaces, list) {
2926 blk_mq_freeze_queue_start(ns->queue);
2928 spin_lock_irq(ns->queue->queue_lock);
2929 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2930 spin_unlock_irq(ns->queue->queue_lock);
2932 blk_mq_cancel_requeue_work(ns->queue);
2933 blk_mq_stop_hw_queues(ns->queue);
2937 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2941 list_for_each_entry(ns, &dev->namespaces, list) {
2942 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2943 blk_mq_unfreeze_queue(ns->queue);
2944 blk_mq_start_stopped_hw_queues(ns->queue, true);
2945 blk_mq_kick_requeue_list(ns->queue);
2949 static void nvme_dev_shutdown(struct nvme_dev *dev)
2954 nvme_dev_list_remove(dev);
2957 nvme_freeze_queues(dev);
2958 csts = readl(&dev->bar->csts);
2960 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2961 for (i = dev->queue_count - 1; i >= 0; i--) {
2962 struct nvme_queue *nvmeq = dev->queues[i];
2963 nvme_suspend_queue(nvmeq);
2966 nvme_disable_io_queues(dev);
2967 nvme_shutdown_ctrl(dev);
2968 nvme_disable_queue(dev, 0);
2970 nvme_dev_unmap(dev);
2972 for (i = dev->queue_count - 1; i >= 0; i--)
2973 nvme_clear_queue(dev->queues[i]);
2976 static void nvme_dev_remove(struct nvme_dev *dev)
2978 struct nvme_ns *ns, *next;
2980 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2984 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2986 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2987 PAGE_SIZE, PAGE_SIZE, 0);
2988 if (!dev->prp_page_pool)
2991 /* Optimisation for I/Os between 4k and 128k */
2992 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2994 if (!dev->prp_small_pool) {
2995 dma_pool_destroy(dev->prp_page_pool);
3001 static void nvme_release_prp_pools(struct nvme_dev *dev)
3003 dma_pool_destroy(dev->prp_page_pool);
3004 dma_pool_destroy(dev->prp_small_pool);
3007 static DEFINE_IDA(nvme_instance_ida);
3009 static int nvme_set_instance(struct nvme_dev *dev)
3011 int instance, error;
3014 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
3017 spin_lock(&dev_list_lock);
3018 error = ida_get_new(&nvme_instance_ida, &instance);
3019 spin_unlock(&dev_list_lock);
3020 } while (error == -EAGAIN);
3025 dev->instance = instance;
3029 static void nvme_release_instance(struct nvme_dev *dev)
3031 spin_lock(&dev_list_lock);
3032 ida_remove(&nvme_instance_ida, dev->instance);
3033 spin_unlock(&dev_list_lock);
3036 static void nvme_free_dev(struct kref *kref)
3038 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
3040 put_device(dev->dev);
3041 put_device(dev->device);
3042 nvme_release_instance(dev);
3043 if (dev->tagset.tags)
3044 blk_mq_free_tag_set(&dev->tagset);
3046 blk_put_queue(dev->admin_q);
3052 static int nvme_dev_open(struct inode *inode, struct file *f)
3054 struct nvme_dev *dev;
3055 int instance = iminor(inode);
3058 spin_lock(&dev_list_lock);
3059 list_for_each_entry(dev, &dev_list, node) {
3060 if (dev->instance == instance) {
3061 if (!dev->admin_q) {
3065 if (!kref_get_unless_zero(&dev->kref))
3067 f->private_data = dev;
3072 spin_unlock(&dev_list_lock);
3077 static int nvme_dev_release(struct inode *inode, struct file *f)
3079 struct nvme_dev *dev = f->private_data;
3080 kref_put(&dev->kref, nvme_free_dev);
3084 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3086 struct nvme_dev *dev = f->private_data;
3090 case NVME_IOCTL_ADMIN_CMD:
3091 return nvme_user_cmd(dev, NULL, (void __user *)arg);
3092 case NVME_IOCTL_IO_CMD:
3093 if (list_empty(&dev->namespaces))
3095 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3096 return nvme_user_cmd(dev, ns, (void __user *)arg);
3097 case NVME_IOCTL_RESET:
3098 dev_warn(dev->dev, "resetting controller\n");
3099 return nvme_reset(dev);
3100 case NVME_IOCTL_SUBSYS_RESET:
3101 return nvme_subsys_reset(dev);
3107 static const struct file_operations nvme_dev_fops = {
3108 .owner = THIS_MODULE,
3109 .open = nvme_dev_open,
3110 .release = nvme_dev_release,
3111 .unlocked_ioctl = nvme_dev_ioctl,
3112 .compat_ioctl = nvme_dev_ioctl,
3115 static void nvme_probe_work(struct work_struct *work)
3117 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3118 bool start_thread = false;
3121 result = nvme_dev_map(dev);
3125 result = nvme_configure_admin_queue(dev);
3129 spin_lock(&dev_list_lock);
3130 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3131 start_thread = true;
3134 list_add(&dev->node, &dev_list);
3135 spin_unlock(&dev_list_lock);
3138 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
3139 wake_up_all(&nvme_kthread_wait);
3141 wait_event_killable(nvme_kthread_wait, nvme_thread);
3143 if (IS_ERR_OR_NULL(nvme_thread)) {
3144 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3148 nvme_init_queue(dev->queues[0], 0);
3149 result = nvme_alloc_admin_tags(dev);
3153 result = nvme_setup_io_queues(dev);
3157 dev->event_limit = 1;
3160 * Keep the controller around but remove all namespaces if we don't have
3161 * any working I/O queue.
3163 if (dev->online_queues < 2) {
3164 dev_warn(dev->dev, "IO queues not created\n");
3165 nvme_dev_remove(dev);
3167 nvme_unfreeze_queues(dev);
3174 nvme_dev_remove_admin(dev);
3175 blk_put_queue(dev->admin_q);
3176 dev->admin_q = NULL;
3177 dev->queues[0]->tags = NULL;
3179 nvme_disable_queue(dev, 0);
3180 nvme_dev_list_remove(dev);
3182 nvme_dev_unmap(dev);
3184 if (!work_busy(&dev->reset_work))
3185 nvme_dead_ctrl(dev);
3188 static int nvme_remove_dead_ctrl(void *arg)
3190 struct nvme_dev *dev = (struct nvme_dev *)arg;
3191 struct pci_dev *pdev = to_pci_dev(dev->dev);
3193 if (pci_get_drvdata(pdev))
3194 pci_stop_and_remove_bus_device_locked(pdev);
3195 kref_put(&dev->kref, nvme_free_dev);
3199 static void nvme_dead_ctrl(struct nvme_dev *dev)
3201 dev_warn(dev->dev, "Device failed to resume\n");
3202 kref_get(&dev->kref);
3203 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3206 "Failed to start controller remove task\n");
3207 kref_put(&dev->kref, nvme_free_dev);
3211 static void nvme_reset_work(struct work_struct *ws)
3213 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
3214 bool in_probe = work_busy(&dev->probe_work);
3216 nvme_dev_shutdown(dev);
3218 /* Synchronize with device probe so that work will see failure status
3219 * and exit gracefully without trying to schedule another reset */
3220 flush_work(&dev->probe_work);
3222 /* Fail this device if reset occured during probe to avoid
3223 * infinite initialization loops. */
3225 nvme_dead_ctrl(dev);
3228 /* Schedule device resume asynchronously so the reset work is available
3229 * to cleanup errors that may occur during reinitialization */
3230 schedule_work(&dev->probe_work);
3233 static int __nvme_reset(struct nvme_dev *dev)
3235 if (work_pending(&dev->reset_work))
3237 list_del_init(&dev->node);
3238 queue_work(nvme_workq, &dev->reset_work);
3242 static int nvme_reset(struct nvme_dev *dev)
3246 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3249 spin_lock(&dev_list_lock);
3250 ret = __nvme_reset(dev);
3251 spin_unlock(&dev_list_lock);
3254 flush_work(&dev->reset_work);
3255 flush_work(&dev->probe_work);
3262 static ssize_t nvme_sysfs_reset(struct device *dev,
3263 struct device_attribute *attr, const char *buf,
3266 struct nvme_dev *ndev = dev_get_drvdata(dev);
3269 ret = nvme_reset(ndev);
3275 static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3277 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3279 int node, result = -ENOMEM;
3280 struct nvme_dev *dev;
3282 node = dev_to_node(&pdev->dev);
3283 if (node == NUMA_NO_NODE)
3284 set_dev_node(&pdev->dev, 0);
3286 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3289 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3293 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3298 INIT_LIST_HEAD(&dev->namespaces);
3299 INIT_WORK(&dev->reset_work, nvme_reset_work);
3300 dev->dev = get_device(&pdev->dev);
3301 pci_set_drvdata(pdev, dev);
3302 result = nvme_set_instance(dev);
3306 result = nvme_setup_prp_pools(dev);
3310 kref_init(&dev->kref);
3311 dev->device = device_create(nvme_class, &pdev->dev,
3312 MKDEV(nvme_char_major, dev->instance),
3313 dev, "nvme%d", dev->instance);
3314 if (IS_ERR(dev->device)) {
3315 result = PTR_ERR(dev->device);
3318 get_device(dev->device);
3319 dev_set_drvdata(dev->device, dev);
3321 result = device_create_file(dev->device, &dev_attr_reset_controller);
3325 INIT_LIST_HEAD(&dev->node);
3326 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3327 INIT_WORK(&dev->probe_work, nvme_probe_work);
3328 schedule_work(&dev->probe_work);
3332 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3333 put_device(dev->device);
3335 nvme_release_prp_pools(dev);
3337 nvme_release_instance(dev);
3339 put_device(dev->dev);
3347 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3349 struct nvme_dev *dev = pci_get_drvdata(pdev);
3352 nvme_dev_shutdown(dev);
3354 schedule_work(&dev->probe_work);
3357 static void nvme_shutdown(struct pci_dev *pdev)
3359 struct nvme_dev *dev = pci_get_drvdata(pdev);
3360 nvme_dev_shutdown(dev);
3363 static void nvme_remove(struct pci_dev *pdev)
3365 struct nvme_dev *dev = pci_get_drvdata(pdev);
3367 spin_lock(&dev_list_lock);
3368 list_del_init(&dev->node);
3369 spin_unlock(&dev_list_lock);
3371 pci_set_drvdata(pdev, NULL);
3372 flush_work(&dev->probe_work);
3373 flush_work(&dev->reset_work);
3374 flush_work(&dev->scan_work);
3375 device_remove_file(dev->device, &dev_attr_reset_controller);
3376 nvme_dev_remove(dev);
3377 nvme_dev_shutdown(dev);
3378 nvme_dev_remove_admin(dev);
3379 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3380 nvme_free_queues(dev, 0);
3381 nvme_release_cmb(dev);
3382 nvme_release_prp_pools(dev);
3383 kref_put(&dev->kref, nvme_free_dev);
3386 /* These functions are yet to be implemented */
3387 #define nvme_error_detected NULL
3388 #define nvme_dump_registers NULL
3389 #define nvme_link_reset NULL
3390 #define nvme_slot_reset NULL
3391 #define nvme_error_resume NULL
3393 #ifdef CONFIG_PM_SLEEP
3394 static int nvme_suspend(struct device *dev)
3396 struct pci_dev *pdev = to_pci_dev(dev);
3397 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3399 nvme_dev_shutdown(ndev);
3403 static int nvme_resume(struct device *dev)
3405 struct pci_dev *pdev = to_pci_dev(dev);
3406 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3408 schedule_work(&ndev->probe_work);
3413 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3415 static const struct pci_error_handlers nvme_err_handler = {
3416 .error_detected = nvme_error_detected,
3417 .mmio_enabled = nvme_dump_registers,
3418 .link_reset = nvme_link_reset,
3419 .slot_reset = nvme_slot_reset,
3420 .resume = nvme_error_resume,
3421 .reset_notify = nvme_reset_notify,
3424 /* Move to pci_ids.h later */
3425 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
3427 static const struct pci_device_id nvme_id_table[] = {
3428 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3429 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
3432 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3434 static struct pci_driver nvme_driver = {
3436 .id_table = nvme_id_table,
3437 .probe = nvme_probe,
3438 .remove = nvme_remove,
3439 .shutdown = nvme_shutdown,
3441 .pm = &nvme_dev_pm_ops,
3443 .err_handler = &nvme_err_handler,
3446 static int __init nvme_init(void)
3450 init_waitqueue_head(&nvme_kthread_wait);
3452 nvme_workq = create_singlethread_workqueue("nvme");
3456 result = register_blkdev(nvme_major, "nvme");
3459 else if (result > 0)
3460 nvme_major = result;
3462 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3465 goto unregister_blkdev;
3466 else if (result > 0)
3467 nvme_char_major = result;
3469 nvme_class = class_create(THIS_MODULE, "nvme");
3470 if (IS_ERR(nvme_class)) {
3471 result = PTR_ERR(nvme_class);
3472 goto unregister_chrdev;
3475 result = pci_register_driver(&nvme_driver);
3481 class_destroy(nvme_class);
3483 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3485 unregister_blkdev(nvme_major, "nvme");
3487 destroy_workqueue(nvme_workq);
3491 static void __exit nvme_exit(void)
3493 pci_unregister_driver(&nvme_driver);
3494 unregister_blkdev(nvme_major, "nvme");
3495 destroy_workqueue(nvme_workq);
3496 class_destroy(nvme_class);
3497 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3498 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3502 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3503 MODULE_LICENSE("GPL");
3504 MODULE_VERSION("1.0");
3505 module_init(nvme_init);
3506 module_exit(nvme_exit);