drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/idr.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kdev_t.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/timer.h>
  43 #include <linux/types.h>
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45 #include <asm/unaligned.h>
  46
  47 #include "nvme.h"
  48
  49 #define NVME_Q_DEPTH            1024
  50 #define NVME_AQ_DEPTH           256
  51 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  52 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  53
  54 /*
  55  * We handle AEN commands ourselves and don't even let the
  56  * block layer know about them.
  57  */
  58 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  59
  60 static int use_threaded_interrupts;
  61 module_param(use_threaded_interrupts, int, 0);
  62
  63 static bool use_cmb_sqes = true;
  64 module_param(use_cmb_sqes, bool, 0644);
  65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  66
  67 static struct workqueue_struct *nvme_workq;
  68
  69 struct nvme_dev;
  70 struct nvme_queue;
  71
  72 static int nvme_reset(struct nvme_dev *dev);
  73 static void nvme_process_cq(struct nvme_queue *nvmeq);
  74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  75
  76 /*
  77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  78  */
  79 struct nvme_dev {
  80         struct nvme_queue **queues;
  81         struct blk_mq_tag_set tagset;
  82         struct blk_mq_tag_set admin_tagset;
  83         u32 __iomem *dbs;
  84         struct device *dev;
  85         struct dma_pool *prp_page_pool;
  86         struct dma_pool *prp_small_pool;
  87         unsigned queue_count;
  88         unsigned online_queues;
  89         unsigned max_qid;
  90         int q_depth;
  91         u32 db_stride;
  92         void __iomem *bar;
  93         struct work_struct reset_work;
  94         struct work_struct remove_work;
  95         struct timer_list watchdog_timer;
  96         struct mutex shutdown_lock;
  97         bool subsystem;
  98         void __iomem *cmb;
  99         dma_addr_t cmb_dma_addr;
 100         u64 cmb_size;
 101         u32 cmbsz;
 102         u32 cmbloc;
 103         struct nvme_ctrl ctrl;
 104         struct completion ioq_wait;
 105 };
 106
 107 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 108 {
 109         return container_of(ctrl, struct nvme_dev, ctrl);
 110 }
 111
 112 /*
 113  * An NVM Express queue.  Each device has at least two (one for admin
 114  * commands and one for I/O commands).
 115  */
 116 struct nvme_queue {
 117         struct device *q_dmadev;
 118         struct nvme_dev *dev;
 119         char irqname[24];       /* nvme4294967295-65535\0 */
 120         spinlock_t q_lock;
 121         struct nvme_command *sq_cmds;
 122         struct nvme_command __iomem *sq_cmds_io;
 123         volatile struct nvme_completion *cqes;
 124         struct blk_mq_tags **tags;
 125         dma_addr_t sq_dma_addr;
 126         dma_addr_t cq_dma_addr;
 127         u32 __iomem *q_db;
 128         u16 q_depth;
 129         s16 cq_vector;
 130         u16 sq_tail;
 131         u16 cq_head;
 132         u16 qid;
 133         u8 cq_phase;
 134         u8 cqe_seen;
 135 };
 136
 137 /*
 138  * The nvme_iod describes the data in an I/O, including the list of PRP
 139  * entries.  You can't see it in this data structure because C doesn't let
 140  * me express that.  Use nvme_init_iod to ensure there's enough space
 141  * allocated to store the PRP list.
 142  */
 143 struct nvme_iod {
 144         struct nvme_request req;
 145         struct nvme_queue *nvmeq;
 146         int aborted;
 147         int npages;             /* In the PRP list. 0 means small pool in use */
 148         int nents;              /* Used in scatterlist */
 149         int length;             /* Of data, in bytes */
 150         dma_addr_t first_dma;
 151         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 152         struct scatterlist *sg;
 153         struct scatterlist inline_sg[0];
 154 };
 155
 156 /*
 157  * Check we didin't inadvertently grow the command struct
 158  */
 159 static inline void _nvme_check_size(void)
 160 {
 161         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 162         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 172         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 173 }
 174
 175 /*
 176  * Max size of iod being embedded in the request payload
 177  */
 178 #define NVME_INT_PAGES          2
 179 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 180
 181 /*
 182  * Will slightly overestimate the number of pages needed.  This is OK
 183  * as it only leads to a small amount of wasted memory for the lifetime of
 184  * the I/O.
 185  */
 186 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 187 {
 188         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 189                                       dev->ctrl.page_size);
 190         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 191 }
 192
 193 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 194                 unsigned int size, unsigned int nseg)
 195 {
 196         return sizeof(__le64 *) * nvme_npages(size, dev) +
 197                         sizeof(struct scatterlist) * nseg;
 198 }
 199
 200 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 201 {
 202         return sizeof(struct nvme_iod) +
 203                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 204 }
 205
 206 static int nvmeq_irq(struct nvme_queue *nvmeq)
 207 {
 208         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 209 }
 210
 211 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 212                                 unsigned int hctx_idx)
 213 {
 214         struct nvme_dev *dev = data;
 215         struct nvme_queue *nvmeq = dev->queues[0];
 216
 217         WARN_ON(hctx_idx != 0);
 218         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 219         WARN_ON(nvmeq->tags);
 220
 221         hctx->driver_data = nvmeq;
 222         nvmeq->tags = &dev->admin_tagset.tags[0];
 223         return 0;
 224 }
 225
 226 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 227 {
 228         struct nvme_queue *nvmeq = hctx->driver_data;
 229
 230         nvmeq->tags = NULL;
 231 }
 232
 233 static int nvme_admin_init_request(void *data, struct request *req,
 234                                 unsigned int hctx_idx, unsigned int rq_idx,
 235                                 unsigned int numa_node)
 236 {
 237         struct nvme_dev *dev = data;
 238         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 239         struct nvme_queue *nvmeq = dev->queues[0];
 240
 241         BUG_ON(!nvmeq);
 242         iod->nvmeq = nvmeq;
 243         return 0;
 244 }
 245
 246 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 247                           unsigned int hctx_idx)
 248 {
 249         struct nvme_dev *dev = data;
 250         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 251
 252         if (!nvmeq->tags)
 253                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 254
 255         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 256         hctx->driver_data = nvmeq;
 257         return 0;
 258 }
 259
 260 static int nvme_init_request(void *data, struct request *req,
 261                                 unsigned int hctx_idx, unsigned int rq_idx,
 262                                 unsigned int numa_node)
 263 {
 264         struct nvme_dev *dev = data;
 265         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 266         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 267
 268         BUG_ON(!nvmeq);
 269         iod->nvmeq = nvmeq;
 270         return 0;
 271 }
 272
 273 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 274 {
 275         struct nvme_dev *dev = set->driver_data;
 276
 277         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 278 }
 279
 280 /**
 281  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 282  * @nvmeq: The queue to use
 283  * @cmd: The command to send
 284  *
 285  * Safe to use from interrupt context
 286  */
 287 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 288                                                 struct nvme_command *cmd)
 289 {
 290         u16 tail = nvmeq->sq_tail;
 291
 292         if (nvmeq->sq_cmds_io)
 293                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 294         else
 295                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 296
 297         if (++tail == nvmeq->q_depth)
 298                 tail = 0;
 299         writel(tail, nvmeq->q_db);
 300         nvmeq->sq_tail = tail;
 301 }
 302
 303 static __le64 **iod_list(struct request *req)
 304 {
 305         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 306         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 307 }
 308
 309 static int nvme_init_iod(struct request *rq, unsigned size,
 310                 struct nvme_dev *dev)
 311 {
 312         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 313         int nseg = blk_rq_nr_phys_segments(rq);
 314
 315         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 316                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 317                 if (!iod->sg)
 318                         return BLK_MQ_RQ_QUEUE_BUSY;
 319         } else {
 320                 iod->sg = iod->inline_sg;
 321         }
 322
 323         iod->aborted = 0;
 324         iod->npages = -1;
 325         iod->nents = 0;
 326         iod->length = size;
 327
 328         if (!(rq->rq_flags & RQF_DONTPREP)) {
 329                 rq->retries = 0;
 330                 rq->rq_flags |= RQF_DONTPREP;
 331         }
 332         return BLK_MQ_RQ_QUEUE_OK;
 333 }
 334
 335 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 336 {
 337         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 338         const int last_prp = dev->ctrl.page_size / 8 - 1;
 339         int i;
 340         __le64 **list = iod_list(req);
 341         dma_addr_t prp_dma = iod->first_dma;
 342
 343         if (iod->npages == 0)
 344                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 345         for (i = 0; i < iod->npages; i++) {
 346                 __le64 *prp_list = list[i];
 347                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 348                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 349                 prp_dma = next_prp_dma;
 350         }
 351
 352         if (iod->sg != iod->inline_sg)
 353                 kfree(iod->sg);
 354 }
 355
 356 #ifdef CONFIG_BLK_DEV_INTEGRITY
 357 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 358 {
 359         if (be32_to_cpu(pi->ref_tag) == v)
 360                 pi->ref_tag = cpu_to_be32(p);
 361 }
 362
 363 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 364 {
 365         if (be32_to_cpu(pi->ref_tag) == p)
 366                 pi->ref_tag = cpu_to_be32(v);
 367 }
 368
 369 /**
 370  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 371  *
 372  * The virtual start sector is the one that was originally submitted by the
 373  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 374  * start sector may be different. Remap protection information to match the
 375  * physical LBA on writes, and back to the original seed on reads.
 376  *
 377  * Type 0 and 3 do not have a ref tag, so no remapping required.
 378  */
 379 static void nvme_dif_remap(struct request *req,
 380                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 381 {
 382         struct nvme_ns *ns = req->rq_disk->private_data;
 383         struct bio_integrity_payload *bip;
 384         struct t10_pi_tuple *pi;
 385         void *p, *pmap;
 386         u32 i, nlb, ts, phys, virt;
 387
 388         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 389                 return;
 390
 391         bip = bio_integrity(req->bio);
 392         if (!bip)
 393                 return;
 394
 395         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 396
 397         p = pmap;
 398         virt = bip_get_seed(bip);
 399         phys = nvme_block_nr(ns, blk_rq_pos(req));
 400         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 401         ts = ns->disk->queue->integrity.tuple_size;
 402
 403         for (i = 0; i < nlb; i++, virt++, phys++) {
 404                 pi = (struct t10_pi_tuple *)p;
 405                 dif_swap(phys, virt, pi);
 406                 p += ts;
 407         }
 408         kunmap_atomic(pmap);
 409 }
 410 #else /* CONFIG_BLK_DEV_INTEGRITY */
 411 static void nvme_dif_remap(struct request *req,
 412                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 413 {
 414 }
 415 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 416 {
 417 }
 418 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 419 {
 420 }
 421 #endif
 422
 423 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 424                 int total_len)
 425 {
 426         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 427         struct dma_pool *pool;
 428         int length = total_len;
 429         struct scatterlist *sg = iod->sg;
 430         int dma_len = sg_dma_len(sg);
 431         u64 dma_addr = sg_dma_address(sg);
 432         u32 page_size = dev->ctrl.page_size;
 433         int offset = dma_addr & (page_size - 1);
 434         __le64 *prp_list;
 435         __le64 **list = iod_list(req);
 436         dma_addr_t prp_dma;
 437         int nprps, i;
 438
 439         length -= (page_size - offset);
 440         if (length <= 0)
 441                 return true;
 442
 443         dma_len -= (page_size - offset);
 444         if (dma_len) {
 445                 dma_addr += (page_size - offset);
 446         } else {
 447                 sg = sg_next(sg);
 448                 dma_addr = sg_dma_address(sg);
 449                 dma_len = sg_dma_len(sg);
 450         }
 451
 452         if (length <= page_size) {
 453                 iod->first_dma = dma_addr;
 454                 return true;
 455         }
 456
 457         nprps = DIV_ROUND_UP(length, page_size);
 458         if (nprps <= (256 / 8)) {
 459                 pool = dev->prp_small_pool;
 460                 iod->npages = 0;
 461         } else {
 462                 pool = dev->prp_page_pool;
 463                 iod->npages = 1;
 464         }
 465
 466         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 467         if (!prp_list) {
 468                 iod->first_dma = dma_addr;
 469                 iod->npages = -1;
 470                 return false;
 471         }
 472         list[0] = prp_list;
 473         iod->first_dma = prp_dma;
 474         i = 0;
 475         for (;;) {
 476                 if (i == page_size >> 3) {
 477                         __le64 *old_prp_list = prp_list;
 478                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 479                         if (!prp_list)
 480                                 return false;
 481                         list[iod->npages++] = prp_list;
 482                         prp_list[0] = old_prp_list[i - 1];
 483                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 484                         i = 1;
 485                 }
 486                 prp_list[i++] = cpu_to_le64(dma_addr);
 487                 dma_len -= page_size;
 488                 dma_addr += page_size;
 489                 length -= page_size;
 490                 if (length <= 0)
 491                         break;
 492                 if (dma_len > 0)
 493                         continue;
 494                 BUG_ON(dma_len < 0);
 495                 sg = sg_next(sg);
 496                 dma_addr = sg_dma_address(sg);
 497                 dma_len = sg_dma_len(sg);
 498         }
 499
 500         return true;
 501 }
 502
 503 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 504                 unsigned size, struct nvme_command *cmnd)
 505 {
 506         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 507         struct request_queue *q = req->q;
 508         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 509                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 510         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 511
 512         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 513         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 514         if (!iod->nents)
 515                 goto out;
 516
 517         ret = BLK_MQ_RQ_QUEUE_BUSY;
 518         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 519                                 DMA_ATTR_NO_WARN))
 520                 goto out;
 521
 522         if (!nvme_setup_prps(dev, req, size))
 523                 goto out_unmap;
 524
 525         ret = BLK_MQ_RQ_QUEUE_ERROR;
 526         if (blk_integrity_rq(req)) {
 527                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 528                         goto out_unmap;
 529
 530                 sg_init_table(&iod->meta_sg, 1);
 531                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 532                         goto out_unmap;
 533
 534                 if (rq_data_dir(req))
 535                         nvme_dif_remap(req, nvme_dif_prep);
 536
 537                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 538                         goto out_unmap;
 539         }
 540
 541         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 542         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 543         if (blk_integrity_rq(req))
 544                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 545         return BLK_MQ_RQ_QUEUE_OK;
 546
 547 out_unmap:
 548         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 549 out:
 550         return ret;
 551 }
 552
 553 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 554 {
 555         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 556         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 557                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 558
 559         if (iod->nents) {
 560                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 561                 if (blk_integrity_rq(req)) {
 562                         if (!rq_data_dir(req))
 563                                 nvme_dif_remap(req, nvme_dif_complete);
 564                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 565                 }
 566         }
 567
 568         nvme_cleanup_cmd(req);
 569         nvme_free_iod(dev, req);
 570 }
 571
 572 /*
 573  * NOTE: ns is NULL when called on the admin queue.
 574  */
 575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 576                          const struct blk_mq_queue_data *bd)
 577 {
 578         struct nvme_ns *ns = hctx->queue->queuedata;
 579         struct nvme_queue *nvmeq = hctx->driver_data;
 580         struct nvme_dev *dev = nvmeq->dev;
 581         struct request *req = bd->rq;
 582         struct nvme_command cmnd;
 583         unsigned map_len;
 584         int ret = BLK_MQ_RQ_QUEUE_OK;
 585
 586         /*
 587          * If formated with metadata, require the block layer provide a buffer
 588          * unless this namespace is formated such that the metadata can be
 589          * stripped/generated by the controller with PRACT=1.
 590          */
 591         if (ns && ns->ms && !blk_integrity_rq(req)) {
 592                 if (!(ns->pi_type && ns->ms == 8) &&
 593                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 594                         blk_mq_end_request(req, -EFAULT);
 595                         return BLK_MQ_RQ_QUEUE_OK;
 596                 }
 597         }
 598
 599         ret = nvme_setup_cmd(ns, req, &cmnd);
 600         if (ret != BLK_MQ_RQ_QUEUE_OK)
 601                 return ret;
 602
 603         map_len = nvme_map_len(req);
 604         ret = nvme_init_iod(req, map_len, dev);
 605         if (ret != BLK_MQ_RQ_QUEUE_OK)
 606                 goto out_free_cmd;
 607
 608         if (blk_rq_nr_phys_segments(req))
 609                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 610
 611         if (ret != BLK_MQ_RQ_QUEUE_OK)
 612                 goto out_cleanup_iod;
 613
 614         blk_mq_start_request(req);
 615
 616         spin_lock_irq(&nvmeq->q_lock);
 617         if (unlikely(nvmeq->cq_vector < 0)) {
 618                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 619                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 620                 else
 621                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 622                 spin_unlock_irq(&nvmeq->q_lock);
 623                 goto out_cleanup_iod;
 624         }
 625         __nvme_submit_cmd(nvmeq, &cmnd);
 626         nvme_process_cq(nvmeq);
 627         spin_unlock_irq(&nvmeq->q_lock);
 628         return BLK_MQ_RQ_QUEUE_OK;
 629 out_cleanup_iod:
 630         nvme_free_iod(dev, req);
 631 out_free_cmd:
 632         nvme_cleanup_cmd(req);
 633         return ret;
 634 }
 635
 636 static void nvme_complete_rq(struct request *req)
 637 {
 638         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 639         struct nvme_dev *dev = iod->nvmeq->dev;
 640         int error = 0;
 641
 642         nvme_unmap_data(dev, req);
 643
 644         if (unlikely(req->errors)) {
 645                 if (nvme_req_needs_retry(req, req->errors)) {
 646                         req->retries++;
 647                         nvme_requeue_req(req);
 648                         return;
 649                 }
 650
 651                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 652                         error = req->errors;
 653                 else
 654                         error = nvme_error_status(req->errors);
 655         }
 656
 657         if (unlikely(iod->aborted)) {
 658                 dev_warn(dev->ctrl.device,
 659                         "completing aborted command with status: %04x\n",
 660                         req->errors);
 661         }
 662
 663         blk_mq_end_request(req, error);
 664 }
 665
 666 /* We read the CQE phase first to check if the rest of the entry is valid */
 667 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 668                 u16 phase)
 669 {
 670         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 671 }
 672
 673 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 674 {
 675         u16 head, phase;
 676
 677         head = nvmeq->cq_head;
 678         phase = nvmeq->cq_phase;
 679
 680         while (nvme_cqe_valid(nvmeq, head, phase)) {
 681                 struct nvme_completion cqe = nvmeq->cqes[head];
 682                 struct request *req;
 683
 684                 if (++head == nvmeq->q_depth) {
 685                         head = 0;
 686                         phase = !phase;
 687                 }
 688
 689                 if (tag && *tag == cqe.command_id)
 690                         *tag = -1;
 691
 692                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 693                         dev_warn(nvmeq->dev->ctrl.device,
 694                                 "invalid id %d completed on queue %d\n",
 695                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 696                         continue;
 697                 }
 698
 699                 /*
 700                  * AEN requests are special as they don't time out and can
 701                  * survive any kind of queue freeze and often don't respond to
 702                  * aborts.  We don't even bother to allocate a struct request
 703                  * for them but rather special case them here.
 704                  */
 705                 if (unlikely(nvmeq->qid == 0 &&
 706                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 707                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 708                                         cqe.status, &cqe.result);
 709                         continue;
 710                 }
 711
 712                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 713                 nvme_req(req)->result = cqe.result;
 714                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 715         }
 716
 717         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 718                 return;
 719
 720         if (likely(nvmeq->cq_vector >= 0))
 721                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 722         nvmeq->cq_head = head;
 723         nvmeq->cq_phase = phase;
 724
 725         nvmeq->cqe_seen = 1;
 726 }
 727
 728 static void nvme_process_cq(struct nvme_queue *nvmeq)
 729 {
 730         __nvme_process_cq(nvmeq, NULL);
 731 }
 732
 733 static irqreturn_t nvme_irq(int irq, void *data)
 734 {
 735         irqreturn_t result;
 736         struct nvme_queue *nvmeq = data;
 737         spin_lock(&nvmeq->q_lock);
 738         nvme_process_cq(nvmeq);
 739         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 740         nvmeq->cqe_seen = 0;
 741         spin_unlock(&nvmeq->q_lock);
 742         return result;
 743 }
 744
 745 static irqreturn_t nvme_irq_check(int irq, void *data)
 746 {
 747         struct nvme_queue *nvmeq = data;
 748         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 749                 return IRQ_WAKE_THREAD;
 750         return IRQ_NONE;
 751 }
 752
 753 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 754 {
 755         struct nvme_queue *nvmeq = hctx->driver_data;
 756
 757         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 758                 spin_lock_irq(&nvmeq->q_lock);
 759                 __nvme_process_cq(nvmeq, &tag);
 760                 spin_unlock_irq(&nvmeq->q_lock);
 761
 762                 if (tag == -1)
 763                         return 1;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 770 {
 771         struct nvme_dev *dev = to_nvme_dev(ctrl);
 772         struct nvme_queue *nvmeq = dev->queues[0];
 773         struct nvme_command c;
 774
 775         memset(&c, 0, sizeof(c));
 776         c.common.opcode = nvme_admin_async_event;
 777         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 778
 779         spin_lock_irq(&nvmeq->q_lock);
 780         __nvme_submit_cmd(nvmeq, &c);
 781         spin_unlock_irq(&nvmeq->q_lock);
 782 }
 783
 784 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 785 {
 786         struct nvme_command c;
 787
 788         memset(&c, 0, sizeof(c));
 789         c.delete_queue.opcode = opcode;
 790         c.delete_queue.qid = cpu_to_le16(id);
 791
 792         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 793 }
 794
 795 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 796                                                 struct nvme_queue *nvmeq)
 797 {
 798         struct nvme_command c;
 799         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 800
 801         /*
 802          * Note: we (ab)use the fact the the prp fields survive if no data
 803          * is attached to the request.
 804          */
 805         memset(&c, 0, sizeof(c));
 806         c.create_cq.opcode = nvme_admin_create_cq;
 807         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 808         c.create_cq.cqid = cpu_to_le16(qid);
 809         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 810         c.create_cq.cq_flags = cpu_to_le16(flags);
 811         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 812
 813         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 814 }
 815
 816 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 817                                                 struct nvme_queue *nvmeq)
 818 {
 819         struct nvme_command c;
 820         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 821
 822         /*
 823          * Note: we (ab)use the fact the the prp fields survive if no data
 824          * is attached to the request.
 825          */
 826         memset(&c, 0, sizeof(c));
 827         c.create_sq.opcode = nvme_admin_create_sq;
 828         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 829         c.create_sq.sqid = cpu_to_le16(qid);
 830         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 831         c.create_sq.sq_flags = cpu_to_le16(flags);
 832         c.create_sq.cqid = cpu_to_le16(qid);
 833
 834         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 835 }
 836
 837 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 838 {
 839         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 840 }
 841
 842 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 843 {
 844         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 845 }
 846
 847 static void abort_endio(struct request *req, int error)
 848 {
 849         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 850         struct nvme_queue *nvmeq = iod->nvmeq;
 851         u16 status = req->errors;
 852
 853         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 854         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 855         blk_mq_free_request(req);
 856 }
 857
 858 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 859 {
 860         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 861         struct nvme_queue *nvmeq = iod->nvmeq;
 862         struct nvme_dev *dev = nvmeq->dev;
 863         struct request *abort_req;
 864         struct nvme_command cmd;
 865
 866         /*
 867          * Shutdown immediately if controller times out while starting. The
 868          * reset work will see the pci device disabled when it gets the forced
 869          * cancellation error. All outstanding requests are completed on
 870          * shutdown, so we return BLK_EH_HANDLED.
 871          */
 872         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 873                 dev_warn(dev->ctrl.device,
 874                          "I/O %d QID %d timeout, disable controller\n",
 875                          req->tag, nvmeq->qid);
 876                 nvme_dev_disable(dev, false);
 877                 req->errors = NVME_SC_CANCELLED;
 878                 return BLK_EH_HANDLED;
 879         }
 880
 881         /*
 882          * Shutdown the controller immediately and schedule a reset if the
 883          * command was already aborted once before and still hasn't been
 884          * returned to the driver, or if this is the admin queue.
 885          */
 886         if (!nvmeq->qid || iod->aborted) {
 887                 dev_warn(dev->ctrl.device,
 888                          "I/O %d QID %d timeout, reset controller\n",
 889                          req->tag, nvmeq->qid);
 890                 nvme_dev_disable(dev, false);
 891                 nvme_reset(dev);
 892
 893                 /*
 894                  * Mark the request as handled, since the inline shutdown
 895                  * forces all outstanding requests to complete.
 896                  */
 897                 req->errors = NVME_SC_CANCELLED;
 898                 return BLK_EH_HANDLED;
 899         }
 900
 901         iod->aborted = 1;
 902
 903         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 904                 atomic_inc(&dev->ctrl.abort_limit);
 905                 return BLK_EH_RESET_TIMER;
 906         }
 907
 908         memset(&cmd, 0, sizeof(cmd));
 909         cmd.abort.opcode = nvme_admin_abort_cmd;
 910         cmd.abort.cid = req->tag;
 911         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 912
 913         dev_warn(nvmeq->dev->ctrl.device,
 914                 "I/O %d QID %d timeout, aborting\n",
 915                  req->tag, nvmeq->qid);
 916
 917         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 918                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 919         if (IS_ERR(abort_req)) {
 920                 atomic_inc(&dev->ctrl.abort_limit);
 921                 return BLK_EH_RESET_TIMER;
 922         }
 923
 924         abort_req->timeout = ADMIN_TIMEOUT;
 925         abort_req->end_io_data = NULL;
 926         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 927
 928         /*
 929          * The aborted req will be completed on receiving the abort req.
 930          * We enable the timer again. If hit twice, it'll cause a device reset,
 931          * as the device then is in a faulty state.
 932          */
 933         return BLK_EH_RESET_TIMER;
 934 }
 935
 936 static void nvme_free_queue(struct nvme_queue *nvmeq)
 937 {
 938         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 939                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 940         if (nvmeq->sq_cmds)
 941                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 942                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 943         kfree(nvmeq);
 944 }
 945
 946 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 947 {
 948         int i;
 949
 950         for (i = dev->queue_count - 1; i >= lowest; i--) {
 951                 struct nvme_queue *nvmeq = dev->queues[i];
 952                 dev->queue_count--;
 953                 dev->queues[i] = NULL;
 954                 nvme_free_queue(nvmeq);
 955         }
 956 }
 957
 958 /**
 959  * nvme_suspend_queue - put queue into suspended state
 960  * @nvmeq - queue to suspend
 961  */
 962 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 963 {
 964         int vector;
 965
 966         spin_lock_irq(&nvmeq->q_lock);
 967         if (nvmeq->cq_vector == -1) {
 968                 spin_unlock_irq(&nvmeq->q_lock);
 969                 return 1;
 970         }
 971         vector = nvmeq_irq(nvmeq);
 972         nvmeq->dev->online_queues--;
 973         nvmeq->cq_vector = -1;
 974         spin_unlock_irq(&nvmeq->q_lock);
 975
 976         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 977                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 978
 979         free_irq(vector, nvmeq);
 980
 981         return 0;
 982 }
 983
 984 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 985 {
 986         struct nvme_queue *nvmeq = dev->queues[0];
 987
 988         if (!nvmeq)
 989                 return;
 990         if (nvme_suspend_queue(nvmeq))
 991                 return;
 992
 993         if (shutdown)
 994                 nvme_shutdown_ctrl(&dev->ctrl);
 995         else
 996                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 997                                                 dev->bar + NVME_REG_CAP));
 998
 999         spin_lock_irq(&nvmeq->q_lock);
1000         nvme_process_cq(nvmeq);
1001         spin_unlock_irq(&nvmeq->q_lock);
1002 }
1003
1004 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1005                                 int entry_size)
1006 {
1007         int q_depth = dev->q_depth;
1008         unsigned q_size_aligned = roundup(q_depth * entry_size,
1009                                           dev->ctrl.page_size);
1010
1011         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1012                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1013                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1014                 q_depth = div_u64(mem_per_q, entry_size);
1015
1016                 /*
1017                  * Ensure the reduced q_depth is above some threshold where it
1018                  * would be better to map queues in system memory with the
1019                  * original depth
1020                  */
1021                 if (q_depth < 64)
1022                         return -ENOMEM;
1023         }
1024
1025         return q_depth;
1026 }
1027
1028 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1029                                 int qid, int depth)
1030 {
1031         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1032                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1033                                                       dev->ctrl.page_size);
1034                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1035                 nvmeq->sq_cmds_io = dev->cmb + offset;
1036         } else {
1037                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1038                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1039                 if (!nvmeq->sq_cmds)
1040                         return -ENOMEM;
1041         }
1042
1043         return 0;
1044 }
1045
1046 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1047                                                         int depth)
1048 {
1049         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1050         if (!nvmeq)
1051                 return NULL;
1052
1053         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1054                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1055         if (!nvmeq->cqes)
1056                 goto free_nvmeq;
1057
1058         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1059                 goto free_cqdma;
1060
1061         nvmeq->q_dmadev = dev->dev;
1062         nvmeq->dev = dev;
1063         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1064                         dev->ctrl.instance, qid);
1065         spin_lock_init(&nvmeq->q_lock);
1066         nvmeq->cq_head = 0;
1067         nvmeq->cq_phase = 1;
1068         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1069         nvmeq->q_depth = depth;
1070         nvmeq->qid = qid;
1071         nvmeq->cq_vector = -1;
1072         dev->queues[qid] = nvmeq;
1073         dev->queue_count++;
1074
1075         return nvmeq;
1076
1077  free_cqdma:
1078         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1079                                                         nvmeq->cq_dma_addr);
1080  free_nvmeq:
1081         kfree(nvmeq);
1082         return NULL;
1083 }
1084
1085 static int queue_request_irq(struct nvme_queue *nvmeq)
1086 {
1087         if (use_threaded_interrupts)
1088                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1089                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1090         else
1091                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1092                                 nvmeq->irqname, nvmeq);
1093 }
1094
1095 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1096 {
1097         struct nvme_dev *dev = nvmeq->dev;
1098
1099         spin_lock_irq(&nvmeq->q_lock);
1100         nvmeq->sq_tail = 0;
1101         nvmeq->cq_head = 0;
1102         nvmeq->cq_phase = 1;
1103         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1104         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1105         dev->online_queues++;
1106         spin_unlock_irq(&nvmeq->q_lock);
1107 }
1108
1109 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1110 {
1111         struct nvme_dev *dev = nvmeq->dev;
1112         int result;
1113
1114         nvmeq->cq_vector = qid - 1;
1115         result = adapter_alloc_cq(dev, qid, nvmeq);
1116         if (result < 0)
1117                 return result;
1118
1119         result = adapter_alloc_sq(dev, qid, nvmeq);
1120         if (result < 0)
1121                 goto release_cq;
1122
1123         result = queue_request_irq(nvmeq);
1124         if (result < 0)
1125                 goto release_sq;
1126
1127         nvme_init_queue(nvmeq, qid);
1128         return result;
1129
1130  release_sq:
1131         adapter_delete_sq(dev, qid);
1132  release_cq:
1133         adapter_delete_cq(dev, qid);
1134         return result;
1135 }
1136
1137 static struct blk_mq_ops nvme_mq_admin_ops = {
1138         .queue_rq       = nvme_queue_rq,
1139         .complete       = nvme_complete_rq,
1140         .init_hctx      = nvme_admin_init_hctx,
1141         .exit_hctx      = nvme_admin_exit_hctx,
1142         .init_request   = nvme_admin_init_request,
1143         .timeout        = nvme_timeout,
1144 };
1145
1146 static struct blk_mq_ops nvme_mq_ops = {
1147         .queue_rq       = nvme_queue_rq,
1148         .complete       = nvme_complete_rq,
1149         .init_hctx      = nvme_init_hctx,
1150         .init_request   = nvme_init_request,
1151         .map_queues     = nvme_pci_map_queues,
1152         .timeout        = nvme_timeout,
1153         .poll           = nvme_poll,
1154 };
1155
1156 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1157 {
1158         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1159                 /*
1160                  * If the controller was reset during removal, it's possible
1161                  * user requests may be waiting on a stopped queue. Start the
1162                  * queue to flush these to completion.
1163                  */
1164                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1165                 blk_cleanup_queue(dev->ctrl.admin_q);
1166                 blk_mq_free_tag_set(&dev->admin_tagset);
1167         }
1168 }
1169
1170 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1171 {
1172         if (!dev->ctrl.admin_q) {
1173                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1174                 dev->admin_tagset.nr_hw_queues = 1;
1175
1176                 /*
1177                  * Subtract one to leave an empty queue entry for 'Full Queue'
1178                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1179                  */
1180                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1181                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1182                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1183                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1184                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1185                 dev->admin_tagset.driver_data = dev;
1186
1187                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1188                         return -ENOMEM;
1189
1190                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1191                 if (IS_ERR(dev->ctrl.admin_q)) {
1192                         blk_mq_free_tag_set(&dev->admin_tagset);
1193                         return -ENOMEM;
1194                 }
1195                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1196                         nvme_dev_remove_admin(dev);
1197                         dev->ctrl.admin_q = NULL;
1198                         return -ENODEV;
1199                 }
1200         } else
1201                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1202
1203         return 0;
1204 }
1205
1206 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1207 {
1208         int result;
1209         u32 aqa;
1210         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1211         struct nvme_queue *nvmeq;
1212
1213         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1214                                                 NVME_CAP_NSSRC(cap) : 0;
1215
1216         if (dev->subsystem &&
1217             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1218                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1219
1220         result = nvme_disable_ctrl(&dev->ctrl, cap);
1221         if (result < 0)
1222                 return result;
1223
1224         nvmeq = dev->queues[0];
1225         if (!nvmeq) {
1226                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1227                 if (!nvmeq)
1228                         return -ENOMEM;
1229         }
1230
1231         aqa = nvmeq->q_depth - 1;
1232         aqa |= aqa << 16;
1233
1234         writel(aqa, dev->bar + NVME_REG_AQA);
1235         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1236         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1237
1238         result = nvme_enable_ctrl(&dev->ctrl, cap);
1239         if (result)
1240                 return result;
1241
1242         nvmeq->cq_vector = 0;
1243         result = queue_request_irq(nvmeq);
1244         if (result) {
1245                 nvmeq->cq_vector = -1;
1246                 return result;
1247         }
1248
1249         return result;
1250 }
1251
1252 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1253 {
1254
1255         /* If true, indicates loss of adapter communication, possibly by a
1256          * NVMe Subsystem reset.
1257          */
1258         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1259
1260         /* If there is a reset ongoing, we shouldn't reset again. */
1261         if (work_busy(&dev->reset_work))
1262                 return false;
1263
1264         /* We shouldn't reset unless the controller is on fatal error state
1265          * _or_ if we lost the communication with it.
1266          */
1267         if (!(csts & NVME_CSTS_CFS) && !nssro)
1268                 return false;
1269
1270         /* If PCI error recovery process is happening, we cannot reset or
1271          * the recovery mechanism will surely fail.
1272          */
1273         if (pci_channel_offline(to_pci_dev(dev->dev)))
1274                 return false;
1275
1276         return true;
1277 }
1278
1279 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1280 {
1281         /* Read a config register to help see what died. */
1282         u16 pci_status;
1283         int result;
1284
1285         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1286                                       &pci_status);
1287         if (result == PCIBIOS_SUCCESSFUL)
1288                 dev_warn(dev->dev,
1289                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1290                          csts, pci_status);
1291         else
1292                 dev_warn(dev->dev,
1293                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1294                          csts, result);
1295 }
1296
1297 static void nvme_watchdog_timer(unsigned long data)
1298 {
1299         struct nvme_dev *dev = (struct nvme_dev *)data;
1300         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1301
1302         /* Skip controllers under certain specific conditions. */
1303         if (nvme_should_reset(dev, csts)) {
1304                 if (!nvme_reset(dev))
1305                         nvme_warn_reset(dev, csts);
1306                 return;
1307         }
1308
1309         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1310 }
1311
1312 static int nvme_create_io_queues(struct nvme_dev *dev)
1313 {
1314         unsigned i, max;
1315         int ret = 0;
1316
1317         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1318                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1319                         ret = -ENOMEM;
1320                         break;
1321                 }
1322         }
1323
1324         max = min(dev->max_qid, dev->queue_count - 1);
1325         for (i = dev->online_queues; i <= max; i++) {
1326                 ret = nvme_create_queue(dev->queues[i], i);
1327                 if (ret)
1328                         break;
1329         }
1330
1331         /*
1332          * Ignore failing Create SQ/CQ commands, we can continue with less
1333          * than the desired aount of queues, and even a controller without
1334          * I/O queues an still be used to issue admin commands.  This might
1335          * be useful to upgrade a buggy firmware for example.
1336          */
1337         return ret >= 0 ? 0 : ret;
1338 }
1339
1340 static ssize_t nvme_cmb_show(struct device *dev,
1341                              struct device_attribute *attr,
1342                              char *buf)
1343 {
1344         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1345
1346         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1347                        ndev->cmbloc, ndev->cmbsz);
1348 }
1349 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1350
1351 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1352 {
1353         u64 szu, size, offset;
1354         resource_size_t bar_size;
1355         struct pci_dev *pdev = to_pci_dev(dev->dev);
1356         void __iomem *cmb;
1357         dma_addr_t dma_addr;
1358
1359         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1360         if (!(NVME_CMB_SZ(dev->cmbsz)))
1361                 return NULL;
1362         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1363
1364         if (!use_cmb_sqes)
1365                 return NULL;
1366
1367         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1368         size = szu * NVME_CMB_SZ(dev->cmbsz);
1369         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1370         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1371
1372         if (offset > bar_size)
1373                 return NULL;
1374
1375         /*
1376          * Controllers may support a CMB size larger than their BAR,
1377          * for example, due to being behind a bridge. Reduce the CMB to
1378          * the reported size of the BAR
1379          */
1380         if (size > bar_size - offset)
1381                 size = bar_size - offset;
1382
1383         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1384         cmb = ioremap_wc(dma_addr, size);
1385         if (!cmb)
1386                 return NULL;
1387
1388         dev->cmb_dma_addr = dma_addr;
1389         dev->cmb_size = size;
1390         return cmb;
1391 }
1392
1393 static inline void nvme_release_cmb(struct nvme_dev *dev)
1394 {
1395         if (dev->cmb) {
1396                 iounmap(dev->cmb);
1397                 dev->cmb = NULL;
1398         }
1399 }
1400
1401 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1402 {
1403         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1404 }
1405
1406 static int nvme_setup_io_queues(struct nvme_dev *dev)
1407 {
1408         struct nvme_queue *adminq = dev->queues[0];
1409         struct pci_dev *pdev = to_pci_dev(dev->dev);
1410         int result, nr_io_queues, size;
1411
1412         nr_io_queues = num_online_cpus();
1413         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1414         if (result < 0)
1415                 return result;
1416
1417         if (nr_io_queues == 0)
1418                 return 0;
1419
1420         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1421                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1422                                 sizeof(struct nvme_command));
1423                 if (result > 0)
1424                         dev->q_depth = result;
1425                 else
1426                         nvme_release_cmb(dev);
1427         }
1428
1429         size = db_bar_size(dev, nr_io_queues);
1430         if (size > 8192) {
1431                 iounmap(dev->bar);
1432                 do {
1433                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1434                         if (dev->bar)
1435                                 break;
1436                         if (!--nr_io_queues)
1437                                 return -ENOMEM;
1438                         size = db_bar_size(dev, nr_io_queues);
1439                 } while (1);
1440                 dev->dbs = dev->bar + 4096;
1441                 adminq->q_db = dev->dbs;
1442         }
1443
1444         /* Deregister the admin queue's interrupt */
1445         free_irq(pci_irq_vector(pdev, 0), adminq);
1446
1447         /*
1448          * If we enable msix early due to not intx, disable it again before
1449          * setting up the full range we need.
1450          */
1451         pci_free_irq_vectors(pdev);
1452         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1453                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1454         if (nr_io_queues <= 0)
1455                 return -EIO;
1456         dev->max_qid = nr_io_queues;
1457
1458         /*
1459          * Should investigate if there's a performance win from allocating
1460          * more queues than interrupt vectors; it might allow the submission
1461          * path to scale better, even if the receive path is limited by the
1462          * number of interrupts.
1463          */
1464
1465         result = queue_request_irq(adminq);
1466         if (result) {
1467                 adminq->cq_vector = -1;
1468                 return result;
1469         }
1470         return nvme_create_io_queues(dev);
1471 }
1472
1473 static void nvme_del_queue_end(struct request *req, int error)
1474 {
1475         struct nvme_queue *nvmeq = req->end_io_data;
1476
1477         blk_mq_free_request(req);
1478         complete(&nvmeq->dev->ioq_wait);
1479 }
1480
1481 static void nvme_del_cq_end(struct request *req, int error)
1482 {
1483         struct nvme_queue *nvmeq = req->end_io_data;
1484
1485         if (!error) {
1486                 unsigned long flags;
1487
1488                 /*
1489                  * We might be called with the AQ q_lock held
1490                  * and the I/O queue q_lock should always
1491                  * nest inside the AQ one.
1492                  */
1493                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1494                                         SINGLE_DEPTH_NESTING);
1495                 nvme_process_cq(nvmeq);
1496                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1497         }
1498
1499         nvme_del_queue_end(req, error);
1500 }
1501
1502 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1503 {
1504         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1505         struct request *req;
1506         struct nvme_command cmd;
1507
1508         memset(&cmd, 0, sizeof(cmd));
1509         cmd.delete_queue.opcode = opcode;
1510         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1511
1512         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1513         if (IS_ERR(req))
1514                 return PTR_ERR(req);
1515
1516         req->timeout = ADMIN_TIMEOUT;
1517         req->end_io_data = nvmeq;
1518
1519         blk_execute_rq_nowait(q, NULL, req, false,
1520                         opcode == nvme_admin_delete_cq ?
1521                                 nvme_del_cq_end : nvme_del_queue_end);
1522         return 0;
1523 }
1524
1525 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1526 {
1527         int pass;
1528         unsigned long timeout;
1529         u8 opcode = nvme_admin_delete_sq;
1530
1531         for (pass = 0; pass < 2; pass++) {
1532                 int sent = 0, i = queues;
1533
1534                 reinit_completion(&dev->ioq_wait);
1535  retry:
1536                 timeout = ADMIN_TIMEOUT;
1537                 for (; i > 0; i--, sent++)
1538                         if (nvme_delete_queue(dev->queues[i], opcode))
1539                                 break;
1540
1541                 while (sent--) {
1542                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1543                         if (timeout == 0)
1544                                 return;
1545                         if (i)
1546                                 goto retry;
1547                 }
1548                 opcode = nvme_admin_delete_cq;
1549         }
1550 }
1551
1552 /*
1553  * Return: error value if an error occurred setting up the queues or calling
1554  * Identify Device.  0 if these succeeded, even if adding some of the
1555  * namespaces failed.  At the moment, these failures are silent.  TBD which
1556  * failures should be reported.
1557  */
1558 static int nvme_dev_add(struct nvme_dev *dev)
1559 {
1560         if (!dev->ctrl.tagset) {
1561                 dev->tagset.ops = &nvme_mq_ops;
1562                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1563                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1564                 dev->tagset.numa_node = dev_to_node(dev->dev);
1565                 dev->tagset.queue_depth =
1566                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1567                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1568                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1569                 dev->tagset.driver_data = dev;
1570
1571                 if (blk_mq_alloc_tag_set(&dev->tagset))
1572                         return 0;
1573                 dev->ctrl.tagset = &dev->tagset;
1574         } else {
1575                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1576
1577                 /* Free previously allocated queues that are no longer usable */
1578                 nvme_free_queues(dev, dev->online_queues);
1579         }
1580
1581         return 0;
1582 }
1583
1584 static int nvme_pci_enable(struct nvme_dev *dev)
1585 {
1586         u64 cap;
1587         int result = -ENOMEM;
1588         struct pci_dev *pdev = to_pci_dev(dev->dev);
1589
1590         if (pci_enable_device_mem(pdev))
1591                 return result;
1592
1593         pci_set_master(pdev);
1594
1595         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1596             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1597                 goto disable;
1598
1599         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1600                 result = -ENODEV;
1601                 goto disable;
1602         }
1603
1604         /*
1605          * Some devices and/or platforms don't advertise or work with INTx
1606          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1607          * adjust this later.
1608          */
1609         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1610         if (result < 0)
1611                 return result;
1612
1613         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1614
1615         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1616         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1617         dev->dbs = dev->bar + 4096;
1618
1619         /*
1620          * Temporary fix for the Apple controller found in the MacBook8,1 and
1621          * some MacBook7,1 to avoid controller resets and data loss.
1622          */
1623         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1624                 dev->q_depth = 2;
1625                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1626                         "queue depth=%u to work around controller resets\n",
1627                         dev->q_depth);
1628         }
1629
1630         /*
1631          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1632          * populate sysfs if a CMB is implemented. Note that we add the
1633          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1634          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1635          * NULL as final argument to sysfs_add_file_to_group.
1636          */
1637
1638         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1639                 dev->cmb = nvme_map_cmb(dev);
1640
1641                 if (dev->cmbsz) {
1642                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1643                                                     &dev_attr_cmb.attr, NULL))
1644                                 dev_warn(dev->dev,
1645                                          "failed to add sysfs attribute for CMB\n");
1646                 }
1647         }
1648
1649         pci_enable_pcie_error_reporting(pdev);
1650         pci_save_state(pdev);
1651         return 0;
1652
1653  disable:
1654         pci_disable_device(pdev);
1655         return result;
1656 }
1657
1658 static void nvme_dev_unmap(struct nvme_dev *dev)
1659 {
1660         if (dev->bar)
1661                 iounmap(dev->bar);
1662         pci_release_mem_regions(to_pci_dev(dev->dev));
1663 }
1664
1665 static void nvme_pci_disable(struct nvme_dev *dev)
1666 {
1667         struct pci_dev *pdev = to_pci_dev(dev->dev);
1668
1669         pci_free_irq_vectors(pdev);
1670
1671         if (pci_is_enabled(pdev)) {
1672                 pci_disable_pcie_error_reporting(pdev);
1673                 pci_disable_device(pdev);
1674         }
1675 }
1676
1677 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1678 {
1679         int i, queues;
1680         u32 csts = -1;
1681
1682         del_timer_sync(&dev->watchdog_timer);
1683
1684         mutex_lock(&dev->shutdown_lock);
1685         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1686                 nvme_stop_queues(&dev->ctrl);
1687                 csts = readl(dev->bar + NVME_REG_CSTS);
1688         }
1689
1690         queues = dev->online_queues - 1;
1691         for (i = dev->queue_count - 1; i > 0; i--)
1692                 nvme_suspend_queue(dev->queues[i]);
1693
1694         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1695                 /* A device might become IO incapable very soon during
1696                  * probe, before the admin queue is configured. Thus,
1697                  * queue_count can be 0 here.
1698                  */
1699                 if (dev->queue_count)
1700                         nvme_suspend_queue(dev->queues[0]);
1701         } else {
1702                 nvme_disable_io_queues(dev, queues);
1703                 nvme_disable_admin_queue(dev, shutdown);
1704         }
1705         nvme_pci_disable(dev);
1706
1707         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1708         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1709         mutex_unlock(&dev->shutdown_lock);
1710 }
1711
1712 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1713 {
1714         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1715                                                 PAGE_SIZE, PAGE_SIZE, 0);
1716         if (!dev->prp_page_pool)
1717                 return -ENOMEM;
1718
1719         /* Optimisation for I/Os between 4k and 128k */
1720         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1721                                                 256, 256, 0);
1722         if (!dev->prp_small_pool) {
1723                 dma_pool_destroy(dev->prp_page_pool);
1724                 return -ENOMEM;
1725         }
1726         return 0;
1727 }
1728
1729 static void nvme_release_prp_pools(struct nvme_dev *dev)
1730 {
1731         dma_pool_destroy(dev->prp_page_pool);
1732         dma_pool_destroy(dev->prp_small_pool);
1733 }
1734
1735 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1736 {
1737         struct nvme_dev *dev = to_nvme_dev(ctrl);
1738
1739         put_device(dev->dev);
1740         if (dev->tagset.tags)
1741                 blk_mq_free_tag_set(&dev->tagset);
1742         if (dev->ctrl.admin_q)
1743                 blk_put_queue(dev->ctrl.admin_q);
1744         kfree(dev->queues);
1745         kfree(dev);
1746 }
1747
1748 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1749 {
1750         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1751
1752         kref_get(&dev->ctrl.kref);
1753         nvme_dev_disable(dev, false);
1754         if (!schedule_work(&dev->remove_work))
1755                 nvme_put_ctrl(&dev->ctrl);
1756 }
1757
1758 static void nvme_reset_work(struct work_struct *work)
1759 {
1760         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1761         int result = -ENODEV;
1762
1763         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1764                 goto out;
1765
1766         /*
1767          * If we're called to reset a live controller first shut it down before
1768          * moving on.
1769          */
1770         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1771                 nvme_dev_disable(dev, false);
1772
1773         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1774                 goto out;
1775
1776         result = nvme_pci_enable(dev);
1777         if (result)
1778                 goto out;
1779
1780         result = nvme_configure_admin_queue(dev);
1781         if (result)
1782                 goto out;
1783
1784         nvme_init_queue(dev->queues[0], 0);
1785         result = nvme_alloc_admin_tags(dev);
1786         if (result)
1787                 goto out;
1788
1789         result = nvme_init_identify(&dev->ctrl);
1790         if (result)
1791                 goto out;
1792
1793         result = nvme_setup_io_queues(dev);
1794         if (result)
1795                 goto out;
1796
1797         /*
1798          * A controller that can not execute IO typically requires user
1799          * intervention to correct. For such degraded controllers, the driver
1800          * should not submit commands the user did not request, so skip
1801          * registering for asynchronous event notification on this condition.
1802          */
1803         if (dev->online_queues > 1)
1804                 nvme_queue_async_events(&dev->ctrl);
1805
1806         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1807
1808         /*
1809          * Keep the controller around but remove all namespaces if we don't have
1810          * any working I/O queue.
1811          */
1812         if (dev->online_queues < 2) {
1813                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1814                 nvme_kill_queues(&dev->ctrl);
1815                 nvme_remove_namespaces(&dev->ctrl);
1816         } else {
1817                 nvme_start_queues(&dev->ctrl);
1818                 nvme_dev_add(dev);
1819         }
1820
1821         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1822                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1823                 goto out;
1824         }
1825
1826         if (dev->online_queues > 1)
1827                 nvme_queue_scan(&dev->ctrl);
1828         return;
1829
1830  out:
1831         nvme_remove_dead_ctrl(dev, result);
1832 }
1833
1834 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1835 {
1836         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1837         struct pci_dev *pdev = to_pci_dev(dev->dev);
1838
1839         nvme_kill_queues(&dev->ctrl);
1840         if (pci_get_drvdata(pdev))
1841                 device_release_driver(&pdev->dev);
1842         nvme_put_ctrl(&dev->ctrl);
1843 }
1844
1845 static int nvme_reset(struct nvme_dev *dev)
1846 {
1847         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1848                 return -ENODEV;
1849         if (work_busy(&dev->reset_work))
1850                 return -ENODEV;
1851         if (!queue_work(nvme_workq, &dev->reset_work))
1852                 return -EBUSY;
1853         return 0;
1854 }
1855
1856 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1857 {
1858         *val = readl(to_nvme_dev(ctrl)->bar + off);
1859         return 0;
1860 }
1861
1862 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1863 {
1864         writel(val, to_nvme_dev(ctrl)->bar + off);
1865         return 0;
1866 }
1867
1868 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1869 {
1870         *val = readq(to_nvme_dev(ctrl)->bar + off);
1871         return 0;
1872 }
1873
1874 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1875 {
1876         struct nvme_dev *dev = to_nvme_dev(ctrl);
1877         int ret = nvme_reset(dev);
1878
1879         if (!ret)
1880                 flush_work(&dev->reset_work);
1881         return ret;
1882 }
1883
1884 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1885         .name                   = "pcie",
1886         .module                 = THIS_MODULE,
1887         .reg_read32             = nvme_pci_reg_read32,
1888         .reg_write32            = nvme_pci_reg_write32,
1889         .reg_read64             = nvme_pci_reg_read64,
1890         .reset_ctrl             = nvme_pci_reset_ctrl,
1891         .free_ctrl              = nvme_pci_free_ctrl,
1892         .submit_async_event     = nvme_pci_submit_async_event,
1893 };
1894
1895 static int nvme_dev_map(struct nvme_dev *dev)
1896 {
1897         struct pci_dev *pdev = to_pci_dev(dev->dev);
1898
1899         if (pci_request_mem_regions(pdev, "nvme"))
1900                 return -ENODEV;
1901
1902         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1903         if (!dev->bar)
1904                 goto release;
1905
1906         return 0;
1907   release:
1908         pci_release_mem_regions(pdev);
1909         return -ENODEV;
1910 }
1911
1912 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1913 {
1914         int node, result = -ENOMEM;
1915         struct nvme_dev *dev;
1916
1917         node = dev_to_node(&pdev->dev);
1918         if (node == NUMA_NO_NODE)
1919                 set_dev_node(&pdev->dev, first_memory_node);
1920
1921         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1922         if (!dev)
1923                 return -ENOMEM;
1924         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1925                                                         GFP_KERNEL, node);
1926         if (!dev->queues)
1927                 goto free;
1928
1929         dev->dev = get_device(&pdev->dev);
1930         pci_set_drvdata(pdev, dev);
1931
1932         result = nvme_dev_map(dev);
1933         if (result)
1934                 goto free;
1935
1936         INIT_WORK(&dev->reset_work, nvme_reset_work);
1937         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1938         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1939                 (unsigned long)dev);
1940         mutex_init(&dev->shutdown_lock);
1941         init_completion(&dev->ioq_wait);
1942
1943         result = nvme_setup_prp_pools(dev);
1944         if (result)
1945                 goto put_pci;
1946
1947         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1948                         id->driver_data);
1949         if (result)
1950                 goto release_pools;
1951
1952         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1953
1954         queue_work(nvme_workq, &dev->reset_work);
1955         return 0;
1956
1957  release_pools:
1958         nvme_release_prp_pools(dev);
1959  put_pci:
1960         put_device(dev->dev);
1961         nvme_dev_unmap(dev);
1962  free:
1963         kfree(dev->queues);
1964         kfree(dev);
1965         return result;
1966 }
1967
1968 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1969 {
1970         struct nvme_dev *dev = pci_get_drvdata(pdev);
1971
1972         if (prepare)
1973                 nvme_dev_disable(dev, false);
1974         else
1975                 nvme_reset(dev);
1976 }
1977
1978 static void nvme_shutdown(struct pci_dev *pdev)
1979 {
1980         struct nvme_dev *dev = pci_get_drvdata(pdev);
1981         nvme_dev_disable(dev, true);
1982 }
1983
1984 /*
1985  * The driver's remove may be called on a device in a partially initialized
1986  * state. This function must not have any dependencies on the device state in
1987  * order to proceed.
1988  */
1989 static void nvme_remove(struct pci_dev *pdev)
1990 {
1991         struct nvme_dev *dev = pci_get_drvdata(pdev);
1992
1993         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1994
1995         pci_set_drvdata(pdev, NULL);
1996
1997         if (!pci_device_is_present(pdev))
1998                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1999
2000         flush_work(&dev->reset_work);
2001         nvme_uninit_ctrl(&dev->ctrl);
2002         nvme_dev_disable(dev, true);
2003         nvme_dev_remove_admin(dev);
2004         nvme_free_queues(dev, 0);
2005         nvme_release_cmb(dev);
2006         nvme_release_prp_pools(dev);
2007         nvme_dev_unmap(dev);
2008         nvme_put_ctrl(&dev->ctrl);
2009 }
2010
2011 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2012 {
2013         int ret = 0;
2014
2015         if (numvfs == 0) {
2016                 if (pci_vfs_assigned(pdev)) {
2017                         dev_warn(&pdev->dev,
2018                                 "Cannot disable SR-IOV VFs while assigned\n");
2019                         return -EPERM;
2020                 }
2021                 pci_disable_sriov(pdev);
2022                 return 0;
2023         }
2024
2025         ret = pci_enable_sriov(pdev, numvfs);
2026         return ret ? ret : numvfs;
2027 }
2028
2029 #ifdef CONFIG_PM_SLEEP
2030 static int nvme_suspend(struct device *dev)
2031 {
2032         struct pci_dev *pdev = to_pci_dev(dev);
2033         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2034
2035         nvme_dev_disable(ndev, true);
2036         return 0;
2037 }
2038
2039 static int nvme_resume(struct device *dev)
2040 {
2041         struct pci_dev *pdev = to_pci_dev(dev);
2042         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2043
2044         nvme_reset(ndev);
2045         return 0;
2046 }
2047 #endif
2048
2049 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2050
2051 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2052                                                 pci_channel_state_t state)
2053 {
2054         struct nvme_dev *dev = pci_get_drvdata(pdev);
2055
2056         /*
2057          * A frozen channel requires a reset. When detected, this method will
2058          * shutdown the controller to quiesce. The controller will be restarted
2059          * after the slot reset through driver's slot_reset callback.
2060          */
2061         switch (state) {
2062         case pci_channel_io_normal:
2063                 return PCI_ERS_RESULT_CAN_RECOVER;
2064         case pci_channel_io_frozen:
2065                 dev_warn(dev->ctrl.device,
2066                         "frozen state error detected, reset controller\n");
2067                 nvme_dev_disable(dev, false);
2068                 return PCI_ERS_RESULT_NEED_RESET;
2069         case pci_channel_io_perm_failure:
2070                 dev_warn(dev->ctrl.device,
2071                         "failure state error detected, request disconnect\n");
2072                 return PCI_ERS_RESULT_DISCONNECT;
2073         }
2074         return PCI_ERS_RESULT_NEED_RESET;
2075 }
2076
2077 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2078 {
2079         struct nvme_dev *dev = pci_get_drvdata(pdev);
2080
2081         dev_info(dev->ctrl.device, "restart after slot reset\n");
2082         pci_restore_state(pdev);
2083         nvme_reset(dev);
2084         return PCI_ERS_RESULT_RECOVERED;
2085 }
2086
2087 static void nvme_error_resume(struct pci_dev *pdev)
2088 {
2089         pci_cleanup_aer_uncorrect_error_status(pdev);
2090 }
2091
2092 static const struct pci_error_handlers nvme_err_handler = {
2093         .error_detected = nvme_error_detected,
2094         .slot_reset     = nvme_slot_reset,
2095         .resume         = nvme_error_resume,
2096         .reset_notify   = nvme_reset_notify,
2097 };
2098
2099 static const struct pci_device_id nvme_id_table[] = {
2100         { PCI_VDEVICE(INTEL, 0x0953),
2101                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2102                                 NVME_QUIRK_DISCARD_ZEROES, },
2103         { PCI_VDEVICE(INTEL, 0x0a53),
2104                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2105                                 NVME_QUIRK_DISCARD_ZEROES, },
2106         { PCI_VDEVICE(INTEL, 0x0a54),
2107                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2108                                 NVME_QUIRK_DISCARD_ZEROES, },
2109         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2110                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2111         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2112                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2113         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2114                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2115         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2116         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2117         { 0, }
2118 };
2119 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2120
2121 static struct pci_driver nvme_driver = {
2122         .name           = "nvme",
2123         .id_table       = nvme_id_table,
2124         .probe          = nvme_probe,
2125         .remove         = nvme_remove,
2126         .shutdown       = nvme_shutdown,
2127         .driver         = {
2128                 .pm     = &nvme_dev_pm_ops,
2129         },
2130         .sriov_configure = nvme_pci_sriov_configure,
2131         .err_handler    = &nvme_err_handler,
2132 };
2133
2134 static int __init nvme_init(void)
2135 {
2136         int result;
2137
2138         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2139         if (!nvme_workq)
2140                 return -ENOMEM;
2141
2142         result = pci_register_driver(&nvme_driver);
2143         if (result)
2144                 destroy_workqueue(nvme_workq);
2145         return result;
2146 }
2147
2148 static void __exit nvme_exit(void)
2149 {
2150         pci_unregister_driver(&nvme_driver);
2151         destroy_workqueue(nvme_workq);
2152         _nvme_check_size();
2153 }
2154
2155 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2156 MODULE_LICENSE("GPL");
2157 MODULE_VERSION("1.0");
2158 module_init(nvme_init);
2159 module_exit(nvme_exit);