3 ** PCI Lower Bus Adapter (LBA) manager
5 ** (c) Copyright 1999,2000 Grant Grundler
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
8 ** This program is free software; you can redistribute it and/or modify
9 ** it under the terms of the GNU General Public License as published by
10 ** the Free Software Foundation; either version 2 of the License, or
11 ** (at your option) any later version.
14 ** This module primarily provides access to PCI bus (config/IOport
15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
16 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
18 ** LBA driver isn't as simple as the Dino driver because:
19 ** (a) this chip has substantial bug fixes between revisions
20 ** (Only one Dino bug has a software workaround :^( )
21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
24 ** (dino only deals with "Legacy" PDC)
26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
27 ** (I/O SAPIC is integratd in the LBA chip).
29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
30 ** FIXME: Add support for PCI card hot-plug (OLARD).
33 #include <linux/delay.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/spinlock.h>
37 #include <linux/init.h> /* for __init and __devinit */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/smp_lock.h>
43 #include <asm/byteorder.h>
45 #include <asm/pdcpat.h>
47 #include <asm/system.h>
49 #include <asm/ropes.h>
50 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
51 #include <asm/parisc-device.h>
52 #include <asm/io.h> /* read/write stuff */
54 #undef DEBUG_LBA /* general stuff */
55 #undef DEBUG_LBA_PORT /* debug I/O Port access */
56 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
57 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
59 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
63 #define DBG(x...) printk(x)
69 #define DBG_PORT(x...) printk(x)
71 #define DBG_PORT(x...)
75 #define DBG_CFG(x...) printk(x)
81 #define DBG_PAT(x...) printk(x)
88 ** Config accessor functions only pass in the 8-bit bus number and not
89 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
90 ** number based on what firmware wrote into the scratch register.
92 ** The "secondary" bus number is set to this before calling
93 ** pci_register_ops(). If any PPB's are present, the scan will
94 ** discover them and update the "secondary" and "subordinate"
95 ** fields in the pci_bus structure.
97 ** Changes in the configuration *may* result in a different
98 ** bus number for each LBA depending on what firmware does.
101 #define MODULE_NAME "LBA"
103 #define LBA_FUNC_ID 0x0000 /* function id */
104 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
105 #define LBA_CAPABLE 0x0030 /* capabilities register */
107 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
108 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
110 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
111 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
112 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
114 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
115 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
116 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
117 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
119 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
121 #define LBA_STAT_CTL 0x0108 /* Status & Control */
122 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
123 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
124 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
125 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
127 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
128 #define LBA_LMMIO_MASK 0x0208
130 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
131 #define LBA_GMMIO_MASK 0x0218
133 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
134 #define LBA_WLMMIO_MASK 0x0228
136 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
137 #define LBA_WGMMIO_MASK 0x0238
139 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
140 #define LBA_IOS_MASK 0x0248
142 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
143 #define LBA_ELMMIO_MASK 0x0258
145 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
146 #define LBA_EIOS_MASK 0x0268
148 #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
149 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
151 #define LBA_IBASE 0x0300 /* SBA DMA support */
152 #define LBA_IMASK 0x0308
154 /* FIXME: ignore DMA Hint stuff until we can measure performance */
155 #define LBA_HINT_CFG 0x0310
156 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
158 #define LBA_BUS_MODE 0x0620
160 /* ERROR regs are needed for config cycle kluges */
161 #define LBA_ERROR_CONFIG 0x0680
162 #define LBA_SMART_MODE 0x20
163 #define LBA_ERROR_STATUS 0x0688
164 #define LBA_ROPE_CTL 0x06A0
166 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
168 /* non-postable I/O port space, densely packed */
169 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
170 static void __iomem *astro_iop_base __read_mostly;
175 #define LBA_FLAG_SKIP_PROBE 0x10
177 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
180 /* Looks nice and keeps the compiler happy */
181 #define LBA_DEV(d) ((struct lba_device *) (d))
185 ** Only allow 8 subsidiary busses per LBA
186 ** Problem is the PCI bus numbering is globally shared.
188 #define LBA_MAX_NUM_BUSES 8
190 /************************************
191 * LBA register read and write support
193 * BE WARNED: register writes are posted.
194 * (ie follow writes which must reach HW with a read)
196 #define READ_U8(addr) __raw_readb(addr)
197 #define READ_U16(addr) __raw_readw(addr)
198 #define READ_U32(addr) __raw_readl(addr)
199 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
200 #define WRITE_U16(value, addr) __raw_writew(value, addr)
201 #define WRITE_U32(value, addr) __raw_writel(value, addr)
203 #define READ_REG8(addr) readb(addr)
204 #define READ_REG16(addr) readw(addr)
205 #define READ_REG32(addr) readl(addr)
206 #define READ_REG64(addr) readq(addr)
207 #define WRITE_REG8(value, addr) writeb(value, addr)
208 #define WRITE_REG16(value, addr) writew(value, addr)
209 #define WRITE_REG32(value, addr) writel(value, addr)
212 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
213 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
214 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
215 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
219 ** Extract LBA (Rope) number from HPA
220 ** REVISIT: 16 ropes for Stretch/Ike?
222 #define ROPES_PER_IOC 8
223 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
227 lba_dump_res(struct resource *r, int d)
234 printk(KERN_DEBUG "(%p)", r->parent);
235 for (i = d; i ; --i) printk(" ");
236 printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r, r->start, r->end, r->flags);
237 lba_dump_res(r->child, d+2);
238 lba_dump_res(r->sibling, d);
243 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
244 ** workaround for cfg cycles:
245 ** -- preserve LBA state
246 ** -- prevent any DMA from occurring
247 ** -- turn on smart mode
248 ** -- probe with config writes before doing config reads
249 ** -- check ERROR_STATUS
250 ** -- clear ERROR_STATUS
251 ** -- restore LBA state
253 ** The workaround is only used for device discovery.
256 static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
258 u8 first_bus = d->hba.hba_bus->secondary;
259 u8 last_sub_bus = d->hba.hba_bus->subordinate;
261 if ((bus < first_bus) ||
262 (bus > last_sub_bus) ||
263 ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
272 #define LBA_CFG_SETUP(d, tok) { \
273 /* Save contents of error config register. */ \
274 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
276 /* Save contents of status control register. */ \
277 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
279 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
280 ** arbitration for full bus walks. \
282 /* Save contents of arb mask register. */ \
283 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
286 * Turn off all device arbitration bits (i.e. everything \
287 * except arbitration enable bit). \
289 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
292 * Set the smart mode bit so that master aborts don't cause \
293 * LBA to go into PCI fatal mode (required). \
295 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
299 #define LBA_CFG_PROBE(d, tok) { \
301 * Setup Vendor ID write and read back the address register \
302 * to make sure that LBA is the bus master. \
304 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
306 * Read address register to ensure that LBA is the bus master, \
307 * which implies that DMA traffic has stopped when DMA arb is off. \
309 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
311 * Generate a cfg write cycle (will have no affect on \
312 * Vendor ID register since read-only). \
314 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
316 * Make sure write has completed before proceeding further, \
317 * i.e. before setting clear enable. \
319 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
325 * -- Can't tell if config cycle got the error.
327 * OV bit is broken until rev 4.0, so can't use OV bit and
328 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
330 * As of rev 4.0, no longer need the error check.
332 * -- Even if we could tell, we still want to return -1
333 * for **ANY** error (not just master abort).
335 * -- Only clear non-fatal errors (we don't want to bring
336 * LBA out of pci-fatal mode).
338 * Actually, there is still a race in which
339 * we could be clearing a fatal error. We will
340 * live with this during our initial bus walk
341 * until rev 4.0 (no driver activity during
342 * initial bus walk). The initial bus walk
343 * has race conditions concerning the use of
344 * smart mode as well.
347 #define LBA_MASTER_ABORT_ERROR 0xc
348 #define LBA_FATAL_ERROR 0x10
350 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
351 u32 error_status = 0; \
353 * Set clear enable (CE) bit. Unset by HW when new \
354 * errors are logged -- LBA HW ERS section 14.3.3). \
356 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
357 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
358 if ((error_status & 0x1f) != 0) { \
360 * Fail the config read request. \
363 if ((error_status & LBA_FATAL_ERROR) == 0) { \
365 * Clear error status (if fatal bit not set) by setting \
366 * clear error log bit (CL). \
368 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
373 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
374 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
376 #define LBA_CFG_ADDR_SETUP(d, addr) { \
377 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
379 * Read address register to ensure that LBA is the bus master, \
380 * which implies that DMA traffic has stopped when DMA arb is off. \
382 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
386 #define LBA_CFG_RESTORE(d, base) { \
388 * Restore status control register (turn off clear enable). \
390 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
392 * Restore error config register (turn off smart mode). \
394 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
396 * Restore arb mask register (reenables DMA arbitration). \
398 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
404 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
408 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
409 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
410 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
412 LBA_CFG_SETUP(d, tok);
413 LBA_CFG_PROBE(d, tok);
414 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
416 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
418 LBA_CFG_ADDR_SETUP(d, tok | reg);
420 case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
421 case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
422 case 4: data = READ_REG32(data_reg); break;
425 LBA_CFG_RESTORE(d, d->hba.base_addr);
430 static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
432 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
433 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
434 u32 tok = LBA_CFG_TOK(local_bus, devfn);
435 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
437 if ((pos > 255) || (devfn > 255))
440 /* FIXME: B2K/C3600 workaround is always use old method... */
441 /* if (!LBA_SKIP_PROBE(d)) */ {
442 /* original - Generate config cycle on broken elroy
443 with risk we will miss PCI bus errors. */
444 *data = lba_rd_cfg(d, tok, pos, size);
445 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
449 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) {
450 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
451 /* either don't want to look or know device isn't present. */
457 ** Should only get here on fully working LBA rev.
458 ** This is how simple the code should have been.
460 LBA_CFG_ADDR_SETUP(d, tok | pos);
462 case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
463 case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
464 case 4: *data = READ_REG32(data_reg); break;
466 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
472 lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
476 u32 error_config = 0;
477 u32 status_control = 0;
478 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
480 LBA_CFG_SETUP(d, tok);
481 LBA_CFG_ADDR_SETUP(d, tok | reg);
483 case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
484 case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
485 case 4: WRITE_REG32(data, data_reg); break;
487 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
488 LBA_CFG_RESTORE(d, d->hba.base_addr);
493 * LBA 4.0 config write code implements non-postable semantics
494 * by doing a read of CONFIG ADDR after the write.
497 static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
499 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
500 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
501 u32 tok = LBA_CFG_TOK(local_bus,devfn);
503 if ((pos > 255) || (devfn > 255))
506 if (!LBA_SKIP_PROBE(d)) {
507 /* Original Workaround */
508 lba_wr_cfg(d, tok, pos, (u32) data, size);
509 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
513 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
514 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
515 return 1; /* New Workaround */
518 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
520 /* Basic Algorithm */
521 LBA_CFG_ADDR_SETUP(d, tok | pos);
523 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
525 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
527 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
530 /* flush posted write */
531 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
536 static struct pci_ops elroy_cfg_ops = {
537 .read = elroy_cfg_read,
538 .write = elroy_cfg_write,
542 * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
543 * TR4.0 as no additional bugs were found in this areea between Elroy and
547 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
549 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
550 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
551 u32 tok = LBA_CFG_TOK(local_bus, devfn);
552 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
554 if ((pos > 255) || (devfn > 255))
557 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
560 *data = READ_REG8(data_reg + (pos & 3));
563 *data = READ_REG16(data_reg + (pos & 2));
566 *data = READ_REG32(data_reg); break;
570 DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
575 * LBA 4.0 config write code implements non-postable semantics
576 * by doing a read of CONFIG ADDR after the write.
579 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
581 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
582 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
583 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
584 u32 tok = LBA_CFG_TOK(local_bus,devfn);
586 if ((pos > 255) || (devfn > 255))
589 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data);
591 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
594 WRITE_REG8 (data, data_reg + (pos & 3));
597 WRITE_REG16(data, data_reg + (pos & 2));
600 WRITE_REG32(data, data_reg);
604 /* flush posted write */
605 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
609 static struct pci_ops mercury_cfg_ops = {
610 .read = mercury_cfg_read,
611 .write = mercury_cfg_write,
618 DBG(MODULE_NAME ": lba_bios_init\n");
625 ** Determine if a device is already configured.
626 ** If so, reserve it resources.
628 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
629 ** PAT has to enable the devices it's using.
631 ** Note: resources are fixed up before we try to claim them.
634 lba_claim_dev_resources(struct pci_dev *dev)
639 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
641 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
642 if (cmd & PCI_COMMAND_MEMORY)
643 srch_flags |= IORESOURCE_MEM;
648 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
649 if (dev->resource[i].flags & srch_flags) {
650 pci_claim_resource(dev, i);
651 DBG(" claimed %s %d [%lx,%lx]/%lx\n",
653 dev->resource[i].start,
654 dev->resource[i].end,
655 dev->resource[i].flags
663 * truncate_pat_collision: Deal with overlaps or outright collisions
664 * between PAT PDC reported ranges.
666 * Broken PA8800 firmware will report lmmio range that
667 * overlaps with CPU HPA. Just truncate the lmmio range.
669 * BEWARE: conflicts with this lmmio range may be an
670 * elmmio range which is pointing down another rope.
672 * FIXME: only deals with one collision per range...theoretically we
673 * could have several. Supporting more than one collision will get messy.
676 truncate_pat_collision(struct resource *root, struct resource *new)
678 unsigned long start = new->start;
679 unsigned long end = new->end;
680 struct resource *tmp = root->child;
682 if (end <= start || start < root->start || !tmp)
685 /* find first overlap */
686 while (tmp && tmp->end < start)
689 /* no entries overlap */
692 /* found one that starts behind the new one
693 ** Don't need to do anything.
695 if (tmp->start >= end) return 0;
697 if (tmp->start <= start) {
698 /* "front" of new one overlaps */
699 new->start = tmp->end + 1;
701 if (tmp->end >= end) {
702 /* AACCKK! totally overlaps! drop this range. */
707 if (tmp->end < end ) {
708 /* "end" of new one overlaps */
709 new->end = tmp->start - 1;
712 printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
715 new->start, new->end );
717 return 0; /* truncation successful */
721 #define lba_claim_dev_resources(dev) do { } while (0)
722 #define truncate_pat_collision(r,n) (0)
726 ** The algorithm is generic code.
727 ** But it needs to access local data structures to get the IRQ base.
728 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
731 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
732 ** Resources aren't allocated until recursive buswalk below HBA is completed.
735 lba_fixup_bus(struct pci_bus *bus)
737 struct list_head *ln;
741 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
742 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
744 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
745 bus, bus->secondary, bus->bridge->platform_data);
748 ** Properly Setup MMIO resources for this bus.
749 ** pci_alloc_primary_bus() mangles this.
753 pci_read_bridge_bases(bus);
755 /* Host-PCI Bridge */
758 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
759 ldev->hba.io_space.name,
760 ldev->hba.io_space.start, ldev->hba.io_space.end,
761 ldev->hba.io_space.flags);
762 DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
763 ldev->hba.lmmio_space.name,
764 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
765 ldev->hba.lmmio_space.flags);
767 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
769 lba_dump_res(&ioport_resource, 2);
772 /* advertize Host bridge resources to PCI bus */
773 bus->resource[0] = &(ldev->hba.io_space);
776 if (ldev->hba.elmmio_space.start) {
777 err = request_resource(&iomem_resource,
778 &(ldev->hba.elmmio_space));
781 printk("FAILED: lba_fixup_bus() request for "
782 "elmmio_space [%lx/%lx]\n",
783 ldev->hba.elmmio_space.start,
784 ldev->hba.elmmio_space.end);
786 /* lba_dump_res(&iomem_resource, 2); */
789 bus->resource[i++] = &(ldev->hba.elmmio_space);
793 /* Overlaps with elmmio can (and should) fail here.
794 * We will prune (or ignore) the distributed range.
796 * FIXME: SBA code should register all elmmio ranges first.
797 * that would take care of elmmio ranges routed
798 * to a different rope (already discovered) from
799 * getting registered *after* LBA code has already
800 * registered it's distributed lmmio range.
802 if (truncate_pat_collision(&iomem_resource,
803 &(ldev->hba.lmmio_space))) {
805 printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
806 ldev->hba.lmmio_space.start,
807 ldev->hba.lmmio_space.end);
809 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
811 printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
812 "lmmio_space [%lx/%lx]\n",
813 ldev->hba.lmmio_space.start,
814 ldev->hba.lmmio_space.end);
816 bus->resource[i++] = &(ldev->hba.lmmio_space);
820 /* GMMIO is distributed range. Every LBA/Rope gets part it. */
821 if (ldev->hba.gmmio_space.flags) {
822 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
824 printk("FAILED: lba_fixup_bus() request for "
825 "gmmio_space [%lx/%lx]\n",
826 ldev->hba.gmmio_space.start,
827 ldev->hba.gmmio_space.end);
828 lba_dump_res(&iomem_resource, 2);
831 bus->resource[i++] = &(ldev->hba.gmmio_space);
837 list_for_each(ln, &bus->devices) {
839 struct pci_dev *dev = pci_dev_b(ln);
841 DBG("lba_fixup_bus() %s\n", pci_name(dev));
843 /* Virtualize Device/Bridge Resources. */
844 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
845 struct resource *res = &dev->resource[i];
847 /* If resource not allocated - skip it */
851 if (res->flags & IORESOURCE_IO) {
852 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
853 res->start, res->end);
854 res->start |= lba_portbase;
855 res->end |= lba_portbase;
856 DBG("[%lx/%lx]\n", res->start, res->end);
857 } else if (res->flags & IORESOURCE_MEM) {
859 ** Convert PCI (IO_VIEW) addresses to
860 ** processor (PA_VIEW) addresses
862 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
863 res->start, res->end);
864 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
865 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
866 DBG("[%lx/%lx]\n", res->start, res->end);
868 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX",
869 res->flags, res->start, res->end);
875 ** If one device does not support FBB transfers,
876 ** No one on the bus can be allowed to use them.
878 (void) pci_read_config_word(dev, PCI_STATUS, &status);
879 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
883 /* Claim resources for PDC's devices */
884 lba_claim_dev_resources(dev);
888 ** P2PB's have no IRQs. ignore them.
890 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
893 /* Adjust INTERRUPT_LINE for this dev */
894 iosapic_fixup_irq(ldev->iosapic_obj, dev);
898 /* FIXME/REVISIT - finish figuring out to set FBB on both
899 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
900 ** Can't fixup here anyway....garr...
906 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
907 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
912 fbb_enable = PCI_COMMAND_FAST_BACK;
915 /* Lastly enable FBB/PERR/SERR on all devices too */
916 list_for_each(ln, &bus->devices) {
917 (void) pci_read_config_word(dev, PCI_COMMAND, &status);
918 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
919 (void) pci_write_config_word(dev, PCI_COMMAND, status);
925 struct pci_bios_ops lba_bios_ops = {
926 .init = lba_bios_init,
927 .fixup_bus = lba_fixup_bus,
933 /*******************************************************
935 ** LBA Sprockets "I/O Port" Space Accessor Functions
937 ** This set of accessor functions is intended for use with
938 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
940 ** Many PCI devices don't require use of I/O port space (eg Tulip,
941 ** NCR720) since they export the same registers to both MMIO and
942 ** I/O port space. In general I/O port space is slower than
943 ** MMIO since drivers are designed so PIO writes can be posted.
945 ********************************************************/
947 #define LBA_PORT_IN(size, mask) \
948 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
951 t = READ_REG##size(astro_iop_base + addr); \
952 DBG_PORT(" 0x%x\n", t); \
963 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
965 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
966 ** guarantee non-postable completion semantics - not avoid X4107.
967 ** The READ_U32 only guarantees the write data gets to elroy but
968 ** out to the PCI bus. We can't read stuff from I/O port space
969 ** since we don't know what has side-effects. Attempting to read
970 ** from configuration space would be suicidal given the number of
971 ** bugs in that elroy functionality.
974 ** DMA read results can improperly pass PIO writes (X4107). The
975 ** result of this bug is that if a processor modifies a location in
976 ** memory after having issued PIO writes, the PIO writes are not
977 ** guaranteed to be completed before a PCI device is allowed to see
978 ** the modified data in a DMA read.
980 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
984 ** The workaround for this bug is to always follow a PIO write with
985 ** a PIO read to the same bus before starting DMA on that PCI bus.
988 #define LBA_PORT_OUT(size, mask) \
989 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
991 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
992 WRITE_REG##size(val, astro_iop_base + addr); \
993 if (LBA_DEV(d)->hw_rev < 3) \
994 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
1002 static struct pci_port_ops lba_astro_port_ops = {
1003 .inb = lba_astro_in8,
1004 .inw = lba_astro_in16,
1005 .inl = lba_astro_in32,
1006 .outb = lba_astro_out8,
1007 .outw = lba_astro_out16,
1008 .outl = lba_astro_out32
1013 #define PIOP_TO_GMMIO(lba, addr) \
1014 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
1016 /*******************************************************
1018 ** LBA PAT "I/O Port" Space Accessor Functions
1020 ** This set of accessor functions is intended for use with
1021 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
1023 ** This uses the PIOP space located in the first 64MB of GMMIO.
1024 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
1025 ** bits 1:0 stay the same. bits 15:2 become 25:12.
1026 ** Then add the base and we can generate an I/O Port cycle.
1027 ********************************************************/
1029 #define LBA_PORT_IN(size, mask) \
1030 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
1033 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
1034 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
1035 DBG_PORT(" 0x%x\n", t); \
1045 #define LBA_PORT_OUT(size, mask) \
1046 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
1048 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
1049 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
1050 WRITE_REG##size(val, where); \
1051 /* flush the I/O down to the elroy at least */ \
1052 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1060 static struct pci_port_ops lba_pat_port_ops = {
1062 .inw = lba_pat_in16,
1063 .inl = lba_pat_in32,
1064 .outb = lba_pat_out8,
1065 .outw = lba_pat_out16,
1066 .outl = lba_pat_out32
1072 ** make range information from PDC available to PCI subsystem.
1073 ** We make the PDC call here in order to get the PCI bus range
1074 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
1075 ** We don't have a struct pci_bus assigned to us yet.
1078 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1080 unsigned long bytecnt;
1081 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */
1082 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */
1084 long status; /* PDC return status */
1088 /* return cell module (IO view) */
1089 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1090 PA_VIEW, & pa_pdc_cell);
1091 pa_count = pa_pdc_cell.mod[1];
1093 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1094 IO_VIEW, &io_pdc_cell);
1095 io_count = io_pdc_cell.mod[1];
1097 /* We've already done this once for device discovery...*/
1098 if (status != PDC_OK) {
1099 panic("pdc_pat_cell_module() call failed for LBA!\n");
1102 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
1103 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1107 ** Inspect the resources PAT tells us about
1109 for (i = 0; i < pa_count; i++) {
1112 unsigned long start;
1113 unsigned long end; /* aka finish */
1117 p = (void *) &(pa_pdc_cell.mod[2+i*3]);
1118 io = (void *) &(io_pdc_cell.mod[2+i*3]);
1120 /* Convert the PAT range data to PCI "struct resource" */
1121 switch(p->type & 0xff) {
1123 lba_dev->hba.bus_num.start = p->start;
1124 lba_dev->hba.bus_num.end = p->end;
1128 /* used to fix up pre-initialized MEM BARs */
1129 if (!lba_dev->hba.lmmio_space.start) {
1130 sprintf(lba_dev->hba.lmmio_name,
1132 lba_dev->hba.bus_num.start);
1133 lba_dev->hba.lmmio_space_offset = p->start -
1135 r = &lba_dev->hba.lmmio_space;
1136 r->name = lba_dev->hba.lmmio_name;
1137 } else if (!lba_dev->hba.elmmio_space.start) {
1138 sprintf(lba_dev->hba.elmmio_name,
1140 lba_dev->hba.bus_num.start);
1141 r = &lba_dev->hba.elmmio_space;
1142 r->name = lba_dev->hba.elmmio_name;
1144 printk(KERN_WARNING MODULE_NAME
1145 " only supports 2 LMMIO resources!\n");
1149 r->start = p->start;
1151 r->flags = IORESOURCE_MEM;
1152 r->parent = r->sibling = r->child = NULL;
1156 /* MMIO space > 4GB phys addr; for 64-bit BAR */
1157 sprintf(lba_dev->hba.gmmio_name, "PCI%02lx GMMIO",
1158 lba_dev->hba.bus_num.start);
1159 r = &lba_dev->hba.gmmio_space;
1160 r->name = lba_dev->hba.gmmio_name;
1161 r->start = p->start;
1163 r->flags = IORESOURCE_MEM;
1164 r->parent = r->sibling = r->child = NULL;
1168 printk(KERN_WARNING MODULE_NAME
1169 " range[%d] : ignoring NPIOP (0x%lx)\n",
1175 ** Postable I/O port space is per PCI host adapter.
1176 ** base of 64MB PIOP region
1178 lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024);
1180 sprintf(lba_dev->hba.io_name, "PCI%02lx Ports",
1181 lba_dev->hba.bus_num.start);
1182 r = &lba_dev->hba.io_space;
1183 r->name = lba_dev->hba.io_name;
1184 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1185 r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
1186 r->flags = IORESOURCE_IO;
1187 r->parent = r->sibling = r->child = NULL;
1191 printk(KERN_WARNING MODULE_NAME
1192 " range[%d] : unknown pat range type (0x%lx)\n",
1199 /* keep compiler from complaining about missing declarations */
1200 #define lba_pat_port_ops lba_astro_port_ops
1201 #define lba_pat_resources(pa_dev, lba_dev)
1202 #endif /* CONFIG_64BIT */
1205 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1206 extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1210 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1215 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1218 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1219 ** represents bus->secondary and the second byte represents
1220 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1221 ** PCI bus walk *should* end up with the same result.
1222 ** FIXME: But we don't have sanity checks in PCI or LBA.
1224 lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
1225 r = &(lba_dev->hba.bus_num);
1226 r->name = "LBA PCI Busses";
1227 r->start = lba_num & 0xff;
1228 r->end = (lba_num>>8) & 0xff;
1230 /* Set up local PCI Bus resources - we don't need them for
1231 ** Legacy boxes but it's nice to see in /proc/iomem.
1233 r = &(lba_dev->hba.lmmio_space);
1234 sprintf(lba_dev->hba.lmmio_name, "PCI%02lx LMMIO",
1235 lba_dev->hba.bus_num.start);
1236 r->name = lba_dev->hba.lmmio_name;
1239 /* We want the CPU -> IO routing of addresses.
1240 * The SBA BASE/MASK registers control CPU -> IO routing.
1241 * Ask SBA what is routed to this rope/LBA.
1243 sba_distributed_lmmio(pa_dev, r);
1246 * The LBA BASE/MASK registers control IO -> System routing.
1248 * The following code works but doesn't get us what we want.
1249 * Well, only because firmware (v5.0) on C3000 doesn't program
1250 * the LBA BASE/MASE registers to be the exact inverse of
1251 * the corresponding SBA registers. Other Astro/Pluto
1252 * based platform firmware may do it right.
1254 * Should someone want to mess with MSI, they may need to
1255 * reprogram LBA BASE/MASK registers. Thus preserve the code
1256 * below until MSI is known to work on C3000/A500/N4000/RP3440.
1258 * Using the code below, /proc/iomem shows:
1260 * f0000000-f0ffffff : PCI00 LMMIO
1261 * f05d0000-f05d0000 : lcd_data
1262 * f05d0008-f05d0008 : lcd_cmd
1263 * f1000000-f1ffffff : PCI01 LMMIO
1264 * f4000000-f4ffffff : PCI02 LMMIO
1265 * f4000000-f4001fff : sym53c8xx
1266 * f4002000-f4003fff : sym53c8xx
1267 * f4004000-f40043ff : sym53c8xx
1268 * f4005000-f40053ff : sym53c8xx
1269 * f4007000-f4007fff : ohci_hcd
1270 * f4008000-f40083ff : tulip
1271 * f6000000-f6ffffff : PCI03 LMMIO
1272 * f8000000-fbffffff : PCI00 ELMMIO
1273 * fa100000-fa4fffff : stifb mmio
1274 * fb000000-fb1fffff : stifb fb
1276 * But everything listed under PCI02 actually lives under PCI00.
1277 * This is clearly wrong.
1279 * Asking SBA how things are routed tells the correct story:
1280 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1281 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1282 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1283 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1284 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1286 * Which looks like this in /proc/iomem:
1287 * f4000000-f47fffff : PCI00 LMMIO
1288 * f4000000-f4001fff : sym53c8xx
1289 * ...[deteled core devices - same as above]...
1290 * f4008000-f40083ff : tulip
1291 * f4800000-f4ffffff : PCI01 LMMIO
1292 * f6000000-f67fffff : PCI02 LMMIO
1293 * f7000000-f77fffff : PCI03 LMMIO
1294 * f9000000-f9ffffff : PCI02 ELMMIO
1295 * fa000000-fbffffff : PCI03 ELMMIO
1296 * fa100000-fa4fffff : stifb mmio
1297 * fb000000-fb1fffff : stifb fb
1299 * ie all Built-in core are under now correctly under PCI00.
1300 * The "PCI02 ELMMIO" directed range is for:
1301 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
1305 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
1307 unsigned long rsize;
1309 r->flags = IORESOURCE_MEM;
1310 /* mmio_mask also clears Enable bit */
1311 r->start &= mmio_mask;
1312 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1313 rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
1316 ** Each rope only gets part of the distributed range.
1317 ** Adjust "window" for this rope.
1319 rsize /= ROPES_PER_IOC;
1320 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
1321 r->end = r->start + rsize;
1323 r->end = r->start = 0; /* Not enabled. */
1328 ** "Directed" ranges are used when the "distributed range" isn't
1329 ** sufficient for all devices below a given LBA. Typically devices
1330 ** like graphics cards or X25 may need a directed range when the
1331 ** bus has multiple slots (ie multiple devices) or the device
1332 ** needs more than the typical 4 or 8MB a distributed range offers.
1334 ** The main reason for ignoring it now frigging complications.
1335 ** Directed ranges may overlap (and have precedence) over
1336 ** distributed ranges. Or a distributed range assigned to a unused
1337 ** rope may be used by a directed range on a different rope.
1338 ** Support for graphics devices may require fixing this
1339 ** since they may be assigned a directed range which overlaps
1340 ** an existing (but unused portion of) distributed range.
1342 r = &(lba_dev->hba.elmmio_space);
1343 sprintf(lba_dev->hba.elmmio_name, "PCI%02lx ELMMIO",
1344 lba_dev->hba.bus_num.start);
1345 r->name = lba_dev->hba.elmmio_name;
1348 /* See comment which precedes call to sba_directed_lmmio() */
1349 sba_directed_lmmio(pa_dev, r);
1351 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
1354 unsigned long rsize;
1355 r->flags = IORESOURCE_MEM;
1356 /* mmio_mask also clears Enable bit */
1357 r->start &= mmio_mask;
1358 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1359 rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
1360 r->end = r->start + ~rsize;
1364 r = &(lba_dev->hba.io_space);
1365 sprintf(lba_dev->hba.io_name, "PCI%02lx Ports",
1366 lba_dev->hba.bus_num.start);
1367 r->name = lba_dev->hba.io_name;
1368 r->flags = IORESOURCE_IO;
1369 r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
1370 r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1372 /* Virtualize the I/O Port space ranges */
1373 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1374 r->start |= lba_num;
1379 /**************************************************************************
1381 ** LBA initialization code (HW and SW)
1383 ** o identify LBA chip itself
1384 ** o initialize LBA chip modes (HardFail)
1385 ** o FIXME: initialize DMA hints for reasonable defaults
1386 ** o enable configuration functions
1387 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1389 **************************************************************************/
1392 lba_hw_init(struct lba_device *d)
1395 u32 bus_reset; /* PDC_PAT_BUG */
1398 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1400 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1401 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1402 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1403 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1404 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1405 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1406 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1407 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1408 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1409 printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1410 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1411 printk(KERN_DEBUG " HINT reg ");
1413 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1414 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1417 #endif /* DEBUG_LBA_PAT */
1421 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1422 * Only N-Class and up can really make use of Get slot status.
1423 * maybe L-class too but I've never played with it there.
1427 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1428 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1430 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1433 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1434 if (stat & LBA_SMART_MODE) {
1435 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1436 stat &= ~LBA_SMART_MODE;
1437 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1440 /* Set HF mode as the default (vs. -1 mode). */
1441 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1442 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1445 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1446 ** if it's not already set. If we just cleared the PCI Bus Reset
1447 ** signal, wait a bit for the PCI devices to recover and setup.
1450 mdelay(pci_post_reset_delay);
1452 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1454 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1455 ** B2000/C3600/J6000 also have this problem?
1457 ** Elroys with hot pluggable slots don't get configured
1458 ** correctly if the slot is empty. ARB_MASK is set to 0
1459 ** and we can't master transactions on the bus if it's
1460 ** not at least one. 0x3 enables elroy and first slot.
1462 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1463 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1467 ** FIXME: Hint registers are programmed with default hint
1468 ** values by firmware. Hints should be sane even if we
1469 ** can't reprogram them the way drivers want.
1477 ** Determine if lba should claim this chip (return 0) or not (return 1).
1478 ** If so, initialize the chip and tell other partners in crime they
1482 lba_driver_probe(struct parisc_device *dev)
1484 struct lba_device *lba_dev;
1485 struct pci_bus *lba_bus;
1486 struct pci_ops *cfg_ops;
1490 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
1492 /* Read HW Rev First */
1493 func_class = READ_REG32(addr + LBA_FCLASS);
1495 if (IS_ELROY(dev)) {
1497 switch (func_class) {
1498 case 0: version = "TR1.0"; break;
1499 case 1: version = "TR2.0"; break;
1500 case 2: version = "TR2.1"; break;
1501 case 3: version = "TR2.2"; break;
1502 case 4: version = "TR3.0"; break;
1503 case 5: version = "TR4.0"; break;
1504 default: version = "TR4+";
1507 printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
1508 version, func_class & 0xf, dev->hpa.start);
1510 if (func_class < 2) {
1511 printk(KERN_WARNING "Can't support LBA older than "
1512 "TR2.1 - continuing under adversity.\n");
1516 /* Elroy TR4.0 should work with simple algorithm.
1517 But it doesn't. Still missing something. *sigh*
1519 if (func_class > 4) {
1520 cfg_ops = &mercury_cfg_ops;
1524 cfg_ops = &elroy_cfg_ops;
1527 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1531 major = func_class >> 4, minor = func_class & 0xf;
1533 /* We could use one printk for both Elroy and Mercury,
1534 * but for the mask for func_class.
1536 printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
1537 IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
1538 minor, func_class, dev->hpa.start);
1540 cfg_ops = &mercury_cfg_ops;
1542 printk(KERN_ERR "Unknown LBA found at 0x%lx\n", dev->hpa.start);
1547 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1549 tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
1551 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1552 ** have an IRT entry will get NULL back from iosapic code.
1555 lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
1557 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1562 /* ---------- First : initialize data we already have --------- */
1564 lba_dev->hw_rev = func_class;
1565 lba_dev->hba.base_addr = addr;
1566 lba_dev->hba.dev = dev;
1567 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
1568 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
1569 parisc_set_drvdata(dev, lba_dev);
1571 /* ------------ Second : initialize common stuff ---------- */
1572 pci_bios = &lba_bios_ops;
1573 pcibios_register_hba(HBA_DATA(lba_dev));
1574 spin_lock_init(&lba_dev->lba_lock);
1576 if (lba_hw_init(lba_dev))
1579 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1582 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1583 pci_port = &lba_pat_port_ops;
1584 /* Go ask PDC PAT what resources this LBA has */
1585 lba_pat_resources(dev, lba_dev);
1587 if (!astro_iop_base) {
1588 /* Sprockets PDC uses NPIOP region */
1589 astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024);
1590 pci_port = &lba_astro_port_ops;
1593 /* Poke the chip a bit for /proc output */
1594 lba_legacy_resources(dev, lba_dev);
1598 ** Tell PCI support another PCI bus was found.
1599 ** Walks PCI bus for us too.
1601 dev->dev.platform_data = lba_dev;
1602 lba_bus = lba_dev->hba.hba_bus =
1603 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1606 pci_bus_add_devices(lba_bus);
1608 /* This is in lieu of calling pci_assign_unassigned_resources() */
1610 /* assign resources to un-initialized devices */
1612 DBG_PAT("LBA pci_bus_size_bridges()\n");
1613 pci_bus_size_bridges(lba_bus);
1615 DBG_PAT("LBA pci_bus_assign_resources()\n");
1616 pci_bus_assign_resources(lba_bus);
1618 #ifdef DEBUG_LBA_PAT
1619 DBG_PAT("\nLBA PIOP resource tree\n");
1620 lba_dump_res(&lba_dev->hba.io_space, 2);
1621 DBG_PAT("\nLBA LMMIO resource tree\n");
1622 lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1625 pci_enable_bridges(lba_bus);
1629 ** Once PCI register ops has walked the bus, access to config
1630 ** space is restricted. Avoids master aborts on config cycles.
1631 ** Early LBA revs go fatal on *any* master abort.
1633 if (cfg_ops == &elroy_cfg_ops) {
1634 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1637 /* Whew! Finally done! Tell services we got this one covered. */
1641 static struct parisc_device_id lba_tbl[] = {
1642 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1643 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1644 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1648 static struct parisc_driver lba_driver = {
1649 .name = MODULE_NAME,
1650 .id_table = lba_tbl,
1651 .probe = lba_driver_probe,
1655 ** One time initialization to let the world know the LBA was found.
1656 ** Must be called exactly once before pci_init().
1658 void __init lba_init(void)
1660 register_parisc_driver(&lba_driver);
1664 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1665 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1666 ** sba_iommu is responsible for locking (none needed at init time).
1668 void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1670 void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096);
1672 imask <<= 2; /* adjust for hints - 2 more bits */
1674 /* Make sure we aren't trying to set bits that aren't writeable. */
1675 WARN_ON((ibase & 0x001fffff) != 0);
1676 WARN_ON((imask & 0x001fffff) != 0);
1678 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1679 WRITE_REG32( imask, base_addr + LBA_IMASK);
1680 WRITE_REG32( ibase, base_addr + LBA_IBASE);