1 #include <linux/delay.h>
3 #include <linux/module.h>
4 #include <linux/sched.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
16 DEFINE_RAW_SPINLOCK(pci_lock);
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
28 #define PCI_OP_READ(size, type, len) \
29 int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
33 unsigned long flags; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
43 #define PCI_OP_WRITE(size, type, len) \
44 int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
56 PCI_OP_READ(byte, u8, 1)
57 PCI_OP_READ(word, u16, 2)
58 PCI_OP_READ(dword, u32, 4)
59 PCI_OP_WRITE(byte, u8, 1)
60 PCI_OP_WRITE(word, u16, 2)
61 PCI_OP_WRITE(dword, u32, 4)
63 EXPORT_SYMBOL(pci_bus_read_config_byte);
64 EXPORT_SYMBOL(pci_bus_read_config_word);
65 EXPORT_SYMBOL(pci_bus_read_config_dword);
66 EXPORT_SYMBOL(pci_bus_write_config_byte);
67 EXPORT_SYMBOL(pci_bus_write_config_word);
68 EXPORT_SYMBOL(pci_bus_write_config_dword);
70 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
71 int where, int size, u32 *val)
75 addr = bus->ops->map_bus(bus, devfn, where);
78 return PCIBIOS_DEVICE_NOT_FOUND;
88 return PCIBIOS_SUCCESSFUL;
90 EXPORT_SYMBOL_GPL(pci_generic_config_read);
92 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 val)
97 addr = bus->ops->map_bus(bus, devfn, where);
99 return PCIBIOS_DEVICE_NOT_FOUND;
108 return PCIBIOS_SUCCESSFUL;
110 EXPORT_SYMBOL_GPL(pci_generic_config_write);
112 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
113 int where, int size, u32 *val)
117 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
120 return PCIBIOS_DEVICE_NOT_FOUND;
126 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
128 return PCIBIOS_SUCCESSFUL;
130 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
132 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
133 int where, int size, u32 val)
138 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
140 return PCIBIOS_DEVICE_NOT_FOUND;
144 return PCIBIOS_SUCCESSFUL;
146 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
149 tmp = readl(addr) & mask;
150 tmp |= val << ((where & 0x3) * 8);
153 return PCIBIOS_SUCCESSFUL;
155 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
158 * pci_bus_set_ops - Set raw operations of pci bus
159 * @bus: pci bus struct
160 * @ops: new raw operations
162 * Return previous raw operations
164 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
166 struct pci_ops *old_ops;
169 raw_spin_lock_irqsave(&pci_lock, flags);
172 raw_spin_unlock_irqrestore(&pci_lock, flags);
175 EXPORT_SYMBOL(pci_bus_set_ops);
178 * The following routines are to prevent the user from accessing PCI config
179 * space when it's unsafe to do so. Some devices require this during BIST and
180 * we're required to prevent it during D-state transitions.
182 * We have a bit per device to indicate it's blocked and a global wait queue
183 * for callers to sleep on until devices are unblocked.
185 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
187 static noinline void pci_wait_cfg(struct pci_dev *dev)
189 DECLARE_WAITQUEUE(wait, current);
191 __add_wait_queue(&pci_cfg_wait, &wait);
193 set_current_state(TASK_UNINTERRUPTIBLE);
194 raw_spin_unlock_irq(&pci_lock);
196 raw_spin_lock_irq(&pci_lock);
197 } while (dev->block_cfg_access);
198 __remove_wait_queue(&pci_cfg_wait, &wait);
201 /* Returns 0 on success, negative values indicate error. */
202 #define PCI_USER_READ_CONFIG(size, type) \
203 int pci_user_read_config_##size \
204 (struct pci_dev *dev, int pos, type *val) \
206 int ret = PCIBIOS_SUCCESSFUL; \
208 if (PCI_##size##_BAD) \
210 raw_spin_lock_irq(&pci_lock); \
211 if (unlikely(dev->block_cfg_access)) \
213 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
214 pos, sizeof(type), &data); \
215 raw_spin_unlock_irq(&pci_lock); \
217 return pcibios_err_to_errno(ret); \
219 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
221 /* Returns 0 on success, negative values indicate error. */
222 #define PCI_USER_WRITE_CONFIG(size, type) \
223 int pci_user_write_config_##size \
224 (struct pci_dev *dev, int pos, type val) \
226 int ret = PCIBIOS_SUCCESSFUL; \
227 if (PCI_##size##_BAD) \
229 raw_spin_lock_irq(&pci_lock); \
230 if (unlikely(dev->block_cfg_access)) \
232 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
233 pos, sizeof(type), val); \
234 raw_spin_unlock_irq(&pci_lock); \
235 return pcibios_err_to_errno(ret); \
237 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
239 PCI_USER_READ_CONFIG(byte, u8)
240 PCI_USER_READ_CONFIG(word, u16)
241 PCI_USER_READ_CONFIG(dword, u32)
242 PCI_USER_WRITE_CONFIG(byte, u8)
243 PCI_USER_WRITE_CONFIG(word, u16)
244 PCI_USER_WRITE_CONFIG(dword, u32)
246 /* VPD access through PCI 2.2+ VPD capability */
249 * pci_read_vpd - Read one entry from Vital Product Data
250 * @dev: pci device struct
251 * @pos: offset in vpd space
252 * @count: number of bytes to read
253 * @buf: pointer to where to store result
255 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
257 if (!dev->vpd || !dev->vpd->ops)
259 return dev->vpd->ops->read(dev, pos, count, buf);
261 EXPORT_SYMBOL(pci_read_vpd);
264 * pci_write_vpd - Write entry to Vital Product Data
265 * @dev: pci device struct
266 * @pos: offset in vpd space
267 * @count: number of bytes to write
268 * @buf: buffer containing write data
270 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
272 if (!dev->vpd || !dev->vpd->ops)
274 return dev->vpd->ops->write(dev, pos, count, buf);
276 EXPORT_SYMBOL(pci_write_vpd);
279 * pci_set_vpd_size - Set size of Vital Product Data space
280 * @dev: pci device struct
281 * @len: size of vpd space
283 int pci_set_vpd_size(struct pci_dev *dev, size_t len)
285 if (!dev->vpd || !dev->vpd->ops)
287 return dev->vpd->ops->set_size(dev, len);
289 EXPORT_SYMBOL(pci_set_vpd_size);
291 #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
294 * pci_vpd_size - determine actual size of Vital Product Data
295 * @dev: pci device struct
296 * @old_size: current assumed size, also maximum allowed size
298 static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
301 unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
303 while (off < old_size &&
304 pci_read_vpd(dev, off, 1, header) == 1) {
307 if (header[0] & PCI_VPD_LRDT) {
308 /* Large Resource Data Type Tag */
309 tag = pci_vpd_lrdt_tag(header);
310 /* Only read length from known tag items */
311 if ((tag == PCI_VPD_LTIN_ID_STRING) ||
312 (tag == PCI_VPD_LTIN_RO_DATA) ||
313 (tag == PCI_VPD_LTIN_RW_DATA)) {
314 if (pci_read_vpd(dev, off+1, 2,
317 "invalid large VPD tag %02x size at offset %zu",
321 off += PCI_VPD_LRDT_TAG_SIZE +
322 pci_vpd_lrdt_size(header);
325 /* Short Resource Data Type Tag */
326 off += PCI_VPD_SRDT_TAG_SIZE +
327 pci_vpd_srdt_size(header);
328 tag = pci_vpd_srdt_tag(header);
331 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
334 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
335 (tag != PCI_VPD_LTIN_RO_DATA) &&
336 (tag != PCI_VPD_LTIN_RW_DATA)) {
338 "invalid %s VPD tag %02x at offset %zu",
339 (header[0] & PCI_VPD_LRDT) ? "large" : "short",
348 * Wait for last operation to complete.
349 * This code has to spin since there is no other notification from the PCI
350 * hardware. Since the VPD is often implemented by serial attachment to an
351 * EEPROM, it may take many milliseconds to complete.
353 * Returns 0 on success, negative values indicate error.
355 static int pci_vpd_wait(struct pci_dev *dev)
357 struct pci_vpd *vpd = dev->vpd;
358 unsigned long timeout = jiffies + msecs_to_jiffies(50);
359 unsigned long max_sleep = 16;
366 while (time_before(jiffies, timeout)) {
367 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
372 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
377 if (fatal_signal_pending(current))
380 usleep_range(10, max_sleep);
381 if (max_sleep < 1024)
385 dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
389 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
392 struct pci_vpd *vpd = dev->vpd;
394 loff_t end = pos + count;
402 vpd->len = pci_vpd_size(dev, vpd->len);
411 if (end > vpd->len) {
416 if (mutex_lock_killable(&vpd->lock))
419 ret = pci_vpd_wait(dev);
425 unsigned int i, skip;
427 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
432 vpd->flag = PCI_VPD_ADDR_F;
433 ret = pci_vpd_wait(dev);
437 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
442 for (i = 0; i < sizeof(u32); i++) {
452 mutex_unlock(&vpd->lock);
453 return ret ? ret : count;
456 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
459 struct pci_vpd *vpd = dev->vpd;
461 loff_t end = pos + count;
464 if (pos < 0 || (pos & 3) || (count & 3))
469 vpd->len = pci_vpd_size(dev, vpd->len);
478 if (mutex_lock_killable(&vpd->lock))
481 ret = pci_vpd_wait(dev);
493 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
496 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
497 pos | PCI_VPD_ADDR_F);
503 ret = pci_vpd_wait(dev);
510 mutex_unlock(&vpd->lock);
511 return ret ? ret : count;
514 static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
516 struct pci_vpd *vpd = dev->vpd;
518 if (len == 0 || len > PCI_VPD_MAX_SIZE)
527 static const struct pci_vpd_ops pci_vpd_ops = {
528 .read = pci_vpd_read,
529 .write = pci_vpd_write,
530 .set_size = pci_vpd_set_size,
533 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
536 struct pci_dev *tdev = pci_get_slot(dev->bus,
537 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
543 ret = pci_read_vpd(tdev, pos, count, arg);
548 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
551 struct pci_dev *tdev = pci_get_slot(dev->bus,
552 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
558 ret = pci_write_vpd(tdev, pos, count, arg);
563 static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
565 struct pci_dev *tdev = pci_get_slot(dev->bus,
566 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
572 ret = pci_set_vpd_size(tdev, len);
577 static const struct pci_vpd_ops pci_vpd_f0_ops = {
578 .read = pci_vpd_f0_read,
579 .write = pci_vpd_f0_write,
580 .set_size = pci_vpd_f0_set_size,
583 int pci_vpd_init(struct pci_dev *dev)
588 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
592 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
596 vpd->len = PCI_VPD_MAX_SIZE;
597 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
598 vpd->ops = &pci_vpd_f0_ops;
600 vpd->ops = &pci_vpd_ops;
601 mutex_init(&vpd->lock);
609 void pci_vpd_release(struct pci_dev *dev)
615 * pci_cfg_access_lock - Lock PCI config reads/writes
616 * @dev: pci device struct
618 * When access is locked, any userspace reads or writes to config
619 * space and concurrent lock requests will sleep until access is
620 * allowed via pci_cfg_access_unlocked again.
622 void pci_cfg_access_lock(struct pci_dev *dev)
626 raw_spin_lock_irq(&pci_lock);
627 if (dev->block_cfg_access)
629 dev->block_cfg_access = 1;
630 raw_spin_unlock_irq(&pci_lock);
632 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
635 * pci_cfg_access_trylock - try to lock PCI config reads/writes
636 * @dev: pci device struct
638 * Same as pci_cfg_access_lock, but will return 0 if access is
639 * already locked, 1 otherwise. This function can be used from
642 bool pci_cfg_access_trylock(struct pci_dev *dev)
647 raw_spin_lock_irqsave(&pci_lock, flags);
648 if (dev->block_cfg_access)
651 dev->block_cfg_access = 1;
652 raw_spin_unlock_irqrestore(&pci_lock, flags);
656 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
659 * pci_cfg_access_unlock - Unlock PCI config reads/writes
660 * @dev: pci device struct
662 * This function allows PCI config accesses to resume.
664 void pci_cfg_access_unlock(struct pci_dev *dev)
668 raw_spin_lock_irqsave(&pci_lock, flags);
670 /* This indicates a problem in the caller, but we don't need
671 * to kill them, unlike a double-block above. */
672 WARN_ON(!dev->block_cfg_access);
674 dev->block_cfg_access = 0;
675 wake_up_all(&pci_cfg_wait);
676 raw_spin_unlock_irqrestore(&pci_lock, flags);
678 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
680 static inline int pcie_cap_version(const struct pci_dev *dev)
682 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
685 static bool pcie_downstream_port(const struct pci_dev *dev)
687 int type = pci_pcie_type(dev);
689 return type == PCI_EXP_TYPE_ROOT_PORT ||
690 type == PCI_EXP_TYPE_DOWNSTREAM;
693 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
695 int type = pci_pcie_type(dev);
697 return type == PCI_EXP_TYPE_ENDPOINT ||
698 type == PCI_EXP_TYPE_LEG_END ||
699 type == PCI_EXP_TYPE_ROOT_PORT ||
700 type == PCI_EXP_TYPE_UPSTREAM ||
701 type == PCI_EXP_TYPE_DOWNSTREAM ||
702 type == PCI_EXP_TYPE_PCI_BRIDGE ||
703 type == PCI_EXP_TYPE_PCIE_BRIDGE;
706 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
708 return pcie_downstream_port(dev) &&
709 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
712 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
714 int type = pci_pcie_type(dev);
716 return type == PCI_EXP_TYPE_ROOT_PORT ||
717 type == PCI_EXP_TYPE_RC_EC;
720 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
722 if (!pci_is_pcie(dev))
735 return pcie_cap_has_lnkctl(dev);
739 return pcie_cap_has_sltctl(dev);
743 return pcie_cap_has_rtctl(dev);
744 case PCI_EXP_DEVCAP2:
745 case PCI_EXP_DEVCTL2:
746 case PCI_EXP_LNKCAP2:
747 case PCI_EXP_LNKCTL2:
748 case PCI_EXP_LNKSTA2:
749 return pcie_cap_version(dev) > 1;
756 * Note that these accessor functions are only for the "PCI Express
757 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
758 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
760 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
768 if (pcie_capability_reg_implemented(dev, pos)) {
769 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
771 * Reset *val to 0 if pci_read_config_word() fails, it may
772 * have been written as 0xFFFF if hardware error happens
773 * during pci_read_config_word().
781 * For Functions that do not implement the Slot Capabilities,
782 * Slot Status, and Slot Control registers, these spaces must
783 * be hardwired to 0b, with the exception of the Presence Detect
784 * State bit in the Slot Status register of Downstream Ports,
785 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
787 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
788 pos == PCI_EXP_SLTSTA)
789 *val = PCI_EXP_SLTSTA_PDS;
793 EXPORT_SYMBOL(pcie_capability_read_word);
795 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
803 if (pcie_capability_reg_implemented(dev, pos)) {
804 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
806 * Reset *val to 0 if pci_read_config_dword() fails, it may
807 * have been written as 0xFFFFFFFF if hardware error happens
808 * during pci_read_config_dword().
815 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
816 pos == PCI_EXP_SLTSTA)
817 *val = PCI_EXP_SLTSTA_PDS;
821 EXPORT_SYMBOL(pcie_capability_read_dword);
823 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
828 if (!pcie_capability_reg_implemented(dev, pos))
831 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
833 EXPORT_SYMBOL(pcie_capability_write_word);
835 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
840 if (!pcie_capability_reg_implemented(dev, pos))
843 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
845 EXPORT_SYMBOL(pcie_capability_write_dword);
847 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
853 ret = pcie_capability_read_word(dev, pos, &val);
857 ret = pcie_capability_write_word(dev, pos, val);
862 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
864 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
870 ret = pcie_capability_read_dword(dev, pos, &val);
874 ret = pcie_capability_write_dword(dev, pos, val);
879 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);