1 #include <linux/delay.h>
3 #include <linux/module.h>
4 #include <linux/sched.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
16 DEFINE_RAW_SPINLOCK(pci_lock);
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
28 #define PCI_OP_READ(size, type, len) \
29 int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
33 unsigned long flags; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
43 #define PCI_OP_WRITE(size, type, len) \
44 int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
56 PCI_OP_READ(byte, u8, 1)
57 PCI_OP_READ(word, u16, 2)
58 PCI_OP_READ(dword, u32, 4)
59 PCI_OP_WRITE(byte, u8, 1)
60 PCI_OP_WRITE(word, u16, 2)
61 PCI_OP_WRITE(dword, u32, 4)
63 EXPORT_SYMBOL(pci_bus_read_config_byte);
64 EXPORT_SYMBOL(pci_bus_read_config_word);
65 EXPORT_SYMBOL(pci_bus_read_config_dword);
66 EXPORT_SYMBOL(pci_bus_write_config_byte);
67 EXPORT_SYMBOL(pci_bus_write_config_word);
68 EXPORT_SYMBOL(pci_bus_write_config_dword);
70 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
71 int where, int size, u32 *val)
75 addr = bus->ops->map_bus(bus, devfn, where);
78 return PCIBIOS_DEVICE_NOT_FOUND;
88 return PCIBIOS_SUCCESSFUL;
90 EXPORT_SYMBOL_GPL(pci_generic_config_read);
92 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 val)
97 addr = bus->ops->map_bus(bus, devfn, where);
99 return PCIBIOS_DEVICE_NOT_FOUND;
108 return PCIBIOS_SUCCESSFUL;
110 EXPORT_SYMBOL_GPL(pci_generic_config_write);
112 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
113 int where, int size, u32 *val)
117 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
120 return PCIBIOS_DEVICE_NOT_FOUND;
126 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
128 return PCIBIOS_SUCCESSFUL;
130 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
132 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
133 int where, int size, u32 val)
138 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
140 return PCIBIOS_DEVICE_NOT_FOUND;
144 return PCIBIOS_SUCCESSFUL;
148 * In general, hardware that supports only 32-bit writes on PCI is
149 * not spec-compliant. For example, software may perform a 16-bit
150 * write. If the hardware only supports 32-bit accesses, we must
151 * do a 32-bit read, merge in the 16 bits we intend to write,
152 * followed by a 32-bit write. If the 16 bits we *don't* intend to
153 * write happen to have any RW1C (write-one-to-clear) bits set, we
154 * just inadvertently cleared something we shouldn't have.
156 dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
157 size, pci_domain_nr(bus), bus->number,
158 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
160 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
161 tmp = readl(addr) & mask;
162 tmp |= val << ((where & 0x3) * 8);
165 return PCIBIOS_SUCCESSFUL;
167 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
170 * pci_bus_set_ops - Set raw operations of pci bus
171 * @bus: pci bus struct
172 * @ops: new raw operations
174 * Return previous raw operations
176 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
178 struct pci_ops *old_ops;
181 raw_spin_lock_irqsave(&pci_lock, flags);
184 raw_spin_unlock_irqrestore(&pci_lock, flags);
187 EXPORT_SYMBOL(pci_bus_set_ops);
190 * The following routines are to prevent the user from accessing PCI config
191 * space when it's unsafe to do so. Some devices require this during BIST and
192 * we're required to prevent it during D-state transitions.
194 * We have a bit per device to indicate it's blocked and a global wait queue
195 * for callers to sleep on until devices are unblocked.
197 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
199 static noinline void pci_wait_cfg(struct pci_dev *dev)
201 DECLARE_WAITQUEUE(wait, current);
203 __add_wait_queue(&pci_cfg_wait, &wait);
205 set_current_state(TASK_UNINTERRUPTIBLE);
206 raw_spin_unlock_irq(&pci_lock);
208 raw_spin_lock_irq(&pci_lock);
209 } while (dev->block_cfg_access);
210 __remove_wait_queue(&pci_cfg_wait, &wait);
213 /* Returns 0 on success, negative values indicate error. */
214 #define PCI_USER_READ_CONFIG(size, type) \
215 int pci_user_read_config_##size \
216 (struct pci_dev *dev, int pos, type *val) \
218 int ret = PCIBIOS_SUCCESSFUL; \
220 if (PCI_##size##_BAD) \
222 raw_spin_lock_irq(&pci_lock); \
223 if (unlikely(dev->block_cfg_access)) \
225 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
226 pos, sizeof(type), &data); \
227 raw_spin_unlock_irq(&pci_lock); \
229 return pcibios_err_to_errno(ret); \
231 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
233 /* Returns 0 on success, negative values indicate error. */
234 #define PCI_USER_WRITE_CONFIG(size, type) \
235 int pci_user_write_config_##size \
236 (struct pci_dev *dev, int pos, type val) \
238 int ret = PCIBIOS_SUCCESSFUL; \
239 if (PCI_##size##_BAD) \
241 raw_spin_lock_irq(&pci_lock); \
242 if (unlikely(dev->block_cfg_access)) \
244 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
245 pos, sizeof(type), val); \
246 raw_spin_unlock_irq(&pci_lock); \
247 return pcibios_err_to_errno(ret); \
249 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
251 PCI_USER_READ_CONFIG(byte, u8)
252 PCI_USER_READ_CONFIG(word, u16)
253 PCI_USER_READ_CONFIG(dword, u32)
254 PCI_USER_WRITE_CONFIG(byte, u8)
255 PCI_USER_WRITE_CONFIG(word, u16)
256 PCI_USER_WRITE_CONFIG(dword, u32)
258 /* VPD access through PCI 2.2+ VPD capability */
261 * pci_read_vpd - Read one entry from Vital Product Data
262 * @dev: pci device struct
263 * @pos: offset in vpd space
264 * @count: number of bytes to read
265 * @buf: pointer to where to store result
267 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
269 if (!dev->vpd || !dev->vpd->ops)
271 return dev->vpd->ops->read(dev, pos, count, buf);
273 EXPORT_SYMBOL(pci_read_vpd);
276 * pci_write_vpd - Write entry to Vital Product Data
277 * @dev: pci device struct
278 * @pos: offset in vpd space
279 * @count: number of bytes to write
280 * @buf: buffer containing write data
282 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
284 if (!dev->vpd || !dev->vpd->ops)
286 return dev->vpd->ops->write(dev, pos, count, buf);
288 EXPORT_SYMBOL(pci_write_vpd);
291 * pci_set_vpd_size - Set size of Vital Product Data space
292 * @dev: pci device struct
293 * @len: size of vpd space
295 int pci_set_vpd_size(struct pci_dev *dev, size_t len)
297 if (!dev->vpd || !dev->vpd->ops)
299 return dev->vpd->ops->set_size(dev, len);
301 EXPORT_SYMBOL(pci_set_vpd_size);
303 #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
306 * pci_vpd_size - determine actual size of Vital Product Data
307 * @dev: pci device struct
308 * @old_size: current assumed size, also maximum allowed size
310 static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
313 unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
315 while (off < old_size &&
316 pci_read_vpd(dev, off, 1, header) == 1) {
319 if (header[0] & PCI_VPD_LRDT) {
320 /* Large Resource Data Type Tag */
321 tag = pci_vpd_lrdt_tag(header);
322 /* Only read length from known tag items */
323 if ((tag == PCI_VPD_LTIN_ID_STRING) ||
324 (tag == PCI_VPD_LTIN_RO_DATA) ||
325 (tag == PCI_VPD_LTIN_RW_DATA)) {
326 if (pci_read_vpd(dev, off+1, 2,
329 "invalid large VPD tag %02x size at offset %zu",
333 off += PCI_VPD_LRDT_TAG_SIZE +
334 pci_vpd_lrdt_size(header);
337 /* Short Resource Data Type Tag */
338 off += PCI_VPD_SRDT_TAG_SIZE +
339 pci_vpd_srdt_size(header);
340 tag = pci_vpd_srdt_tag(header);
343 if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
346 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
347 (tag != PCI_VPD_LTIN_RO_DATA) &&
348 (tag != PCI_VPD_LTIN_RW_DATA)) {
350 "invalid %s VPD tag %02x at offset %zu",
351 (header[0] & PCI_VPD_LRDT) ? "large" : "short",
360 * Wait for last operation to complete.
361 * This code has to spin since there is no other notification from the PCI
362 * hardware. Since the VPD is often implemented by serial attachment to an
363 * EEPROM, it may take many milliseconds to complete.
365 * Returns 0 on success, negative values indicate error.
367 static int pci_vpd_wait(struct pci_dev *dev)
369 struct pci_vpd *vpd = dev->vpd;
370 unsigned long timeout = jiffies + msecs_to_jiffies(50);
371 unsigned long max_sleep = 16;
378 while (time_before(jiffies, timeout)) {
379 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
384 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
389 if (fatal_signal_pending(current))
392 usleep_range(10, max_sleep);
393 if (max_sleep < 1024)
397 dev_warn(&dev->dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
401 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
404 struct pci_vpd *vpd = dev->vpd;
406 loff_t end = pos + count;
414 vpd->len = pci_vpd_size(dev, vpd->len);
423 if (end > vpd->len) {
428 if (mutex_lock_killable(&vpd->lock))
431 ret = pci_vpd_wait(dev);
437 unsigned int i, skip;
439 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
444 vpd->flag = PCI_VPD_ADDR_F;
445 ret = pci_vpd_wait(dev);
449 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
454 for (i = 0; i < sizeof(u32); i++) {
464 mutex_unlock(&vpd->lock);
465 return ret ? ret : count;
468 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
471 struct pci_vpd *vpd = dev->vpd;
473 loff_t end = pos + count;
476 if (pos < 0 || (pos & 3) || (count & 3))
481 vpd->len = pci_vpd_size(dev, vpd->len);
490 if (mutex_lock_killable(&vpd->lock))
493 ret = pci_vpd_wait(dev);
505 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
508 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
509 pos | PCI_VPD_ADDR_F);
515 ret = pci_vpd_wait(dev);
522 mutex_unlock(&vpd->lock);
523 return ret ? ret : count;
526 static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
528 struct pci_vpd *vpd = dev->vpd;
530 if (len == 0 || len > PCI_VPD_MAX_SIZE)
539 static const struct pci_vpd_ops pci_vpd_ops = {
540 .read = pci_vpd_read,
541 .write = pci_vpd_write,
542 .set_size = pci_vpd_set_size,
545 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
548 struct pci_dev *tdev = pci_get_slot(dev->bus,
549 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
555 ret = pci_read_vpd(tdev, pos, count, arg);
560 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
563 struct pci_dev *tdev = pci_get_slot(dev->bus,
564 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
570 ret = pci_write_vpd(tdev, pos, count, arg);
575 static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
577 struct pci_dev *tdev = pci_get_slot(dev->bus,
578 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
584 ret = pci_set_vpd_size(tdev, len);
589 static const struct pci_vpd_ops pci_vpd_f0_ops = {
590 .read = pci_vpd_f0_read,
591 .write = pci_vpd_f0_write,
592 .set_size = pci_vpd_f0_set_size,
595 int pci_vpd_init(struct pci_dev *dev)
600 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
604 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
608 vpd->len = PCI_VPD_MAX_SIZE;
609 if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
610 vpd->ops = &pci_vpd_f0_ops;
612 vpd->ops = &pci_vpd_ops;
613 mutex_init(&vpd->lock);
621 void pci_vpd_release(struct pci_dev *dev)
627 * pci_cfg_access_lock - Lock PCI config reads/writes
628 * @dev: pci device struct
630 * When access is locked, any userspace reads or writes to config
631 * space and concurrent lock requests will sleep until access is
632 * allowed via pci_cfg_access_unlocked again.
634 void pci_cfg_access_lock(struct pci_dev *dev)
638 raw_spin_lock_irq(&pci_lock);
639 if (dev->block_cfg_access)
641 dev->block_cfg_access = 1;
642 raw_spin_unlock_irq(&pci_lock);
644 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
647 * pci_cfg_access_trylock - try to lock PCI config reads/writes
648 * @dev: pci device struct
650 * Same as pci_cfg_access_lock, but will return 0 if access is
651 * already locked, 1 otherwise. This function can be used from
654 bool pci_cfg_access_trylock(struct pci_dev *dev)
659 raw_spin_lock_irqsave(&pci_lock, flags);
660 if (dev->block_cfg_access)
663 dev->block_cfg_access = 1;
664 raw_spin_unlock_irqrestore(&pci_lock, flags);
668 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
671 * pci_cfg_access_unlock - Unlock PCI config reads/writes
672 * @dev: pci device struct
674 * This function allows PCI config accesses to resume.
676 void pci_cfg_access_unlock(struct pci_dev *dev)
680 raw_spin_lock_irqsave(&pci_lock, flags);
682 /* This indicates a problem in the caller, but we don't need
683 * to kill them, unlike a double-block above. */
684 WARN_ON(!dev->block_cfg_access);
686 dev->block_cfg_access = 0;
687 wake_up_all(&pci_cfg_wait);
688 raw_spin_unlock_irqrestore(&pci_lock, flags);
690 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
692 static inline int pcie_cap_version(const struct pci_dev *dev)
694 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
697 static bool pcie_downstream_port(const struct pci_dev *dev)
699 int type = pci_pcie_type(dev);
701 return type == PCI_EXP_TYPE_ROOT_PORT ||
702 type == PCI_EXP_TYPE_DOWNSTREAM;
705 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
707 int type = pci_pcie_type(dev);
709 return type == PCI_EXP_TYPE_ENDPOINT ||
710 type == PCI_EXP_TYPE_LEG_END ||
711 type == PCI_EXP_TYPE_ROOT_PORT ||
712 type == PCI_EXP_TYPE_UPSTREAM ||
713 type == PCI_EXP_TYPE_DOWNSTREAM ||
714 type == PCI_EXP_TYPE_PCI_BRIDGE ||
715 type == PCI_EXP_TYPE_PCIE_BRIDGE;
718 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
720 return pcie_downstream_port(dev) &&
721 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
724 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
726 int type = pci_pcie_type(dev);
728 return type == PCI_EXP_TYPE_ROOT_PORT ||
729 type == PCI_EXP_TYPE_RC_EC;
732 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
734 if (!pci_is_pcie(dev))
747 return pcie_cap_has_lnkctl(dev);
751 return pcie_cap_has_sltctl(dev);
755 return pcie_cap_has_rtctl(dev);
756 case PCI_EXP_DEVCAP2:
757 case PCI_EXP_DEVCTL2:
758 case PCI_EXP_LNKCAP2:
759 case PCI_EXP_LNKCTL2:
760 case PCI_EXP_LNKSTA2:
761 return pcie_cap_version(dev) > 1;
768 * Note that these accessor functions are only for the "PCI Express
769 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
770 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
772 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
780 if (pcie_capability_reg_implemented(dev, pos)) {
781 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
783 * Reset *val to 0 if pci_read_config_word() fails, it may
784 * have been written as 0xFFFF if hardware error happens
785 * during pci_read_config_word().
793 * For Functions that do not implement the Slot Capabilities,
794 * Slot Status, and Slot Control registers, these spaces must
795 * be hardwired to 0b, with the exception of the Presence Detect
796 * State bit in the Slot Status register of Downstream Ports,
797 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
799 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
800 pos == PCI_EXP_SLTSTA)
801 *val = PCI_EXP_SLTSTA_PDS;
805 EXPORT_SYMBOL(pcie_capability_read_word);
807 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
815 if (pcie_capability_reg_implemented(dev, pos)) {
816 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
818 * Reset *val to 0 if pci_read_config_dword() fails, it may
819 * have been written as 0xFFFFFFFF if hardware error happens
820 * during pci_read_config_dword().
827 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
828 pos == PCI_EXP_SLTSTA)
829 *val = PCI_EXP_SLTSTA_PDS;
833 EXPORT_SYMBOL(pcie_capability_read_dword);
835 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
840 if (!pcie_capability_reg_implemented(dev, pos))
843 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
845 EXPORT_SYMBOL(pcie_capability_write_word);
847 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
852 if (!pcie_capability_reg_implemented(dev, pos))
855 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
857 EXPORT_SYMBOL(pcie_capability_write_dword);
859 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
865 ret = pcie_capability_read_word(dev, pos, &val);
869 ret = pcie_capability_write_word(dev, pos, val);
874 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
876 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
882 ret = pcie_capability_read_dword(dev, pos, &val);
886 ret = pcie_capability_write_dword(dev, pos, val);
891 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);