1 #include <linux/delay.h>
3 #include <linux/module.h>
4 #include <linux/sched.h>
5 #include <linux/slab.h>
6 #include <linux/ioport.h>
7 #include <linux/wait.h>
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
16 DEFINE_RAW_SPINLOCK(pci_lock);
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
24 #define PCI_byte_BAD 0
25 #define PCI_word_BAD (pos & 1)
26 #define PCI_dword_BAD (pos & 3)
28 #define PCI_OP_READ(size,type,len) \
29 int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
33 unsigned long flags; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
43 #define PCI_OP_WRITE(size,type,len) \
44 int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
56 PCI_OP_READ(byte, u8, 1)
57 PCI_OP_READ(word, u16, 2)
58 PCI_OP_READ(dword, u32, 4)
59 PCI_OP_WRITE(byte, u8, 1)
60 PCI_OP_WRITE(word, u16, 2)
61 PCI_OP_WRITE(dword, u32, 4)
63 EXPORT_SYMBOL(pci_bus_read_config_byte);
64 EXPORT_SYMBOL(pci_bus_read_config_word);
65 EXPORT_SYMBOL(pci_bus_read_config_dword);
66 EXPORT_SYMBOL(pci_bus_write_config_byte);
67 EXPORT_SYMBOL(pci_bus_write_config_word);
68 EXPORT_SYMBOL(pci_bus_write_config_dword);
70 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
71 int where, int size, u32 *val)
75 addr = bus->ops->map_bus(bus, devfn, where);
78 return PCIBIOS_DEVICE_NOT_FOUND;
88 return PCIBIOS_SUCCESSFUL;
90 EXPORT_SYMBOL_GPL(pci_generic_config_read);
92 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 val)
97 addr = bus->ops->map_bus(bus, devfn, where);
99 return PCIBIOS_DEVICE_NOT_FOUND;
108 return PCIBIOS_SUCCESSFUL;
110 EXPORT_SYMBOL_GPL(pci_generic_config_write);
112 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
113 int where, int size, u32 *val)
117 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
120 return PCIBIOS_DEVICE_NOT_FOUND;
126 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
128 return PCIBIOS_SUCCESSFUL;
130 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
132 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
133 int where, int size, u32 val)
138 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
140 return PCIBIOS_DEVICE_NOT_FOUND;
144 return PCIBIOS_SUCCESSFUL;
146 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
149 tmp = readl(addr) & mask;
150 tmp |= val << ((where & 0x3) * 8);
153 return PCIBIOS_SUCCESSFUL;
155 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
158 * pci_bus_set_ops - Set raw operations of pci bus
159 * @bus: pci bus struct
160 * @ops: new raw operations
162 * Return previous raw operations
164 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
166 struct pci_ops *old_ops;
169 raw_spin_lock_irqsave(&pci_lock, flags);
172 raw_spin_unlock_irqrestore(&pci_lock, flags);
175 EXPORT_SYMBOL(pci_bus_set_ops);
178 * pci_read_vpd - Read one entry from Vital Product Data
179 * @dev: pci device struct
180 * @pos: offset in vpd space
181 * @count: number of bytes to read
182 * @buf: pointer to where to store result
185 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
187 if (!dev->vpd || !dev->vpd->ops)
189 return dev->vpd->ops->read(dev, pos, count, buf);
191 EXPORT_SYMBOL(pci_read_vpd);
194 * pci_write_vpd - Write entry to Vital Product Data
195 * @dev: pci device struct
196 * @pos: offset in vpd space
197 * @count: number of bytes to write
198 * @buf: buffer containing write data
201 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
203 if (!dev->vpd || !dev->vpd->ops)
205 return dev->vpd->ops->write(dev, pos, count, buf);
207 EXPORT_SYMBOL(pci_write_vpd);
210 * The following routines are to prevent the user from accessing PCI config
211 * space when it's unsafe to do so. Some devices require this during BIST and
212 * we're required to prevent it during D-state transitions.
214 * We have a bit per device to indicate it's blocked and a global wait queue
215 * for callers to sleep on until devices are unblocked.
217 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
219 static noinline void pci_wait_cfg(struct pci_dev *dev)
221 DECLARE_WAITQUEUE(wait, current);
223 __add_wait_queue(&pci_cfg_wait, &wait);
225 set_current_state(TASK_UNINTERRUPTIBLE);
226 raw_spin_unlock_irq(&pci_lock);
228 raw_spin_lock_irq(&pci_lock);
229 } while (dev->block_cfg_access);
230 __remove_wait_queue(&pci_cfg_wait, &wait);
233 /* Returns 0 on success, negative values indicate error. */
234 #define PCI_USER_READ_CONFIG(size,type) \
235 int pci_user_read_config_##size \
236 (struct pci_dev *dev, int pos, type *val) \
238 int ret = PCIBIOS_SUCCESSFUL; \
240 if (PCI_##size##_BAD) \
242 raw_spin_lock_irq(&pci_lock); \
243 if (unlikely(dev->block_cfg_access)) \
245 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
246 pos, sizeof(type), &data); \
247 raw_spin_unlock_irq(&pci_lock); \
249 return pcibios_err_to_errno(ret); \
251 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
253 /* Returns 0 on success, negative values indicate error. */
254 #define PCI_USER_WRITE_CONFIG(size,type) \
255 int pci_user_write_config_##size \
256 (struct pci_dev *dev, int pos, type val) \
258 int ret = PCIBIOS_SUCCESSFUL; \
259 if (PCI_##size##_BAD) \
261 raw_spin_lock_irq(&pci_lock); \
262 if (unlikely(dev->block_cfg_access)) \
264 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
265 pos, sizeof(type), val); \
266 raw_spin_unlock_irq(&pci_lock); \
267 return pcibios_err_to_errno(ret); \
269 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
271 PCI_USER_READ_CONFIG(byte, u8)
272 PCI_USER_READ_CONFIG(word, u16)
273 PCI_USER_READ_CONFIG(dword, u32)
274 PCI_USER_WRITE_CONFIG(byte, u8)
275 PCI_USER_WRITE_CONFIG(word, u16)
276 PCI_USER_WRITE_CONFIG(dword, u32)
278 /* VPD access through PCI 2.2+ VPD capability */
280 #define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
282 struct pci_vpd_pci22 {
291 * Wait for last operation to complete.
292 * This code has to spin since there is no other notification from the PCI
293 * hardware. Since the VPD is often implemented by serial attachment to an
294 * EEPROM, it may take many milliseconds to complete.
296 * Returns 0 on success, negative values indicate error.
298 static int pci_vpd_pci22_wait(struct pci_dev *dev)
300 struct pci_vpd_pci22 *vpd =
301 container_of(dev->vpd, struct pci_vpd_pci22, base);
302 unsigned long timeout = jiffies + HZ/20 + 2;
310 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
315 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
320 if (time_after(jiffies, timeout)) {
321 dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
324 if (fatal_signal_pending(current))
331 static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
334 struct pci_vpd_pci22 *vpd =
335 container_of(dev->vpd, struct pci_vpd_pci22, base);
337 loff_t end = pos + count;
340 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
343 if (mutex_lock_killable(&vpd->lock))
346 ret = pci_vpd_pci22_wait(dev);
352 unsigned int i, skip;
354 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
359 vpd->flag = PCI_VPD_ADDR_F;
360 ret = pci_vpd_pci22_wait(dev);
364 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
369 for (i = 0; i < sizeof(u32); i++) {
379 mutex_unlock(&vpd->lock);
380 return ret ? ret : count;
383 static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
386 struct pci_vpd_pci22 *vpd =
387 container_of(dev->vpd, struct pci_vpd_pci22, base);
389 loff_t end = pos + count;
392 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
395 if (mutex_lock_killable(&vpd->lock))
398 ret = pci_vpd_pci22_wait(dev);
410 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
413 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
414 pos | PCI_VPD_ADDR_F);
420 ret = pci_vpd_pci22_wait(dev);
427 mutex_unlock(&vpd->lock);
428 return ret ? ret : count;
431 static void pci_vpd_pci22_release(struct pci_dev *dev)
433 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
436 static const struct pci_vpd_ops pci_vpd_pci22_ops = {
437 .read = pci_vpd_pci22_read,
438 .write = pci_vpd_pci22_write,
439 .release = pci_vpd_pci22_release,
442 int pci_vpd_pci22_init(struct pci_dev *dev)
444 struct pci_vpd_pci22 *vpd;
447 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
450 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
454 vpd->base.len = PCI_VPD_PCI22_SIZE;
455 vpd->base.ops = &pci_vpd_pci22_ops;
456 mutex_init(&vpd->lock);
459 dev->vpd = &vpd->base;
464 * pci_cfg_access_lock - Lock PCI config reads/writes
465 * @dev: pci device struct
467 * When access is locked, any userspace reads or writes to config
468 * space and concurrent lock requests will sleep until access is
469 * allowed via pci_cfg_access_unlocked again.
471 void pci_cfg_access_lock(struct pci_dev *dev)
475 raw_spin_lock_irq(&pci_lock);
476 if (dev->block_cfg_access)
478 dev->block_cfg_access = 1;
479 raw_spin_unlock_irq(&pci_lock);
481 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
484 * pci_cfg_access_trylock - try to lock PCI config reads/writes
485 * @dev: pci device struct
487 * Same as pci_cfg_access_lock, but will return 0 if access is
488 * already locked, 1 otherwise. This function can be used from
491 bool pci_cfg_access_trylock(struct pci_dev *dev)
496 raw_spin_lock_irqsave(&pci_lock, flags);
497 if (dev->block_cfg_access)
500 dev->block_cfg_access = 1;
501 raw_spin_unlock_irqrestore(&pci_lock, flags);
505 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
508 * pci_cfg_access_unlock - Unlock PCI config reads/writes
509 * @dev: pci device struct
511 * This function allows PCI config accesses to resume.
513 void pci_cfg_access_unlock(struct pci_dev *dev)
517 raw_spin_lock_irqsave(&pci_lock, flags);
519 /* This indicates a problem in the caller, but we don't need
520 * to kill them, unlike a double-block above. */
521 WARN_ON(!dev->block_cfg_access);
523 dev->block_cfg_access = 0;
524 wake_up_all(&pci_cfg_wait);
525 raw_spin_unlock_irqrestore(&pci_lock, flags);
527 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
529 static inline int pcie_cap_version(const struct pci_dev *dev)
531 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
534 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
536 int type = pci_pcie_type(dev);
538 return type == PCI_EXP_TYPE_ENDPOINT ||
539 type == PCI_EXP_TYPE_LEG_END ||
540 type == PCI_EXP_TYPE_ROOT_PORT ||
541 type == PCI_EXP_TYPE_UPSTREAM ||
542 type == PCI_EXP_TYPE_DOWNSTREAM ||
543 type == PCI_EXP_TYPE_PCI_BRIDGE ||
544 type == PCI_EXP_TYPE_PCIE_BRIDGE;
547 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
549 int type = pci_pcie_type(dev);
551 return (type == PCI_EXP_TYPE_ROOT_PORT ||
552 type == PCI_EXP_TYPE_DOWNSTREAM) &&
553 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
556 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
558 int type = pci_pcie_type(dev);
560 return type == PCI_EXP_TYPE_ROOT_PORT ||
561 type == PCI_EXP_TYPE_RC_EC;
564 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
566 if (!pci_is_pcie(dev))
579 return pcie_cap_has_lnkctl(dev);
583 return pcie_cap_has_sltctl(dev);
587 return pcie_cap_has_rtctl(dev);
588 case PCI_EXP_DEVCAP2:
589 case PCI_EXP_DEVCTL2:
590 case PCI_EXP_LNKCAP2:
591 case PCI_EXP_LNKCTL2:
592 case PCI_EXP_LNKSTA2:
593 return pcie_cap_version(dev) > 1;
600 * Note that these accessor functions are only for the "PCI Express
601 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
602 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
604 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
612 if (pcie_capability_reg_implemented(dev, pos)) {
613 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
615 * Reset *val to 0 if pci_read_config_word() fails, it may
616 * have been written as 0xFFFF if hardware error happens
617 * during pci_read_config_word().
625 * For Functions that do not implement the Slot Capabilities,
626 * Slot Status, and Slot Control registers, these spaces must
627 * be hardwired to 0b, with the exception of the Presence Detect
628 * State bit in the Slot Status register of Downstream Ports,
629 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
631 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
632 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
633 *val = PCI_EXP_SLTSTA_PDS;
638 EXPORT_SYMBOL(pcie_capability_read_word);
640 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
648 if (pcie_capability_reg_implemented(dev, pos)) {
649 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
651 * Reset *val to 0 if pci_read_config_dword() fails, it may
652 * have been written as 0xFFFFFFFF if hardware error happens
653 * during pci_read_config_dword().
660 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
661 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
662 *val = PCI_EXP_SLTSTA_PDS;
667 EXPORT_SYMBOL(pcie_capability_read_dword);
669 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
674 if (!pcie_capability_reg_implemented(dev, pos))
677 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
679 EXPORT_SYMBOL(pcie_capability_write_word);
681 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
686 if (!pcie_capability_reg_implemented(dev, pos))
689 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
691 EXPORT_SYMBOL(pcie_capability_write_dword);
693 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
699 ret = pcie_capability_read_word(dev, pos, &val);
703 ret = pcie_capability_write_word(dev, pos, val);
708 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
710 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
716 ret = pcie_capability_read_dword(dev, pos, &val);
720 ret = pcie_capability_write_dword(dev, pos, val);
725 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);