drivers/pci/dwc/pci-dra7xx.c

   1 /*
   2  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/pci.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/resource.h>
  26 #include <linux/types.h>
  27
  28 #include "pcie-designware.h"
  29
  30 /* PCIe controller wrapper DRA7XX configuration registers */
  31
  32 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN             0x0024
  33 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN         0x0028
  34 #define ERR_SYS                                         BIT(0)
  35 #define ERR_FATAL                                       BIT(1)
  36 #define ERR_NONFATAL                                    BIT(2)
  37 #define ERR_COR                                         BIT(3)
  38 #define ERR_AXI                                         BIT(4)
  39 #define ERR_ECRC                                        BIT(5)
  40 #define PME_TURN_OFF                                    BIT(8)
  41 #define PME_TO_ACK                                      BIT(9)
  42 #define PM_PME                                          BIT(10)
  43 #define LINK_REQ_RST                                    BIT(11)
  44 #define LINK_UP_EVT                                     BIT(12)
  45 #define CFG_BME_EVT                                     BIT(13)
  46 #define CFG_MSE_EVT                                     BIT(14)
  47 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
  48                         ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
  49                         LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
  50
  51 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI              0x0034
  52 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI          0x0038
  53 #define INTA                                            BIT(0)
  54 #define INTB                                            BIT(1)
  55 #define INTC                                            BIT(2)
  56 #define INTD                                            BIT(3)
  57 #define MSI                                             BIT(4)
  58 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
  59
  60 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD                 0x0104
  61 #define LTSSM_EN                                        0x1
  62
  63 #define PCIECTRL_DRA7XX_CONF_PHY_CS                     0x010C
  64 #define LINK_UP                                         BIT(16)
  65 #define DRA7XX_CPU_TO_BUS_ADDR                          0x0FFFFFFF
  66
  67 #define EXP_CAP_ID_OFFSET                               0x70
  68
  69 struct dra7xx_pcie {
  70         struct dw_pcie          *pci;
  71         void __iomem            *base;          /* DT ti_conf */
  72         int                     phy_count;      /* DT phy-names count */
  73         struct phy              **phy;
  74         int                     link_gen;
  75         struct irq_domain       *irq_domain;
  76 };
  77
  78 #define to_dra7xx_pcie(x)       dev_get_drvdata((x)->dev)
  79
  80 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
  81 {
  82         return readl(pcie->base + offset);
  83 }
  84
  85 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
  86                                       u32 value)
  87 {
  88         writel(value, pcie->base + offset);
  89 }
  90
  91 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
  92 {
  93         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
  94         u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
  95
  96         return !!(reg & LINK_UP);
  97 }
  98
  99 static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
 100 {
 101         struct dw_pcie *pci = dra7xx->pci;
 102         struct device *dev = pci->dev;
 103         u32 reg;
 104         u32 exp_cap_off = EXP_CAP_ID_OFFSET;
 105
 106         if (dw_pcie_link_up(pci)) {
 107                 dev_err(dev, "link is already up\n");
 108                 return 0;
 109         }
 110
 111         if (dra7xx->link_gen == 1) {
 112                 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
 113                              4, &reg);
 114                 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 115                         reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
 116                         reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
 117                         dw_pcie_write(pci->dbi_base + exp_cap_off +
 118                                       PCI_EXP_LNKCAP, 4, reg);
 119                 }
 120
 121                 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
 122                              2, &reg);
 123                 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 124                         reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
 125                         reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
 126                         dw_pcie_write(pci->dbi_base + exp_cap_off +
 127                                       PCI_EXP_LNKCTL2, 2, reg);
 128                 }
 129         }
 130
 131         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 132         reg |= LTSSM_EN;
 133         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 134
 135         return dw_pcie_wait_for_link(pci);
 136 }
 137
 138 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
 139 {
 140         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
 141                            ~INTERRUPTS);
 142         dra7xx_pcie_writel(dra7xx,
 143                            PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
 144         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
 145                            ~LEG_EP_INTERRUPTS & ~MSI);
 146         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
 147                            MSI | LEG_EP_INTERRUPTS);
 148 }
 149
 150 static void dra7xx_pcie_host_init(struct pcie_port *pp)
 151 {
 152         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 153         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 154
 155         pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
 156         pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
 157         pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
 158         pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
 159
 160         dw_pcie_setup_rc(pp);
 161
 162         dra7xx_pcie_establish_link(dra7xx);
 163         dw_pcie_msi_init(pp);
 164         dra7xx_pcie_enable_interrupts(dra7xx);
 165 }
 166
 167 static struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
 168         .host_init = dra7xx_pcie_host_init,
 169 };
 170
 171 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 172                                 irq_hw_number_t hwirq)
 173 {
 174         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 175         irq_set_chip_data(irq, domain->host_data);
 176
 177         return 0;
 178 }
 179
 180 static const struct irq_domain_ops intx_domain_ops = {
 181         .map = dra7xx_pcie_intx_map,
 182 };
 183
 184 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
 185 {
 186         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 187         struct device *dev = pci->dev;
 188         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 189         struct device_node *node = dev->of_node;
 190         struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
 191
 192         if (!pcie_intc_node) {
 193                 dev_err(dev, "No PCIe Intc node found\n");
 194                 return -ENODEV;
 195         }
 196
 197         dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
 198                                                    &intx_domain_ops, pp);
 199         if (!dra7xx->irq_domain) {
 200                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 201                 return -ENODEV;
 202         }
 203
 204         return 0;
 205 }
 206
 207 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 208 {
 209         struct dra7xx_pcie *dra7xx = arg;
 210         struct dw_pcie *pci = dra7xx->pci;
 211         struct pcie_port *pp = &pci->pp;
 212         u32 reg;
 213
 214         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
 215
 216         switch (reg) {
 217         case MSI:
 218                 dw_handle_msi_irq(pp);
 219                 break;
 220         case INTA:
 221         case INTB:
 222         case INTC:
 223         case INTD:
 224                 generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
 225                                                     ffs(reg)));
 226                 break;
 227         }
 228
 229         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
 230
 231         return IRQ_HANDLED;
 232 }
 233
 234
 235 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
 236 {
 237         struct dra7xx_pcie *dra7xx = arg;
 238         struct dw_pcie *pci = dra7xx->pci;
 239         struct device *dev = pci->dev;
 240         u32 reg;
 241
 242         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
 243
 244         if (reg & ERR_SYS)
 245                 dev_dbg(dev, "System Error\n");
 246
 247         if (reg & ERR_FATAL)
 248                 dev_dbg(dev, "Fatal Error\n");
 249
 250         if (reg & ERR_NONFATAL)
 251                 dev_dbg(dev, "Non Fatal Error\n");
 252
 253         if (reg & ERR_COR)
 254                 dev_dbg(dev, "Correctable Error\n");
 255
 256         if (reg & ERR_AXI)
 257                 dev_dbg(dev, "AXI tag lookup fatal Error\n");
 258
 259         if (reg & ERR_ECRC)
 260                 dev_dbg(dev, "ECRC Error\n");
 261
 262         if (reg & PME_TURN_OFF)
 263                 dev_dbg(dev,
 264                         "Power Management Event Turn-Off message received\n");
 265
 266         if (reg & PME_TO_ACK)
 267                 dev_dbg(dev,
 268                         "Power Management Turn-Off Ack message received\n");
 269
 270         if (reg & PM_PME)
 271                 dev_dbg(dev, "PM Power Management Event message received\n");
 272
 273         if (reg & LINK_REQ_RST)
 274                 dev_dbg(dev, "Link Request Reset\n");
 275
 276         if (reg & LINK_UP_EVT)
 277                 dev_dbg(dev, "Link-up state change\n");
 278
 279         if (reg & CFG_BME_EVT)
 280                 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
 281
 282         if (reg & CFG_MSE_EVT)
 283                 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
 284
 285         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
 286
 287         return IRQ_HANDLED;
 288 }
 289
 290 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
 291                                        struct platform_device *pdev)
 292 {
 293         int ret;
 294         struct dw_pcie *pci = dra7xx->pci;
 295         struct pcie_port *pp = &pci->pp;
 296         struct device *dev = pci->dev;
 297         struct resource *res;
 298
 299         pp->irq = platform_get_irq(pdev, 1);
 300         if (pp->irq < 0) {
 301                 dev_err(dev, "missing IRQ resource\n");
 302                 return -EINVAL;
 303         }
 304
 305         ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
 306                                IRQF_SHARED | IRQF_NO_THREAD,
 307                                "dra7-pcie-msi", dra7xx);
 308         if (ret) {
 309                 dev_err(dev, "failed to request irq\n");
 310                 return ret;
 311         }
 312
 313         ret = dra7xx_pcie_init_irq_domain(pp);
 314         if (ret < 0)
 315                 return ret;
 316
 317         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
 318         pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
 319         if (!pci->dbi_base)
 320                 return -ENOMEM;
 321
 322         ret = dw_pcie_host_init(pp);
 323         if (ret) {
 324                 dev_err(dev, "failed to initialize host\n");
 325                 return ret;
 326         }
 327
 328         return 0;
 329 }
 330
 331 static const struct dw_pcie_ops dw_pcie_ops = {
 332         .link_up = dra7xx_pcie_link_up,
 333 };
 334
 335 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
 336 {
 337         int phy_count = dra7xx->phy_count;
 338
 339         while (phy_count--) {
 340                 phy_power_off(dra7xx->phy[phy_count]);
 341                 phy_exit(dra7xx->phy[phy_count]);
 342         }
 343 }
 344
 345 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
 346 {
 347         int phy_count = dra7xx->phy_count;
 348         int ret;
 349         int i;
 350
 351         for (i = 0; i < phy_count; i++) {
 352                 ret = phy_init(dra7xx->phy[i]);
 353                 if (ret < 0)
 354                         goto err_phy;
 355
 356                 ret = phy_power_on(dra7xx->phy[i]);
 357                 if (ret < 0) {
 358                         phy_exit(dra7xx->phy[i]);
 359                         goto err_phy;
 360                 }
 361         }
 362
 363         return 0;
 364
 365 err_phy:
 366         while (--i >= 0) {
 367                 phy_power_off(dra7xx->phy[i]);
 368                 phy_exit(dra7xx->phy[i]);
 369         }
 370
 371         return ret;
 372 }
 373
 374 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 375 {
 376         u32 reg;
 377         int ret;
 378         int irq;
 379         int i;
 380         int phy_count;
 381         struct phy **phy;
 382         void __iomem *base;
 383         struct resource *res;
 384         struct dw_pcie *pci;
 385         struct pcie_port *pp;
 386         struct dra7xx_pcie *dra7xx;
 387         struct device *dev = &pdev->dev;
 388         struct device_node *np = dev->of_node;
 389         char name[10];
 390         struct gpio_desc *reset;
 391
 392         dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
 393         if (!dra7xx)
 394                 return -ENOMEM;
 395
 396         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 397         if (!pci)
 398                 return -ENOMEM;
 399
 400         pci->dev = dev;
 401         pci->ops = &dw_pcie_ops;
 402
 403         pp = &pci->pp;
 404         pp->ops = &dra7xx_pcie_host_ops;
 405
 406         irq = platform_get_irq(pdev, 0);
 407         if (irq < 0) {
 408                 dev_err(dev, "missing IRQ resource\n");
 409                 return -EINVAL;
 410         }
 411
 412         ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
 413                                IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
 414         if (ret) {
 415                 dev_err(dev, "failed to request irq\n");
 416                 return ret;
 417         }
 418
 419         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
 420         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 421         if (!base)
 422                 return -ENOMEM;
 423
 424         phy_count = of_property_count_strings(np, "phy-names");
 425         if (phy_count < 0) {
 426                 dev_err(dev, "unable to find the strings\n");
 427                 return phy_count;
 428         }
 429
 430         phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
 431         if (!phy)
 432                 return -ENOMEM;
 433
 434         for (i = 0; i < phy_count; i++) {
 435                 snprintf(name, sizeof(name), "pcie-phy%d", i);
 436                 phy[i] = devm_phy_get(dev, name);
 437                 if (IS_ERR(phy[i]))
 438                         return PTR_ERR(phy[i]);
 439         }
 440
 441         dra7xx->base = base;
 442         dra7xx->phy = phy;
 443         dra7xx->pci = pci;
 444         dra7xx->phy_count = phy_count;
 445
 446         ret = dra7xx_pcie_enable_phy(dra7xx);
 447         if (ret) {
 448                 dev_err(dev, "failed to enable phy\n");
 449                 return ret;
 450         }
 451
 452         platform_set_drvdata(pdev, dra7xx);
 453
 454         pm_runtime_enable(dev);
 455         ret = pm_runtime_get_sync(dev);
 456         if (ret < 0) {
 457                 dev_err(dev, "pm_runtime_get_sync failed\n");
 458                 goto err_get_sync;
 459         }
 460
 461         reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
 462         if (IS_ERR(reset)) {
 463                 ret = PTR_ERR(reset);
 464                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
 465                 goto err_gpio;
 466         }
 467
 468         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 469         reg &= ~LTSSM_EN;
 470         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 471
 472         dra7xx->link_gen = of_pci_get_max_link_speed(np);
 473         if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
 474                 dra7xx->link_gen = 2;
 475
 476         ret = dra7xx_add_pcie_port(dra7xx, pdev);
 477         if (ret < 0)
 478                 goto err_gpio;
 479
 480         return 0;
 481
 482 err_gpio:
 483         pm_runtime_put(dev);
 484
 485 err_get_sync:
 486         pm_runtime_disable(dev);
 487         dra7xx_pcie_disable_phy(dra7xx);
 488
 489         return ret;
 490 }
 491
 492 #ifdef CONFIG_PM_SLEEP
 493 static int dra7xx_pcie_suspend(struct device *dev)
 494 {
 495         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 496         struct dw_pcie *pci = dra7xx->pci;
 497         u32 val;
 498
 499         /* clear MSE */
 500         val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
 501         val &= ~PCI_COMMAND_MEMORY;
 502         dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 503
 504         return 0;
 505 }
 506
 507 static int dra7xx_pcie_resume(struct device *dev)
 508 {
 509         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 510         struct dw_pcie *pci = dra7xx->pci;
 511         u32 val;
 512
 513         /* set MSE */
 514         val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
 515         val |= PCI_COMMAND_MEMORY;
 516         dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 517
 518         return 0;
 519 }
 520
 521 static int dra7xx_pcie_suspend_noirq(struct device *dev)
 522 {
 523         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 524
 525         dra7xx_pcie_disable_phy(dra7xx);
 526
 527         return 0;
 528 }
 529
 530 static int dra7xx_pcie_resume_noirq(struct device *dev)
 531 {
 532         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 533         int ret;
 534
 535         ret = dra7xx_pcie_enable_phy(dra7xx);
 536         if (ret) {
 537                 dev_err(dev, "failed to enable phy\n");
 538                 return ret;
 539         }
 540
 541         return 0;
 542 }
 543 #endif
 544
 545 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
 546         SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
 547         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
 548                                       dra7xx_pcie_resume_noirq)
 549 };
 550
 551 static const struct of_device_id of_dra7xx_pcie_match[] = {
 552         { .compatible = "ti,dra7-pcie", },
 553         {},
 554 };
 555
 556 static struct platform_driver dra7xx_pcie_driver = {
 557         .driver = {
 558                 .name   = "dra7-pcie",
 559                 .of_match_table = of_dra7xx_pcie_match,
 560                 .suppress_bind_attrs = true,
 561                 .pm     = &dra7xx_pcie_pm_ops,
 562         },
 563 };
 564 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);