2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
21 #include <linux/module.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_device.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29 #include <linux/types.h>
30 #include <linux/interrupt.h>
31 #include <linux/reset.h>
33 #include "pcie-designware.h"
35 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
37 enum imx6_pcie_variants {
47 bool gpio_active_high;
50 struct clk *pcie_inbound_axi;
52 struct regmap *iomuxc_gpr;
53 struct reset_control *pciephy_reset;
54 struct reset_control *apps_reset;
55 enum imx6_pcie_variants variant;
57 u32 tx_deemph_gen2_3p5db;
58 u32 tx_deemph_gen2_6db;
64 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
65 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
66 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
67 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
69 /* PCIe Root Complex registers (memory-mapped) */
70 #define PCIE_RC_LCR 0x7c
71 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
72 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
73 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
75 #define PCIE_RC_LCSR 0x80
77 /* PCIe Port Logic registers (memory-mapped) */
78 #define PL_OFFSET 0x700
79 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
80 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
81 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
84 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
85 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
87 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
88 #define PCIE_PHY_CTRL_DATA_LOC 0
89 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
90 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
91 #define PCIE_PHY_CTRL_WR_LOC 18
92 #define PCIE_PHY_CTRL_RD_LOC 19
94 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
95 #define PCIE_PHY_STAT_ACK_LOC 16
97 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
98 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
100 /* PHY registers (not memory-mapped) */
101 #define PCIE_PHY_RX_ASIC_OUT 0x100D
102 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
104 #define PHY_RX_OVRD_IN_LO 0x1005
105 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
106 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
108 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
110 struct dw_pcie *pci = imx6_pcie->pci;
112 u32 max_iterations = 10;
113 u32 wait_counter = 0;
116 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
117 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
124 } while (wait_counter < max_iterations);
129 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
131 struct dw_pcie *pci = imx6_pcie->pci;
135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
138 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
139 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
141 ret = pcie_phy_poll_ack(imx6_pcie, 1);
145 val = addr << PCIE_PHY_CTRL_DATA_LOC;
146 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
148 return pcie_phy_poll_ack(imx6_pcie, 0);
151 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
152 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
154 struct dw_pcie *pci = imx6_pcie->pci;
158 ret = pcie_phy_wait_ack(imx6_pcie, addr);
162 /* assert Read signal */
163 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
164 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
166 ret = pcie_phy_poll_ack(imx6_pcie, 1);
170 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
171 *data = val & 0xffff;
173 /* deassert Read signal */
174 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
176 return pcie_phy_poll_ack(imx6_pcie, 0);
179 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
181 struct dw_pcie *pci = imx6_pcie->pci;
187 ret = pcie_phy_wait_ack(imx6_pcie, addr);
191 var = data << PCIE_PHY_CTRL_DATA_LOC;
192 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
195 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
196 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
198 ret = pcie_phy_poll_ack(imx6_pcie, 1);
202 /* deassert cap data */
203 var = data << PCIE_PHY_CTRL_DATA_LOC;
204 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
206 /* wait for ack de-assertion */
207 ret = pcie_phy_poll_ack(imx6_pcie, 0);
211 /* assert wr signal */
212 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
213 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
216 ret = pcie_phy_poll_ack(imx6_pcie, 1);
220 /* deassert wr signal */
221 var = data << PCIE_PHY_CTRL_DATA_LOC;
222 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
224 /* wait for ack de-assertion */
225 ret = pcie_phy_poll_ack(imx6_pcie, 0);
229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
234 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
238 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
239 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
240 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
241 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
243 usleep_range(2000, 3000);
245 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
246 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
247 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
248 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
251 /* Added for PCI abort handling */
252 static int imx6q_pcie_abort_handler(unsigned long addr,
253 unsigned int fsr, struct pt_regs *regs)
255 unsigned long pc = instruction_pointer(regs);
256 unsigned long instr = *(unsigned long *)pc;
257 int reg = (instr >> 12) & 15;
260 * If the instruction being executed was a read,
261 * make it look like it read all-ones.
263 if ((instr & 0x0c100000) == 0x04100000) {
266 if (instr & 0x00400000)
271 regs->uregs[reg] = val;
276 if ((instr & 0x0e100090) == 0x00100090) {
277 regs->uregs[reg] = -1;
285 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
287 switch (imx6_pcie->variant) {
289 reset_control_assert(imx6_pcie->pciephy_reset);
290 reset_control_assert(imx6_pcie->apps_reset);
293 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
294 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
295 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
296 /* Force PCIe PHY reset */
297 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
298 IMX6SX_GPR5_PCIE_BTNRST_RESET,
299 IMX6SX_GPR5_PCIE_BTNRST_RESET);
302 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
303 IMX6Q_GPR1_PCIE_SW_RST,
304 IMX6Q_GPR1_PCIE_SW_RST);
307 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
308 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
309 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
310 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
315 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
317 struct dw_pcie *pci = imx6_pcie->pci;
318 struct device *dev = pci->dev;
321 switch (imx6_pcie->variant) {
323 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
325 dev_err(dev, "unable to enable pcie_axi clock\n");
329 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
330 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
332 case IMX6QP: /* FALLTHROUGH */
334 /* power up core phy and enable ref clock */
335 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
336 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
338 * the async reset input need ref clock to sync internally,
339 * when the ref clock comes after reset, internal synced
340 * reset time is too short, cannot meet the requirement.
341 * add one ~10us delay here.
344 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
345 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
354 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
357 unsigned int retries;
358 struct device *dev = imx6_pcie->pci->dev;
360 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
361 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
363 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
366 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
367 PHY_PLL_LOCK_WAIT_USLEEP_MAX);
370 dev_err(dev, "PCIe PLL lock timeout\n");
373 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
375 struct dw_pcie *pci = imx6_pcie->pci;
376 struct device *dev = pci->dev;
379 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
381 dev_err(dev, "unable to enable pcie_phy clock\n");
385 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
387 dev_err(dev, "unable to enable pcie_bus clock\n");
391 ret = clk_prepare_enable(imx6_pcie->pcie);
393 dev_err(dev, "unable to enable pcie clock\n");
397 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
399 dev_err(dev, "unable to enable pcie ref clock\n");
403 /* allow the clocks to stabilize */
404 usleep_range(200, 500);
406 /* Some boards don't have PCIe reset GPIO. */
407 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
408 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
409 imx6_pcie->gpio_active_high);
411 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
412 !imx6_pcie->gpio_active_high);
415 switch (imx6_pcie->variant) {
417 reset_control_deassert(imx6_pcie->pciephy_reset);
418 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
421 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
422 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
425 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
426 IMX6Q_GPR1_PCIE_SW_RST, 0);
428 usleep_range(200, 500);
430 case IMX6Q: /* Nothing to do */
437 clk_disable_unprepare(imx6_pcie->pcie);
439 clk_disable_unprepare(imx6_pcie->pcie_bus);
441 clk_disable_unprepare(imx6_pcie->pcie_phy);
444 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
446 switch (imx6_pcie->variant) {
448 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
449 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
452 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
453 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
454 IMX6SX_GPR12_PCIE_RX_EQ_2);
457 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
458 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
460 /* configure constant input signal to the pcie ctrl and phy */
461 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
462 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
464 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
465 IMX6Q_GPR8_TX_DEEMPH_GEN1,
466 imx6_pcie->tx_deemph_gen1 << 0);
467 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
468 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
469 imx6_pcie->tx_deemph_gen2_3p5db << 6);
470 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
471 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
472 imx6_pcie->tx_deemph_gen2_6db << 12);
473 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
474 IMX6Q_GPR8_TX_SWING_FULL,
475 imx6_pcie->tx_swing_full << 18);
476 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
477 IMX6Q_GPR8_TX_SWING_LOW,
478 imx6_pcie->tx_swing_low << 25);
482 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
483 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
486 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
488 struct dw_pcie *pci = imx6_pcie->pci;
489 struct device *dev = pci->dev;
491 /* check if the link is up or not */
492 if (!dw_pcie_wait_for_link(pci))
495 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
496 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
497 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
501 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
503 struct dw_pcie *pci = imx6_pcie->pci;
504 struct device *dev = pci->dev;
506 unsigned int retries;
508 for (retries = 0; retries < 200; retries++) {
509 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
510 /* Test if the speed change finished. */
511 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
513 usleep_range(100, 1000);
516 dev_err(dev, "Speed change timeout\n");
520 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
522 struct imx6_pcie *imx6_pcie = arg;
523 struct dw_pcie *pci = imx6_pcie->pci;
524 struct pcie_port *pp = &pci->pp;
526 return dw_handle_msi_irq(pp);
529 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
531 struct dw_pcie *pci = imx6_pcie->pci;
532 struct device *dev = pci->dev;
537 * Force Gen1 operation when starting the link. In case the link is
538 * started in Gen2 mode, there is a possibility the devices on the
539 * bus will not be detected at all. This happens with PCIe switches.
541 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
542 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
543 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
544 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
547 if (imx6_pcie->variant == IMX7D)
548 reset_control_deassert(imx6_pcie->apps_reset);
550 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
551 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
553 ret = imx6_pcie_wait_for_link(imx6_pcie);
557 if (imx6_pcie->link_gen == 2) {
558 /* Allow Gen2 mode after the link is up. */
559 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
560 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
561 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
562 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
565 * Start Directed Speed Change so the best possible
566 * speed both link partners support can be negotiated.
568 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
569 tmp |= PORT_LOGIC_SPEED_CHANGE;
570 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
572 if (imx6_pcie->variant != IMX7D) {
574 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
575 * from i.MX6 family when no link speed transition
576 * occurs and we go Gen1 -> yep, Gen1. The difference
577 * is that, in such case, it will not be cleared by HW
578 * which will cause the following code to report false
582 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
584 dev_err(dev, "Failed to bring link up!\n");
589 /* Make sure link training is finished as well! */
590 ret = imx6_pcie_wait_for_link(imx6_pcie);
592 dev_err(dev, "Failed to bring link up!\n");
596 dev_info(dev, "Link: Gen2 disabled\n");
599 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
600 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
604 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
605 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
606 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
607 imx6_pcie_reset_phy(imx6_pcie);
611 static void imx6_pcie_host_init(struct pcie_port *pp)
613 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
614 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
616 imx6_pcie_assert_core_reset(imx6_pcie);
617 imx6_pcie_init_phy(imx6_pcie);
618 imx6_pcie_deassert_core_reset(imx6_pcie);
619 dw_pcie_setup_rc(pp);
620 imx6_pcie_establish_link(imx6_pcie);
622 if (IS_ENABLED(CONFIG_PCI_MSI))
623 dw_pcie_msi_init(pp);
626 static int imx6_pcie_link_up(struct dw_pcie *pci)
628 return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
629 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
632 static struct dw_pcie_host_ops imx6_pcie_host_ops = {
633 .host_init = imx6_pcie_host_init,
636 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
637 struct platform_device *pdev)
639 struct dw_pcie *pci = imx6_pcie->pci;
640 struct pcie_port *pp = &pci->pp;
641 struct device *dev = &pdev->dev;
644 if (IS_ENABLED(CONFIG_PCI_MSI)) {
645 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
646 if (pp->msi_irq <= 0) {
647 dev_err(dev, "failed to get MSI irq\n");
651 ret = devm_request_irq(dev, pp->msi_irq,
652 imx6_pcie_msi_handler,
653 IRQF_SHARED | IRQF_NO_THREAD,
654 "mx6-pcie-msi", imx6_pcie);
656 dev_err(dev, "failed to request MSI irq\n");
661 pp->root_bus_nr = -1;
662 pp->ops = &imx6_pcie_host_ops;
664 ret = dw_pcie_host_init(pp);
666 dev_err(dev, "failed to initialize host\n");
673 static const struct dw_pcie_ops dw_pcie_ops = {
674 .link_up = imx6_pcie_link_up,
677 static int imx6_pcie_probe(struct platform_device *pdev)
679 struct device *dev = &pdev->dev;
681 struct imx6_pcie *imx6_pcie;
682 struct resource *dbi_base;
683 struct device_node *node = dev->of_node;
686 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
690 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
695 pci->ops = &dw_pcie_ops;
697 imx6_pcie->pci = pci;
699 (enum imx6_pcie_variants)of_device_get_match_data(dev);
701 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
702 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
703 if (IS_ERR(pci->dbi_base))
704 return PTR_ERR(pci->dbi_base);
707 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
708 imx6_pcie->gpio_active_high = of_property_read_bool(node,
709 "reset-gpio-active-high");
710 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
711 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
712 imx6_pcie->gpio_active_high ?
713 GPIOF_OUT_INIT_HIGH :
717 dev_err(dev, "unable to get reset gpio\n");
720 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
721 return imx6_pcie->reset_gpio;
725 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
726 if (IS_ERR(imx6_pcie->pcie_phy)) {
727 dev_err(dev, "pcie_phy clock source missing or invalid\n");
728 return PTR_ERR(imx6_pcie->pcie_phy);
731 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
732 if (IS_ERR(imx6_pcie->pcie_bus)) {
733 dev_err(dev, "pcie_bus clock source missing or invalid\n");
734 return PTR_ERR(imx6_pcie->pcie_bus);
737 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
738 if (IS_ERR(imx6_pcie->pcie)) {
739 dev_err(dev, "pcie clock source missing or invalid\n");
740 return PTR_ERR(imx6_pcie->pcie);
743 switch (imx6_pcie->variant) {
745 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
747 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
748 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
749 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
753 imx6_pcie->pciephy_reset = devm_reset_control_get(dev,
755 if (IS_ERR(imx6_pcie->pciephy_reset)) {
756 dev_err(dev, "Failed to get PCIEPHY reset control\n");
757 return PTR_ERR(imx6_pcie->pciephy_reset);
760 imx6_pcie->apps_reset = devm_reset_control_get(dev, "apps");
761 if (IS_ERR(imx6_pcie->apps_reset)) {
762 dev_err(dev, "Failed to get PCIE APPS reset control\n");
763 return PTR_ERR(imx6_pcie->apps_reset);
770 /* Grab GPR config register range */
771 imx6_pcie->iomuxc_gpr =
772 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
773 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
774 dev_err(dev, "unable to find iomuxc registers\n");
775 return PTR_ERR(imx6_pcie->iomuxc_gpr);
778 /* Grab PCIe PHY Tx Settings */
779 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
780 &imx6_pcie->tx_deemph_gen1))
781 imx6_pcie->tx_deemph_gen1 = 0;
783 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
784 &imx6_pcie->tx_deemph_gen2_3p5db))
785 imx6_pcie->tx_deemph_gen2_3p5db = 0;
787 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
788 &imx6_pcie->tx_deemph_gen2_6db))
789 imx6_pcie->tx_deemph_gen2_6db = 20;
791 if (of_property_read_u32(node, "fsl,tx-swing-full",
792 &imx6_pcie->tx_swing_full))
793 imx6_pcie->tx_swing_full = 127;
795 if (of_property_read_u32(node, "fsl,tx-swing-low",
796 &imx6_pcie->tx_swing_low))
797 imx6_pcie->tx_swing_low = 127;
799 /* Limit link speed */
800 ret = of_property_read_u32(node, "fsl,max-link-speed",
801 &imx6_pcie->link_gen);
803 imx6_pcie->link_gen = 1;
805 platform_set_drvdata(pdev, imx6_pcie);
807 ret = imx6_add_pcie_port(imx6_pcie, pdev);
814 static void imx6_pcie_shutdown(struct platform_device *pdev)
816 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
818 /* bring down link, so bootloader gets clean state in case of reboot */
819 imx6_pcie_assert_core_reset(imx6_pcie);
822 static const struct of_device_id imx6_pcie_of_match[] = {
823 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
824 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
825 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
826 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
830 static struct platform_driver imx6_pcie_driver = {
832 .name = "imx6q-pcie",
833 .of_match_table = imx6_pcie_of_match,
834 .suppress_bind_attrs = true,
836 .probe = imx6_pcie_probe,
837 .shutdown = imx6_pcie_shutdown,
840 static int __init imx6_pcie_init(void)
843 * Since probe() can be deferred we need to make sure that
844 * hook_fault_code is not called after __init memory is freed
845 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
846 * we can install the handler here without risking it
847 * accessing some uninitialized driver state.
849 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
850 "external abort on non-linefetch");
852 return platform_driver_register(&imx6_pcie_driver);
854 device_initcall(imx6_pcie_init);