2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
21 #include <linux/module.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_device.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/regmap.h>
27 #include <linux/resource.h>
28 #include <linux/signal.h>
29 #include <linux/types.h>
30 #include <linux/interrupt.h>
31 #include <linux/reset.h>
33 #include "pcie-designware.h"
35 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
37 enum imx6_pcie_variants {
47 bool gpio_active_high;
50 struct clk *pcie_inbound_axi;
52 struct regmap *iomuxc_gpr;
53 struct reset_control *pciephy_reset;
54 struct reset_control *apps_reset;
55 enum imx6_pcie_variants variant;
57 u32 tx_deemph_gen2_3p5db;
58 u32 tx_deemph_gen2_6db;
64 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
65 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
66 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
67 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
69 /* PCIe Root Complex registers (memory-mapped) */
70 #define PCIE_RC_LCR 0x7c
71 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
72 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
73 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
75 #define PCIE_RC_LCSR 0x80
77 /* PCIe Port Logic registers (memory-mapped) */
78 #define PL_OFFSET 0x700
79 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
80 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
81 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
84 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
85 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
87 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
88 #define PCIE_PHY_CTRL_DATA_LOC 0
89 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
90 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
91 #define PCIE_PHY_CTRL_WR_LOC 18
92 #define PCIE_PHY_CTRL_RD_LOC 19
94 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
95 #define PCIE_PHY_STAT_ACK_LOC 16
97 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
98 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
100 /* PHY registers (not memory-mapped) */
101 #define PCIE_PHY_RX_ASIC_OUT 0x100D
102 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
104 #define PHY_RX_OVRD_IN_LO 0x1005
105 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
106 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
108 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
110 struct dw_pcie *pci = imx6_pcie->pci;
112 u32 max_iterations = 10;
113 u32 wait_counter = 0;
116 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
117 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
124 } while (wait_counter < max_iterations);
129 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
131 struct dw_pcie *pci = imx6_pcie->pci;
135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
138 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
139 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
141 ret = pcie_phy_poll_ack(imx6_pcie, 1);
145 val = addr << PCIE_PHY_CTRL_DATA_LOC;
146 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
148 return pcie_phy_poll_ack(imx6_pcie, 0);
151 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
152 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
154 struct dw_pcie *pci = imx6_pcie->pci;
158 ret = pcie_phy_wait_ack(imx6_pcie, addr);
162 /* assert Read signal */
163 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
164 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
166 ret = pcie_phy_poll_ack(imx6_pcie, 1);
170 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
171 *data = val & 0xffff;
173 /* deassert Read signal */
174 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
176 return pcie_phy_poll_ack(imx6_pcie, 0);
179 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
181 struct dw_pcie *pci = imx6_pcie->pci;
187 ret = pcie_phy_wait_ack(imx6_pcie, addr);
191 var = data << PCIE_PHY_CTRL_DATA_LOC;
192 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
195 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
196 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
198 ret = pcie_phy_poll_ack(imx6_pcie, 1);
202 /* deassert cap data */
203 var = data << PCIE_PHY_CTRL_DATA_LOC;
204 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
206 /* wait for ack de-assertion */
207 ret = pcie_phy_poll_ack(imx6_pcie, 0);
211 /* assert wr signal */
212 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
213 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
216 ret = pcie_phy_poll_ack(imx6_pcie, 1);
220 /* deassert wr signal */
221 var = data << PCIE_PHY_CTRL_DATA_LOC;
222 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
224 /* wait for ack de-assertion */
225 ret = pcie_phy_poll_ack(imx6_pcie, 0);
229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
234 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
238 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
239 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
240 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
241 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
243 usleep_range(2000, 3000);
245 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
246 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
247 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
248 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
251 /* Added for PCI abort handling */
252 static int imx6q_pcie_abort_handler(unsigned long addr,
253 unsigned int fsr, struct pt_regs *regs)
258 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
260 switch (imx6_pcie->variant) {
262 reset_control_assert(imx6_pcie->pciephy_reset);
263 reset_control_assert(imx6_pcie->apps_reset);
266 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
267 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
268 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
269 /* Force PCIe PHY reset */
270 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
271 IMX6SX_GPR5_PCIE_BTNRST_RESET,
272 IMX6SX_GPR5_PCIE_BTNRST_RESET);
275 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
276 IMX6Q_GPR1_PCIE_SW_RST,
277 IMX6Q_GPR1_PCIE_SW_RST);
280 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
281 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
282 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
283 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
288 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
290 struct dw_pcie *pci = imx6_pcie->pci;
291 struct device *dev = pci->dev;
294 switch (imx6_pcie->variant) {
296 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
298 dev_err(dev, "unable to enable pcie_axi clock\n");
302 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
303 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
305 case IMX6QP: /* FALLTHROUGH */
307 /* power up core phy and enable ref clock */
308 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
309 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
311 * the async reset input need ref clock to sync internally,
312 * when the ref clock comes after reset, internal synced
313 * reset time is too short, cannot meet the requirement.
314 * add one ~10us delay here.
317 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
318 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
327 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
330 unsigned int retries;
331 struct device *dev = imx6_pcie->pci->dev;
333 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
334 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
336 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
339 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
340 PHY_PLL_LOCK_WAIT_USLEEP_MAX);
343 dev_err(dev, "PCIe PLL lock timeout\n");
346 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
348 struct dw_pcie *pci = imx6_pcie->pci;
349 struct device *dev = pci->dev;
352 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
354 dev_err(dev, "unable to enable pcie_phy clock\n");
358 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
360 dev_err(dev, "unable to enable pcie_bus clock\n");
364 ret = clk_prepare_enable(imx6_pcie->pcie);
366 dev_err(dev, "unable to enable pcie clock\n");
370 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
372 dev_err(dev, "unable to enable pcie ref clock\n");
376 /* allow the clocks to stabilize */
377 usleep_range(200, 500);
379 /* Some boards don't have PCIe reset GPIO. */
380 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
381 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
382 imx6_pcie->gpio_active_high);
384 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
385 !imx6_pcie->gpio_active_high);
388 switch (imx6_pcie->variant) {
390 reset_control_deassert(imx6_pcie->pciephy_reset);
391 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
394 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
395 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
398 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
399 IMX6Q_GPR1_PCIE_SW_RST, 0);
401 usleep_range(200, 500);
403 case IMX6Q: /* Nothing to do */
410 clk_disable_unprepare(imx6_pcie->pcie);
412 clk_disable_unprepare(imx6_pcie->pcie_bus);
414 clk_disable_unprepare(imx6_pcie->pcie_phy);
417 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
419 switch (imx6_pcie->variant) {
421 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
422 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
425 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
426 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
427 IMX6SX_GPR12_PCIE_RX_EQ_2);
430 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
431 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
433 /* configure constant input signal to the pcie ctrl and phy */
434 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
435 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
437 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
438 IMX6Q_GPR8_TX_DEEMPH_GEN1,
439 imx6_pcie->tx_deemph_gen1 << 0);
440 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
441 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
442 imx6_pcie->tx_deemph_gen2_3p5db << 6);
443 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
444 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
445 imx6_pcie->tx_deemph_gen2_6db << 12);
446 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
447 IMX6Q_GPR8_TX_SWING_FULL,
448 imx6_pcie->tx_swing_full << 18);
449 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
450 IMX6Q_GPR8_TX_SWING_LOW,
451 imx6_pcie->tx_swing_low << 25);
455 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
456 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
459 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
461 struct dw_pcie *pci = imx6_pcie->pci;
462 struct device *dev = pci->dev;
464 /* check if the link is up or not */
465 if (!dw_pcie_wait_for_link(pci))
468 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
469 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
470 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
474 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
476 struct dw_pcie *pci = imx6_pcie->pci;
477 struct device *dev = pci->dev;
479 unsigned int retries;
481 for (retries = 0; retries < 200; retries++) {
482 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
483 /* Test if the speed change finished. */
484 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
486 usleep_range(100, 1000);
489 dev_err(dev, "Speed change timeout\n");
493 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
495 struct imx6_pcie *imx6_pcie = arg;
496 struct dw_pcie *pci = imx6_pcie->pci;
497 struct pcie_port *pp = &pci->pp;
499 return dw_handle_msi_irq(pp);
502 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
504 struct dw_pcie *pci = imx6_pcie->pci;
505 struct device *dev = pci->dev;
510 * Force Gen1 operation when starting the link. In case the link is
511 * started in Gen2 mode, there is a possibility the devices on the
512 * bus will not be detected at all. This happens with PCIe switches.
514 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
515 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
516 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
517 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
520 if (imx6_pcie->variant == IMX7D)
521 reset_control_deassert(imx6_pcie->apps_reset);
523 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
524 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
526 ret = imx6_pcie_wait_for_link(imx6_pcie);
530 if (imx6_pcie->link_gen == 2) {
531 /* Allow Gen2 mode after the link is up. */
532 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
533 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
534 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
535 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
538 * Start Directed Speed Change so the best possible
539 * speed both link partners support can be negotiated.
541 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
542 tmp |= PORT_LOGIC_SPEED_CHANGE;
543 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
545 if (imx6_pcie->variant != IMX7D) {
547 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
548 * from i.MX6 family when no link speed transition
549 * occurs and we go Gen1 -> yep, Gen1. The difference
550 * is that, in such case, it will not be cleared by HW
551 * which will cause the following code to report false
555 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
557 dev_err(dev, "Failed to bring link up!\n");
562 /* Make sure link training is finished as well! */
563 ret = imx6_pcie_wait_for_link(imx6_pcie);
565 dev_err(dev, "Failed to bring link up!\n");
569 dev_info(dev, "Link: Gen2 disabled\n");
572 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
573 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
577 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
578 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
579 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
580 imx6_pcie_reset_phy(imx6_pcie);
584 static void imx6_pcie_host_init(struct pcie_port *pp)
586 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
587 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
589 imx6_pcie_assert_core_reset(imx6_pcie);
590 imx6_pcie_init_phy(imx6_pcie);
591 imx6_pcie_deassert_core_reset(imx6_pcie);
592 dw_pcie_setup_rc(pp);
593 imx6_pcie_establish_link(imx6_pcie);
595 if (IS_ENABLED(CONFIG_PCI_MSI))
596 dw_pcie_msi_init(pp);
599 static int imx6_pcie_link_up(struct dw_pcie *pci)
601 return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
602 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
605 static struct dw_pcie_host_ops imx6_pcie_host_ops = {
606 .host_init = imx6_pcie_host_init,
609 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
610 struct platform_device *pdev)
612 struct dw_pcie *pci = imx6_pcie->pci;
613 struct pcie_port *pp = &pci->pp;
614 struct device *dev = &pdev->dev;
617 if (IS_ENABLED(CONFIG_PCI_MSI)) {
618 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
619 if (pp->msi_irq <= 0) {
620 dev_err(dev, "failed to get MSI irq\n");
624 ret = devm_request_irq(dev, pp->msi_irq,
625 imx6_pcie_msi_handler,
626 IRQF_SHARED | IRQF_NO_THREAD,
627 "mx6-pcie-msi", imx6_pcie);
629 dev_err(dev, "failed to request MSI irq\n");
634 pp->root_bus_nr = -1;
635 pp->ops = &imx6_pcie_host_ops;
637 ret = dw_pcie_host_init(pp);
639 dev_err(dev, "failed to initialize host\n");
646 static const struct dw_pcie_ops dw_pcie_ops = {
647 .link_up = imx6_pcie_link_up,
650 static int imx6_pcie_probe(struct platform_device *pdev)
652 struct device *dev = &pdev->dev;
654 struct imx6_pcie *imx6_pcie;
655 struct resource *dbi_base;
656 struct device_node *node = dev->of_node;
659 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
663 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
668 pci->ops = &dw_pcie_ops;
670 imx6_pcie->pci = pci;
672 (enum imx6_pcie_variants)of_device_get_match_data(dev);
674 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
675 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
676 if (IS_ERR(pci->dbi_base))
677 return PTR_ERR(pci->dbi_base);
680 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
681 imx6_pcie->gpio_active_high = of_property_read_bool(node,
682 "reset-gpio-active-high");
683 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
684 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
685 imx6_pcie->gpio_active_high ?
686 GPIOF_OUT_INIT_HIGH :
690 dev_err(dev, "unable to get reset gpio\n");
693 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
694 return imx6_pcie->reset_gpio;
698 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
699 if (IS_ERR(imx6_pcie->pcie_phy)) {
700 dev_err(dev, "pcie_phy clock source missing or invalid\n");
701 return PTR_ERR(imx6_pcie->pcie_phy);
704 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
705 if (IS_ERR(imx6_pcie->pcie_bus)) {
706 dev_err(dev, "pcie_bus clock source missing or invalid\n");
707 return PTR_ERR(imx6_pcie->pcie_bus);
710 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
711 if (IS_ERR(imx6_pcie->pcie)) {
712 dev_err(dev, "pcie clock source missing or invalid\n");
713 return PTR_ERR(imx6_pcie->pcie);
716 switch (imx6_pcie->variant) {
718 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
720 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
721 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
722 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
726 imx6_pcie->pciephy_reset = devm_reset_control_get(dev,
728 if (IS_ERR(imx6_pcie->pciephy_reset)) {
729 dev_err(dev, "Failed to get PCIEPHY reset control\n");
730 return PTR_ERR(imx6_pcie->pciephy_reset);
733 imx6_pcie->apps_reset = devm_reset_control_get(dev, "apps");
734 if (IS_ERR(imx6_pcie->apps_reset)) {
735 dev_err(dev, "Failed to get PCIE APPS reset control\n");
736 return PTR_ERR(imx6_pcie->apps_reset);
743 /* Grab GPR config register range */
744 imx6_pcie->iomuxc_gpr =
745 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
746 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
747 dev_err(dev, "unable to find iomuxc registers\n");
748 return PTR_ERR(imx6_pcie->iomuxc_gpr);
751 /* Grab PCIe PHY Tx Settings */
752 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
753 &imx6_pcie->tx_deemph_gen1))
754 imx6_pcie->tx_deemph_gen1 = 0;
756 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
757 &imx6_pcie->tx_deemph_gen2_3p5db))
758 imx6_pcie->tx_deemph_gen2_3p5db = 0;
760 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
761 &imx6_pcie->tx_deemph_gen2_6db))
762 imx6_pcie->tx_deemph_gen2_6db = 20;
764 if (of_property_read_u32(node, "fsl,tx-swing-full",
765 &imx6_pcie->tx_swing_full))
766 imx6_pcie->tx_swing_full = 127;
768 if (of_property_read_u32(node, "fsl,tx-swing-low",
769 &imx6_pcie->tx_swing_low))
770 imx6_pcie->tx_swing_low = 127;
772 /* Limit link speed */
773 ret = of_property_read_u32(node, "fsl,max-link-speed",
774 &imx6_pcie->link_gen);
776 imx6_pcie->link_gen = 1;
778 platform_set_drvdata(pdev, imx6_pcie);
780 ret = imx6_add_pcie_port(imx6_pcie, pdev);
787 static void imx6_pcie_shutdown(struct platform_device *pdev)
789 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
791 /* bring down link, so bootloader gets clean state in case of reboot */
792 imx6_pcie_assert_core_reset(imx6_pcie);
795 static const struct of_device_id imx6_pcie_of_match[] = {
796 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
797 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
798 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
799 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
803 static struct platform_driver imx6_pcie_driver = {
805 .name = "imx6q-pcie",
806 .of_match_table = imx6_pcie_of_match,
807 .suppress_bind_attrs = true,
809 .probe = imx6_pcie_probe,
810 .shutdown = imx6_pcie_shutdown,
813 static int __init imx6_pcie_init(void)
816 * Since probe() can be deferred we need to make sure that
817 * hook_fault_code is not called after __init memory is freed
818 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
819 * we can install the handler here without risking it
820 * accessing some uninitialized driver state.
822 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
823 "imprecise external abort");
825 return platform_driver_register(&imx6_pcie_driver);
827 device_initcall(imx6_pcie_init);