2 * PCIe host controller driver for Marvell Armada-8K SoCs
4 * Armada-8K PCIe Glue Layer Source Code
6 * Copyright (C) 2016 Marvell Technology Group Ltd.
8 * Author: Yehuda Yitshak <yehuday@marvell.com>
9 * Author: Shadi Ammouri <shadi@marvell.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/resource.h>
26 #include <linux/of_pci.h>
27 #include <linux/of_irq.h>
29 #include "pcie-designware.h"
31 struct armada8k_pcie {
36 #define PCIE_VENDOR_REGS_OFFSET 0x8000
38 #define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
39 #define PCIE_APP_LTSSM_EN BIT(2)
40 #define PCIE_DEVICE_TYPE_SHIFT 4
41 #define PCIE_DEVICE_TYPE_MASK 0xF
42 #define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
44 #define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
45 #define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
46 #define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
48 #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
49 #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
50 #define PCIE_INT_A_ASSERT_MASK BIT(9)
51 #define PCIE_INT_B_ASSERT_MASK BIT(10)
52 #define PCIE_INT_C_ASSERT_MASK BIT(11)
53 #define PCIE_INT_D_ASSERT_MASK BIT(12)
55 #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
56 #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
57 #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
58 #define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
60 * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
63 #define ARCACHE_DEFAULT_VALUE 0x3511
64 #define AWCACHE_DEFAULT_VALUE 0x5311
66 #define DOMAIN_OUTER_SHAREABLE 0x2
67 #define AX_USER_DOMAIN_MASK 0x3
68 #define AX_USER_DOMAIN_SHIFT 4
70 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
72 static int armada8k_pcie_link_up(struct dw_pcie *pci)
75 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
77 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
79 if ((reg & mask) == mask)
82 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
86 static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
88 struct dw_pcie *pci = pcie->pci;
91 if (!dw_pcie_link_up(pci)) {
92 /* Disable LTSSM state machine to enable configuration */
93 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
94 reg &= ~(PCIE_APP_LTSSM_EN);
95 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
98 /* Set the device to root complex mode */
99 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
100 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
101 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
102 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
104 /* Set the PCIe master AxCache attributes */
105 dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
106 dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
108 /* Set the PCIe master AxDomain attributes */
109 reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
110 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
111 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
112 dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
114 reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
115 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
116 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
117 dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
119 /* Enable INT A-D interrupts */
120 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
121 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
122 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
123 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
125 if (!dw_pcie_link_up(pci)) {
126 /* Configuration done. Start LTSSM */
127 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
128 reg |= PCIE_APP_LTSSM_EN;
129 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
132 /* Wait until the link becomes active again */
133 if (dw_pcie_wait_for_link(pci))
134 dev_err(pci->dev, "Link not up after reconfiguration\n");
137 static void armada8k_pcie_host_init(struct pcie_port *pp)
139 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
140 struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
142 dw_pcie_setup_rc(pp);
143 armada8k_pcie_establish_link(pcie);
146 static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
148 struct armada8k_pcie *pcie = arg;
149 struct dw_pcie *pci = pcie->pci;
153 * Interrupts are directly handled by the device driver of the
154 * PCI device. However, they are also latched into the PCIe
155 * controller, so we simply discard them.
157 val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
158 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
163 static struct dw_pcie_host_ops armada8k_pcie_host_ops = {
164 .host_init = armada8k_pcie_host_init,
167 static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
168 struct platform_device *pdev)
170 struct dw_pcie *pci = pcie->pci;
171 struct pcie_port *pp = &pci->pp;
172 struct device *dev = &pdev->dev;
175 pp->root_bus_nr = -1;
176 pp->ops = &armada8k_pcie_host_ops;
178 pp->irq = platform_get_irq(pdev, 0);
180 dev_err(dev, "failed to get irq for port\n");
184 ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
185 IRQF_SHARED, "armada8k-pcie", pcie);
187 dev_err(dev, "failed to request irq %d\n", pp->irq);
191 ret = dw_pcie_host_init(pp);
193 dev_err(dev, "failed to initialize host: %d\n", ret);
200 static const struct dw_pcie_ops dw_pcie_ops = {
201 .link_up = armada8k_pcie_link_up,
204 static int armada8k_pcie_probe(struct platform_device *pdev)
207 struct armada8k_pcie *pcie;
208 struct device *dev = &pdev->dev;
209 struct resource *base;
212 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
216 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
221 pci->ops = &dw_pcie_ops;
223 pcie->clk = devm_clk_get(dev, NULL);
224 if (IS_ERR(pcie->clk))
225 return PTR_ERR(pcie->clk);
227 clk_prepare_enable(pcie->clk);
229 /* Get the dw-pcie unit configuration/control registers base. */
230 base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
231 pci->dbi_base = devm_ioremap_resource(dev, base);
232 if (IS_ERR(pci->dbi_base)) {
233 dev_err(dev, "couldn't remap regs base %p\n", base);
234 ret = PTR_ERR(pci->dbi_base);
238 platform_set_drvdata(pdev, pcie);
240 ret = armada8k_add_pcie_port(pcie, pdev);
247 if (!IS_ERR(pcie->clk))
248 clk_disable_unprepare(pcie->clk);
253 static const struct of_device_id armada8k_pcie_of_match[] = {
254 { .compatible = "marvell,armada8k-pcie", },
258 static struct platform_driver armada8k_pcie_driver = {
259 .probe = armada8k_pcie_probe,
261 .name = "armada8k-pcie",
262 .of_match_table = of_match_ptr(armada8k_pcie_of_match),
265 builtin_platform_driver(armada8k_pcie_driver);