2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/delay.h>
16 #include <linux/types.h>
18 #include "pcie-designware.h"
20 /* PCIe Port Logic registers */
21 #define PLR_OFFSET 0x700
22 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
23 #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
24 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
26 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
28 if ((uintptr_t)addr & (size - 1)) {
30 return PCIBIOS_BAD_REGISTER_NUMBER;
35 } else if (size == 2) {
37 } else if (size == 1) {
41 return PCIBIOS_BAD_REGISTER_NUMBER;
44 return PCIBIOS_SUCCESSFUL;
47 int dw_pcie_write(void __iomem *addr, int size, u32 val)
49 if ((uintptr_t)addr & (size - 1))
50 return PCIBIOS_BAD_REGISTER_NUMBER;
59 return PCIBIOS_BAD_REGISTER_NUMBER;
61 return PCIBIOS_SUCCESSFUL;
64 u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
70 if (pci->ops->read_dbi)
71 return pci->ops->read_dbi(pci, base, reg, size);
73 ret = dw_pcie_read(base + reg, size, &val);
75 dev_err(pci->dev, "read DBI address failed\n");
80 void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
85 if (pci->ops->write_dbi) {
86 pci->ops->write_dbi(pci, base, reg, size, val);
90 ret = dw_pcie_write(base + reg, size, val);
92 dev_err(pci->dev, "write DBI address failed\n");
95 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
97 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
99 return dw_pcie_readl_dbi(pci, offset + reg);
102 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
105 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
107 dw_pcie_writel_dbi(pci, offset + reg, val);
110 void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type,
111 u64 cpu_addr, u64 pci_addr, u32 size)
115 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
116 lower_32_bits(cpu_addr));
117 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
118 upper_32_bits(cpu_addr));
119 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
120 lower_32_bits(cpu_addr + size - 1));
121 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
122 lower_32_bits(pci_addr));
123 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
124 upper_32_bits(pci_addr));
125 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
127 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
131 * Make sure ATU enable takes effect before any subsequent config
134 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
135 val = dw_pcie_readl_ob_unroll(pci, index,
136 PCIE_ATU_UNR_REGION_CTRL2);
137 if (val & PCIE_ATU_ENABLE)
140 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
142 dev_err(pci->dev, "outbound iATU is not being enabled\n");
145 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
146 u64 cpu_addr, u64 pci_addr, u32 size)
150 if (pci->ops->cpu_addr_fixup)
151 cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
153 if (pci->iatu_unroll_enabled) {
154 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
159 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
160 PCIE_ATU_REGION_OUTBOUND | index);
161 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
162 lower_32_bits(cpu_addr));
163 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
164 upper_32_bits(cpu_addr));
165 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
166 lower_32_bits(cpu_addr + size - 1));
167 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
168 lower_32_bits(pci_addr));
169 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
170 upper_32_bits(pci_addr));
171 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
172 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
175 * Make sure ATU enable takes effect before any subsequent config
178 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
179 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
180 if (val == PCIE_ATU_ENABLE)
183 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
185 dev_err(pci->dev, "outbound iATU is not being enabled\n");
188 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
190 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
192 return dw_pcie_readl_dbi(pci, offset + reg);
195 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
198 u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
200 dw_pcie_writel_dbi(pci, offset + reg, val);
203 int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, int bar,
204 u64 cpu_addr, enum dw_pcie_as_type as_type)
209 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
210 lower_32_bits(cpu_addr));
211 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
212 upper_32_bits(cpu_addr));
216 type = PCIE_ATU_TYPE_MEM;
219 type = PCIE_ATU_TYPE_IO;
225 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
226 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
228 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
231 * Make sure ATU enable takes effect before any subsequent config
234 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
235 val = dw_pcie_readl_ib_unroll(pci, index,
236 PCIE_ATU_UNR_REGION_CTRL2);
237 if (val & PCIE_ATU_ENABLE)
240 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
242 dev_err(pci->dev, "inbound iATU is not being enabled\n");
247 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
248 u64 cpu_addr, enum dw_pcie_as_type as_type)
253 if (pci->iatu_unroll_enabled)
254 return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
257 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
259 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
260 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
264 type = PCIE_ATU_TYPE_MEM;
267 type = PCIE_ATU_TYPE_IO;
273 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
274 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
275 | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
278 * Make sure ATU enable takes effect before any subsequent config
281 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
282 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
283 if (val & PCIE_ATU_ENABLE)
286 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
288 dev_err(pci->dev, "inbound iATU is not being enabled\n");
293 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
294 enum dw_pcie_region_type type)
299 case DW_PCIE_REGION_INBOUND:
300 region = PCIE_ATU_REGION_INBOUND;
302 case DW_PCIE_REGION_OUTBOUND:
303 region = PCIE_ATU_REGION_OUTBOUND;
309 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
310 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
313 int dw_pcie_wait_for_link(struct dw_pcie *pci)
317 /* check if the link is up or not */
318 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
319 if (dw_pcie_link_up(pci)) {
320 dev_info(pci->dev, "link up\n");
323 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
326 dev_err(pci->dev, "phy link never came up\n");
331 int dw_pcie_link_up(struct dw_pcie *pci)
335 if (pci->ops->link_up)
336 return pci->ops->link_up(pci);
338 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
339 return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
340 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
343 void dw_pcie_setup(struct dw_pcie *pci)
348 struct device *dev = pci->dev;
349 struct device_node *np = dev->of_node;
351 ret = of_property_read_u32(np, "num-lanes", &lanes);
355 /* set the number of lanes */
356 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
357 val &= ~PORT_LINK_MODE_MASK;
360 val |= PORT_LINK_MODE_1_LANES;
363 val |= PORT_LINK_MODE_2_LANES;
366 val |= PORT_LINK_MODE_4_LANES;
369 val |= PORT_LINK_MODE_8_LANES;
372 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
375 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
377 /* set link width speed control register */
378 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
379 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
382 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
385 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
388 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
391 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
394 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);