2 * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
4 * SPEAr13xx PCIe Glue Layer Source Code
6 * Copyright (C) 2010-2014 ST Microelectronics
7 * Pratyush Anand <pratyush.anand@gmail.com>
8 * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
15 #include <linux/clk.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
25 #include "pcie-designware.h"
27 struct spear13xx_pcie {
29 void __iomem *app_base;
36 u32 app_ctrl_0; /* cr0 */
37 u32 app_ctrl_1; /* cr1 */
38 u32 app_status_0; /* cr2 */
39 u32 app_status_1; /* cr3 */
40 u32 msg_status; /* cr4 */
41 u32 msg_payload; /* cr5 */
42 u32 int_sts; /* cr6 */
43 u32 int_clr; /* cr7 */
44 u32 int_mask; /* cr8 */
45 u32 mst_bmisc; /* cr9 */
46 u32 phy_ctrl; /* cr10 */
47 u32 phy_status; /* cr11 */
48 u32 cxpl_debug_info_0; /* cr12 */
49 u32 cxpl_debug_info_1; /* cr13 */
50 u32 ven_msg_ctrl_0; /* cr14 */
51 u32 ven_msg_ctrl_1; /* cr15 */
52 u32 ven_msg_data_0; /* cr16 */
53 u32 ven_msg_data_1; /* cr17 */
54 u32 ven_msi_0; /* cr18 */
55 u32 ven_msi_1; /* cr19 */
56 u32 mst_rmisc; /* cr20 */
60 #define APP_LTSSM_ENABLE_ID 3
61 #define DEVICE_TYPE_RC (4 << 25)
62 #define MISCTRL_EN_ID 30
63 #define REG_TRANSLATION_ENABLE 31
66 #define XMLH_LINK_UP (1 << 6)
69 #define MSI_CTRL_INT (1 << 26)
71 #define EXP_CAP_ID_OFFSET 0x70
73 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
75 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
77 struct dw_pcie *pci = spear13xx_pcie->pci;
78 struct pcie_port *pp = &pci->pp;
79 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
81 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
83 if (dw_pcie_link_up(pci)) {
84 dev_err(pci->dev, "link already up\n");
91 * this controller support only 128 bytes read size, however its
92 * default value in capability register is 512 bytes. So force
95 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
96 val &= ~PCI_EXP_DEVCTL_READRQ;
97 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
99 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
100 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
103 * if is_gen1 is set then handle it, so that some buggy card
106 if (spear13xx_pcie->is_gen1) {
107 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
109 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
110 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
111 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
112 dw_pcie_write(pci->dbi_base + exp_cap_off +
113 PCI_EXP_LNKCAP, 4, val);
116 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
118 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
119 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
120 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
121 dw_pcie_write(pci->dbi_base + exp_cap_off +
122 PCI_EXP_LNKCTL2, 2, val);
127 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
128 | (1 << APP_LTSSM_ENABLE_ID)
129 | ((u32)1 << REG_TRANSLATION_ENABLE),
130 &app_reg->app_ctrl_0);
132 return dw_pcie_wait_for_link(pci);
135 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
137 struct spear13xx_pcie *spear13xx_pcie = arg;
138 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
139 struct dw_pcie *pci = spear13xx_pcie->pci;
140 struct pcie_port *pp = &pci->pp;
143 status = readl(&app_reg->int_sts);
145 if (status & MSI_CTRL_INT) {
146 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
147 dw_handle_msi_irq(pp);
150 writel(status, &app_reg->int_clr);
155 static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
157 struct dw_pcie *pci = spear13xx_pcie->pci;
158 struct pcie_port *pp = &pci->pp;
159 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
161 /* Enable MSI interrupt */
162 if (IS_ENABLED(CONFIG_PCI_MSI)) {
163 dw_pcie_msi_init(pp);
164 writel(readl(&app_reg->int_mask) |
165 MSI_CTRL_INT, &app_reg->int_mask);
169 static int spear13xx_pcie_link_up(struct dw_pcie *pci)
171 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
172 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
174 if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
180 static void spear13xx_pcie_host_init(struct pcie_port *pp)
182 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
183 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
185 spear13xx_pcie_establish_link(spear13xx_pcie);
186 spear13xx_pcie_enable_interrupts(spear13xx_pcie);
189 static struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
190 .host_init = spear13xx_pcie_host_init,
193 static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
194 struct platform_device *pdev)
196 struct dw_pcie *pci = spear13xx_pcie->pci;
197 struct pcie_port *pp = &pci->pp;
198 struct device *dev = &pdev->dev;
201 pp->irq = platform_get_irq(pdev, 0);
203 dev_err(dev, "failed to get irq\n");
206 ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
207 IRQF_SHARED | IRQF_NO_THREAD,
208 "spear1340-pcie", spear13xx_pcie);
210 dev_err(dev, "failed to request irq %d\n", pp->irq);
214 pp->root_bus_nr = -1;
215 pp->ops = &spear13xx_pcie_host_ops;
217 ret = dw_pcie_host_init(pp);
219 dev_err(dev, "failed to initialize host\n");
226 static const struct dw_pcie_ops dw_pcie_ops = {
227 .link_up = spear13xx_pcie_link_up,
230 static int spear13xx_pcie_probe(struct platform_device *pdev)
232 struct device *dev = &pdev->dev;
234 struct spear13xx_pcie *spear13xx_pcie;
235 struct device_node *np = dev->of_node;
236 struct resource *dbi_base;
239 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
243 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
248 pci->ops = &dw_pcie_ops;
250 spear13xx_pcie->pci = pci;
252 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
253 if (IS_ERR(spear13xx_pcie->phy)) {
254 ret = PTR_ERR(spear13xx_pcie->phy);
255 if (ret == -EPROBE_DEFER)
256 dev_info(dev, "probe deferred\n");
258 dev_err(dev, "couldn't get pcie-phy\n");
262 phy_init(spear13xx_pcie->phy);
264 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
265 if (IS_ERR(spear13xx_pcie->clk)) {
266 dev_err(dev, "couldn't get clk for pcie\n");
267 return PTR_ERR(spear13xx_pcie->clk);
269 ret = clk_prepare_enable(spear13xx_pcie->clk);
271 dev_err(dev, "couldn't enable clk for pcie\n");
275 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
276 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
277 if (IS_ERR(pci->dbi_base)) {
278 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
279 ret = PTR_ERR(pci->dbi_base);
282 spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
284 if (of_property_read_bool(np, "st,pcie-is-gen1"))
285 spear13xx_pcie->is_gen1 = true;
287 platform_set_drvdata(pdev, spear13xx_pcie);
289 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
296 clk_disable_unprepare(spear13xx_pcie->clk);
301 static const struct of_device_id spear13xx_pcie_of_match[] = {
302 { .compatible = "st,spear1340-pcie", },
306 static struct platform_driver spear13xx_pcie_driver = {
307 .probe = spear13xx_pcie_probe,
309 .name = "spear-pcie",
310 .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
314 builtin_platform_driver(spear13xx_pcie_driver);