2 * Support for Faraday Technology FTPC100 PCI Controller
4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
6 * Based on the out-of-tree OpenWRT patch for Cortina Gemini:
7 * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
8 * Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
9 * Based on SL2312 PCI controller code
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irqchip/chained_irq.h>
26 #include <linux/bitops.h>
27 #include <linux/irq.h>
30 * Special configuration registers directly in the first few words
33 #define PCI_IOSIZE 0x00
34 #define PCI_PROT 0x04 /* AHB protection */
35 #define PCI_CTRL 0x08 /* PCI control signal */
36 #define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
37 #define PCI_CONFIG 0x28 /* PCI configuration command register */
40 #define FARADAY_PCI_PMC 0x40 /* Power management control */
41 #define FARADAY_PCI_PMCSR 0x44 /* Power management status */
42 #define FARADAY_PCI_CTRL1 0x48 /* Control register 1 */
43 #define FARADAY_PCI_CTRL2 0x4C /* Control register 2 */
44 #define FARADAY_PCI_MEM1_BASE_SIZE 0x50 /* Memory base and size #1 */
45 #define FARADAY_PCI_MEM2_BASE_SIZE 0x54 /* Memory base and size #2 */
46 #define FARADAY_PCI_MEM3_BASE_SIZE 0x58 /* Memory base and size #3 */
48 /* Bits 31..28 gives INTD..INTA status */
49 #define PCI_CTRL2_INTSTS_SHIFT 28
50 #define PCI_CTRL2_INTMASK_CMDERR BIT(27)
51 #define PCI_CTRL2_INTMASK_PARERR BIT(26)
52 /* Bits 25..22 masks INTD..INTA */
53 #define PCI_CTRL2_INTMASK_SHIFT 22
54 #define PCI_CTRL2_INTMASK_MABRT_RX BIT(21)
55 #define PCI_CTRL2_INTMASK_TABRT_RX BIT(20)
56 #define PCI_CTRL2_INTMASK_TABRT_TX BIT(19)
57 #define PCI_CTRL2_INTMASK_RETRY4 BIT(18)
58 #define PCI_CTRL2_INTMASK_SERR_RX BIT(17)
59 #define PCI_CTRL2_INTMASK_PERR_RX BIT(16)
61 #define PCI_CTRL2_MSTPRI_REQ6 BIT(14)
62 #define PCI_CTRL2_MSTPRI_REQ5 BIT(13)
63 #define PCI_CTRL2_MSTPRI_REQ4 BIT(12)
64 #define PCI_CTRL2_MSTPRI_REQ3 BIT(11)
65 #define PCI_CTRL2_MSTPRI_REQ2 BIT(10)
66 #define PCI_CTRL2_MSTPRI_REQ1 BIT(9)
67 #define PCI_CTRL2_MSTPRI_REQ0 BIT(8)
68 /* Bits 7..4 reserved */
73 * Bit 31..20 defines the PCI side memory base
74 * Bit 19..16 (4 bits) defines the size per below
76 #define FARADAY_PCI_MEMBASE_MASK 0xfff00000
77 #define FARADAY_PCI_MEMSIZE_1MB 0x0
78 #define FARADAY_PCI_MEMSIZE_2MB 0x1
79 #define FARADAY_PCI_MEMSIZE_4MB 0x2
80 #define FARADAY_PCI_MEMSIZE_8MB 0x3
81 #define FARADAY_PCI_MEMSIZE_16MB 0x4
82 #define FARADAY_PCI_MEMSIZE_32MB 0x5
83 #define FARADAY_PCI_MEMSIZE_64MB 0x6
84 #define FARADAY_PCI_MEMSIZE_128MB 0x7
85 #define FARADAY_PCI_MEMSIZE_256MB 0x8
86 #define FARADAY_PCI_MEMSIZE_512MB 0x9
87 #define FARADAY_PCI_MEMSIZE_1GB 0xa
88 #define FARADAY_PCI_MEMSIZE_2GB 0xb
89 #define FARADAY_PCI_MEMSIZE_SHIFT 16
92 * The DMA base is set to 0x0 for all memory segments, it reflects the
93 * fact that the memory of the host system starts at 0x0.
95 #define FARADAY_PCI_DMA_MEM1_BASE 0x00000000
96 #define FARADAY_PCI_DMA_MEM2_BASE 0x00000000
97 #define FARADAY_PCI_DMA_MEM3_BASE 0x00000000
99 /* Defines for PCI configuration command register */
100 #define PCI_CONF_ENABLE BIT(31)
101 #define PCI_CONF_WHERE(r) ((r) & 0xFC)
102 #define PCI_CONF_BUS(b) (((b) & 0xFF) << 16)
103 #define PCI_CONF_DEVICE(d) (((d) & 0x1F) << 11)
104 #define PCI_CONF_FUNCTION(f) (((f) & 0x07) << 8)
107 * struct faraday_pci_variant - encodes IP block differences
108 * @cascaded_irq: this host has cascaded IRQs from an interrupt controller
109 * embedded in the host bridge.
111 struct faraday_pci_variant {
118 struct irq_domain *irqdomain;
122 static int faraday_res_to_memcfg(resource_size_t mem_base,
123 resource_size_t mem_size, u32 *val)
129 outval = FARADAY_PCI_MEMSIZE_1MB;
132 outval = FARADAY_PCI_MEMSIZE_2MB;
135 outval = FARADAY_PCI_MEMSIZE_4MB;
138 outval = FARADAY_PCI_MEMSIZE_8MB;
141 outval = FARADAY_PCI_MEMSIZE_16MB;
144 outval = FARADAY_PCI_MEMSIZE_32MB;
147 outval = FARADAY_PCI_MEMSIZE_64MB;
150 outval = FARADAY_PCI_MEMSIZE_128MB;
153 outval = FARADAY_PCI_MEMSIZE_256MB;
156 outval = FARADAY_PCI_MEMSIZE_512MB;
159 outval = FARADAY_PCI_MEMSIZE_1GB;
162 outval = FARADAY_PCI_MEMSIZE_2GB;
167 outval <<= FARADAY_PCI_MEMSIZE_SHIFT;
169 /* This is probably not good */
170 if (mem_base & ~(FARADAY_PCI_MEMBASE_MASK))
171 pr_warn("truncated PCI memory base\n");
172 /* Translate to bridge side address space */
173 outval |= (mem_base & FARADAY_PCI_MEMBASE_MASK);
174 pr_debug("Translated pci base @%pap, size %pap to config %08x\n",
175 &mem_base, &mem_size, outval);
181 static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
182 unsigned int fn, int config, int size,
185 writel(PCI_CONF_BUS(bus_number) |
186 PCI_CONF_DEVICE(PCI_SLOT(fn)) |
187 PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
188 PCI_CONF_WHERE(config) |
190 p->base + PCI_CONFIG);
192 *value = readl(p->base + PCI_DATA);
195 *value = (*value >> (8 * (config & 3))) & 0xFF;
197 *value = (*value >> (8 * (config & 3))) & 0xFFFF;
199 return PCIBIOS_SUCCESSFUL;
202 static int faraday_pci_read_config(struct pci_bus *bus, unsigned int fn,
203 int config, int size, u32 *value)
205 struct faraday_pci *p = bus->sysdata;
208 "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
209 PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
211 return faraday_raw_pci_read_config(p, bus->number, fn, config, size, value);
214 static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
215 unsigned int fn, int config, int size,
218 int ret = PCIBIOS_SUCCESSFUL;
220 writel(PCI_CONF_BUS(bus_number) |
221 PCI_CONF_DEVICE(PCI_SLOT(fn)) |
222 PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
223 PCI_CONF_WHERE(config) |
225 p->base + PCI_CONFIG);
229 writel(value, p->base + PCI_DATA);
232 writew(value, p->base + PCI_DATA + (config & 3));
235 writeb(value, p->base + PCI_DATA + (config & 3));
238 ret = PCIBIOS_BAD_REGISTER_NUMBER;
244 static int faraday_pci_write_config(struct pci_bus *bus, unsigned int fn,
245 int config, int size, u32 value)
247 struct faraday_pci *p = bus->sysdata;
250 "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
251 PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
253 return faraday_raw_pci_write_config(p, bus->number, fn, config, size,
257 static struct pci_ops faraday_pci_ops = {
258 .read = faraday_pci_read_config,
259 .write = faraday_pci_write_config,
262 static void faraday_pci_ack_irq(struct irq_data *d)
264 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
267 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
268 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
269 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTSTS_SHIFT);
270 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
273 static void faraday_pci_mask_irq(struct irq_data *d)
275 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
278 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
279 reg &= ~((0xF << PCI_CTRL2_INTSTS_SHIFT)
280 | BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT));
281 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
284 static void faraday_pci_unmask_irq(struct irq_data *d)
286 struct faraday_pci *p = irq_data_get_irq_chip_data(d);
289 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
290 reg &= ~(0xF << PCI_CTRL2_INTSTS_SHIFT);
291 reg |= BIT(irqd_to_hwirq(d) + PCI_CTRL2_INTMASK_SHIFT);
292 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, reg);
295 static void faraday_pci_irq_handler(struct irq_desc *desc)
297 struct faraday_pci *p = irq_desc_get_handler_data(desc);
298 struct irq_chip *irqchip = irq_desc_get_chip(desc);
299 unsigned int irq_stat, reg, i;
301 faraday_raw_pci_read_config(p, 0, 0, FARADAY_PCI_CTRL2, 4, ®);
302 irq_stat = reg >> PCI_CTRL2_INTSTS_SHIFT;
304 chained_irq_enter(irqchip, desc);
306 for (i = 0; i < 4; i++) {
307 if ((irq_stat & BIT(i)) == 0)
309 generic_handle_irq(irq_find_mapping(p->irqdomain, i));
312 chained_irq_exit(irqchip, desc);
315 static struct irq_chip faraday_pci_irq_chip = {
317 .irq_ack = faraday_pci_ack_irq,
318 .irq_mask = faraday_pci_mask_irq,
319 .irq_unmask = faraday_pci_unmask_irq,
322 static int faraday_pci_irq_map(struct irq_domain *domain, unsigned int irq,
323 irq_hw_number_t hwirq)
325 irq_set_chip_and_handler(irq, &faraday_pci_irq_chip, handle_level_irq);
326 irq_set_chip_data(irq, domain->host_data);
331 static const struct irq_domain_ops faraday_pci_irqdomain_ops = {
332 .map = faraday_pci_irq_map,
335 static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
337 struct device_node *intc = of_get_next_child(p->dev->of_node, NULL);
342 dev_err(p->dev, "missing child interrupt-controller node\n");
346 /* All PCI IRQs cascade off this one */
347 irq = of_irq_get(intc, 0);
349 dev_err(p->dev, "failed to get parent IRQ\n");
353 p->irqdomain = irq_domain_add_linear(intc, 4,
354 &faraday_pci_irqdomain_ops, p);
356 dev_err(p->dev, "failed to create Gemini PCI IRQ domain\n");
360 irq_set_chained_handler_and_data(irq, faraday_pci_irq_handler, p);
362 for (i = 0; i < 4; i++)
363 irq_create_mapping(p->irqdomain, i);
368 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
369 struct device_node *node)
371 const int na = 3, ns = 2;
375 parser->pna = of_n_addr_cells(node);
376 parser->np = parser->pna + na + ns;
378 parser->range = of_get_property(node, "dma-ranges", &rlen);
381 parser->end = parser->range + rlen / sizeof(__be32);
386 static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
387 struct device_node *np)
389 struct of_pci_range range;
390 struct of_pci_range_parser parser;
391 struct device *dev = p->dev;
393 FARADAY_PCI_MEM1_BASE_SIZE,
394 FARADAY_PCI_MEM2_BASE_SIZE,
395 FARADAY_PCI_MEM3_BASE_SIZE,
400 if (pci_dma_range_parser_init(&parser, np)) {
401 dev_err(dev, "missing dma-ranges property\n");
406 * Get the dma-ranges from the device tree
408 for_each_of_pci_range(&parser, &range) {
409 u64 end = range.pci_addr + range.size - 1;
412 ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
415 "DMA range %d: illegal MEM resource size\n", i);
419 dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
420 i + 1, range.pci_addr, end, val);
422 faraday_raw_pci_write_config(p, 0, 0, confreg[i],
425 dev_err(dev, "ignore extraneous dma-range %d\n", i);
435 static int faraday_pci_probe(struct platform_device *pdev)
437 struct device *dev = &pdev->dev;
438 const struct faraday_pci_variant *variant =
439 of_device_get_match_data(dev);
440 struct resource *regs;
441 resource_size_t io_base;
442 struct resource_entry *win;
443 struct faraday_pci *p;
444 struct resource *mem;
446 struct pci_host_bridge *host;
451 host = devm_pci_alloc_host_bridge(dev, sizeof(*p));
455 host->dev.parent = dev;
456 host->ops = &faraday_pci_ops;
459 host->map_irq = of_irq_parse_and_map_pci;
460 host->swizzle_irq = pci_common_swizzle;
461 p = pci_host_bridge_priv(host);
465 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
466 p->base = devm_ioremap_resource(dev, regs);
468 return PTR_ERR(p->base);
470 ret = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
475 ret = devm_request_pci_bus_resources(dev, &res);
479 /* Get the I/O and memory ranges from DT */
480 resource_list_for_each_entry(win, &res) {
481 switch (resource_type(win->res)) {
484 io->name = "Gemini PCI I/O";
485 if (!faraday_res_to_memcfg(io->start - win->offset,
486 resource_size(io), &val)) {
487 /* setup I/O space size */
488 writel(val, p->base + PCI_IOSIZE);
490 dev_err(dev, "illegal IO mem size\n");
493 ret = pci_remap_iospace(io, io_base);
495 dev_warn(dev, "error %d: failed to map resource %pR\n",
502 mem->name = "Gemini PCI MEM";
511 /* Setup hostbridge */
512 val = readl(p->base + PCI_CTRL);
513 val |= PCI_COMMAND_IO;
514 val |= PCI_COMMAND_MEMORY;
515 val |= PCI_COMMAND_MASTER;
516 writel(val, p->base + PCI_CTRL);
517 /* Mask and clear all interrupts */
518 faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
519 if (variant->cascaded_irq) {
520 ret = faraday_pci_setup_cascaded_irq(p);
522 dev_err(dev, "failed to setup cascaded IRQ\n");
527 ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
531 list_splice_init(&res, &host->windows);
532 ret = pci_scan_root_bus_bridge(host);
534 dev_err(dev, "failed to scan host: %d\n", ret);
539 pci_bus_assign_resources(p->bus);
540 pci_bus_add_devices(p->bus);
541 pci_free_resource_list(&res);
547 * We encode bridge variants here, we have at least two so it doesn't
548 * hurt to have infrastructure to encompass future variants as well.
550 const struct faraday_pci_variant faraday_regular = {
551 .cascaded_irq = true,
554 const struct faraday_pci_variant faraday_dual = {
555 .cascaded_irq = false,
558 static const struct of_device_id faraday_pci_of_match[] = {
560 .compatible = "faraday,ftpci100",
561 .data = &faraday_regular,
564 .compatible = "faraday,ftpci100-dual",
565 .data = &faraday_dual,
570 static struct platform_driver faraday_pci_driver = {
573 .of_match_table = of_match_ptr(faraday_pci_of_match),
574 .suppress_bind_attrs = true,
576 .probe = faraday_pci_probe,
578 builtin_platform_driver(faraday_pci_driver);