2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
30 #include "pcie-designware.h"
32 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
35 struct gpio_desc *reset_gpio;
40 struct regmap *iomuxc_gpr;
41 void __iomem *mem_base;
43 u32 tx_deemph_gen2_3p5db;
44 u32 tx_deemph_gen2_6db;
49 /* PCIe Root Complex registers (memory-mapped) */
50 #define PCIE_RC_LCR 0x7c
51 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
52 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
53 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
55 #define PCIE_RC_LCSR 0x80
57 /* PCIe Port Logic registers (memory-mapped) */
58 #define PL_OFFSET 0x700
59 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
60 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
61 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
62 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
63 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
64 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
65 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
67 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
68 #define PCIE_PHY_CTRL_DATA_LOC 0
69 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
70 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
71 #define PCIE_PHY_CTRL_WR_LOC 18
72 #define PCIE_PHY_CTRL_RD_LOC 19
74 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
75 #define PCIE_PHY_STAT_ACK_LOC 16
77 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
78 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
80 /* PHY registers (not memory-mapped) */
81 #define PCIE_PHY_RX_ASIC_OUT 0x100D
82 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
84 #define PHY_RX_OVRD_IN_LO 0x1005
85 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
86 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
88 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
91 u32 max_iterations = 10;
95 val = readl(dbi_base + PCIE_PHY_STAT);
96 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
103 } while (wait_counter < max_iterations);
108 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
113 val = addr << PCIE_PHY_CTRL_DATA_LOC;
114 writel(val, dbi_base + PCIE_PHY_CTRL);
116 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
117 writel(val, dbi_base + PCIE_PHY_CTRL);
119 ret = pcie_phy_poll_ack(dbi_base, 1);
123 val = addr << PCIE_PHY_CTRL_DATA_LOC;
124 writel(val, dbi_base + PCIE_PHY_CTRL);
126 return pcie_phy_poll_ack(dbi_base, 0);
129 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
130 static int pcie_phy_read(void __iomem *dbi_base, int addr, int *data)
135 ret = pcie_phy_wait_ack(dbi_base, addr);
139 /* assert Read signal */
140 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
141 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
143 ret = pcie_phy_poll_ack(dbi_base, 1);
147 val = readl(dbi_base + PCIE_PHY_STAT);
148 *data = val & 0xffff;
150 /* deassert Read signal */
151 writel(0x00, dbi_base + PCIE_PHY_CTRL);
153 return pcie_phy_poll_ack(dbi_base, 0);
156 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
163 ret = pcie_phy_wait_ack(dbi_base, addr);
167 var = data << PCIE_PHY_CTRL_DATA_LOC;
168 writel(var, dbi_base + PCIE_PHY_CTRL);
171 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
172 writel(var, dbi_base + PCIE_PHY_CTRL);
174 ret = pcie_phy_poll_ack(dbi_base, 1);
178 /* deassert cap data */
179 var = data << PCIE_PHY_CTRL_DATA_LOC;
180 writel(var, dbi_base + PCIE_PHY_CTRL);
182 /* wait for ack de-assertion */
183 ret = pcie_phy_poll_ack(dbi_base, 0);
187 /* assert wr signal */
188 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
189 writel(var, dbi_base + PCIE_PHY_CTRL);
192 ret = pcie_phy_poll_ack(dbi_base, 1);
196 /* deassert wr signal */
197 var = data << PCIE_PHY_CTRL_DATA_LOC;
198 writel(var, dbi_base + PCIE_PHY_CTRL);
200 /* wait for ack de-assertion */
201 ret = pcie_phy_poll_ack(dbi_base, 0);
205 writel(0x0, dbi_base + PCIE_PHY_CTRL);
210 static void imx6_pcie_reset_phy(struct pcie_port *pp)
214 pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
215 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
216 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
217 pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
219 usleep_range(2000, 3000);
221 pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
222 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
223 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
224 pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
227 /* Added for PCI abort handling */
228 static int imx6q_pcie_abort_handler(unsigned long addr,
229 unsigned int fsr, struct pt_regs *regs)
234 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
236 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
237 u32 val, gpr1, gpr12;
240 * If the bootloader already enabled the link we need some special
241 * handling to get the core back into a state where it is safe to
242 * touch it for configuration. As there is no dedicated reset signal
243 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
244 * state before completely disabling LTSSM, which is a prerequisite
245 * for core configuration.
247 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
248 * indication that the bootloader activated the link.
250 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
251 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
253 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
254 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
255 val = readl(pp->dbi_base + PCIE_PL_PFLR);
256 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
257 val |= PCIE_PL_PFLR_FORCE_LINK;
258 writel(val, pp->dbi_base + PCIE_PL_PFLR);
260 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
261 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
264 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
265 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
266 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
267 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
272 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
274 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
277 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
279 dev_err(pp->dev, "unable to enable pcie_phy clock\n");
283 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
285 dev_err(pp->dev, "unable to enable pcie_bus clock\n");
289 ret = clk_prepare_enable(imx6_pcie->pcie);
291 dev_err(pp->dev, "unable to enable pcie clock\n");
295 /* power up core phy and enable ref clock */
296 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
297 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
299 * the async reset input need ref clock to sync internally,
300 * when the ref clock comes after reset, internal synced
301 * reset time is too short, cannot meet the requirement.
302 * add one ~10us delay here.
305 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
306 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
308 /* allow the clocks to stabilize */
309 usleep_range(200, 500);
311 /* Some boards don't have PCIe reset GPIO. */
312 if (imx6_pcie->reset_gpio) {
313 gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 0);
315 gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
320 clk_disable_unprepare(imx6_pcie->pcie_bus);
322 clk_disable_unprepare(imx6_pcie->pcie_phy);
328 static void imx6_pcie_init_phy(struct pcie_port *pp)
330 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
332 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
333 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
335 /* configure constant input signal to the pcie ctrl and phy */
336 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
337 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
338 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
339 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
341 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
342 IMX6Q_GPR8_TX_DEEMPH_GEN1,
343 imx6_pcie->tx_deemph_gen1 << 0);
344 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
345 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
346 imx6_pcie->tx_deemph_gen2_3p5db << 6);
347 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
348 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
349 imx6_pcie->tx_deemph_gen2_6db << 12);
350 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
351 IMX6Q_GPR8_TX_SWING_FULL,
352 imx6_pcie->tx_swing_full << 18);
353 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
354 IMX6Q_GPR8_TX_SWING_LOW,
355 imx6_pcie->tx_swing_low << 25);
358 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
360 unsigned int retries;
363 * Test if the PHY reports that the link is up and also that the LTSSM
364 * training finished. There are three possible states of the link when
365 * this code is called:
366 * 1) The link is DOWN (unlikely)
367 * The link didn't come up yet for some reason. This usually means
368 * we have a real problem somewhere, if it happens with a peripheral
369 * connected. This state calls for inspection of the DEBUG registers.
370 * 2) The link is UP, but still in LTSSM training
371 * Wait for the training to finish, which should take a very short
372 * time. If the training does not finish, we have a problem and we
373 * need to inspect the DEBUG registers. If the training does finish,
374 * the link is up and operating correctly.
375 * 3) The link is UP and no longer in LTSSM training
376 * The link is up and operating correctly.
378 for (retries = 0; retries < 200; retries++) {
379 u32 reg = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
380 if ((reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
381 !(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
383 usleep_range(1000, 2000);
389 static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
392 unsigned int retries;
394 for (retries = 0; retries < 200; retries++) {
395 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
396 /* Test if the speed change finished. */
397 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
399 usleep_range(100, 1000);
402 dev_err(pp->dev, "Speed change timeout\n");
406 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
408 struct pcie_port *pp = arg;
410 return dw_handle_msi_irq(pp);
413 static int imx6_pcie_establish_link(struct pcie_port *pp)
415 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
420 * Force Gen1 operation when starting the link. In case the link is
421 * started in Gen2 mode, there is a possibility the devices on the
422 * bus will not be detected at all. This happens with PCIe switches.
424 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
425 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
426 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
427 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
430 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
431 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
433 ret = imx6_pcie_wait_for_link(pp);
435 dev_info(pp->dev, "Link never came up\n");
439 /* Allow Gen2 mode after the link is up. */
440 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
441 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
442 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
443 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
446 * Start Directed Speed Change so the best possible speed both link
447 * partners support can be negotiated.
449 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
450 tmp |= PORT_LOGIC_SPEED_CHANGE;
451 writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
453 ret = imx6_pcie_wait_for_speed_change(pp);
455 dev_err(pp->dev, "Failed to bring link up!\n");
459 /* Make sure link training is finished as well! */
460 ret = imx6_pcie_wait_for_link(pp);
462 dev_err(pp->dev, "Failed to bring link up!\n");
466 tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
467 dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
472 dev_dbg(pp->dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
473 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
474 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
475 imx6_pcie_reset_phy(pp);
480 static void imx6_pcie_host_init(struct pcie_port *pp)
482 imx6_pcie_assert_core_reset(pp);
484 imx6_pcie_init_phy(pp);
486 imx6_pcie_deassert_core_reset(pp);
488 dw_pcie_setup_rc(pp);
490 imx6_pcie_establish_link(pp);
492 if (IS_ENABLED(CONFIG_PCI_MSI))
493 dw_pcie_msi_init(pp);
496 static int imx6_pcie_link_up(struct pcie_port *pp)
498 return readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) &
499 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
502 static struct pcie_host_ops imx6_pcie_host_ops = {
503 .link_up = imx6_pcie_link_up,
504 .host_init = imx6_pcie_host_init,
507 static int __init imx6_add_pcie_port(struct pcie_port *pp,
508 struct platform_device *pdev)
512 if (IS_ENABLED(CONFIG_PCI_MSI)) {
513 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
514 if (pp->msi_irq <= 0) {
515 dev_err(&pdev->dev, "failed to get MSI irq\n");
519 ret = devm_request_irq(&pdev->dev, pp->msi_irq,
520 imx6_pcie_msi_handler,
521 IRQF_SHARED | IRQF_NO_THREAD,
524 dev_err(&pdev->dev, "failed to request MSI irq\n");
529 pp->root_bus_nr = -1;
530 pp->ops = &imx6_pcie_host_ops;
532 ret = dw_pcie_host_init(pp);
534 dev_err(&pdev->dev, "failed to initialize host\n");
541 static int __init imx6_pcie_probe(struct platform_device *pdev)
543 struct imx6_pcie *imx6_pcie;
544 struct pcie_port *pp;
545 struct resource *dbi_base;
546 struct device_node *node = pdev->dev.of_node;
549 imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
554 pp->dev = &pdev->dev;
556 /* Added for PCI abort handling */
557 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
558 "imprecise external abort");
560 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561 pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
562 if (IS_ERR(pp->dbi_base))
563 return PTR_ERR(pp->dbi_base);
566 imx6_pcie->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
570 imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
571 if (IS_ERR(imx6_pcie->pcie_phy)) {
573 "pcie_phy clock source missing or invalid\n");
574 return PTR_ERR(imx6_pcie->pcie_phy);
577 imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
578 if (IS_ERR(imx6_pcie->pcie_bus)) {
580 "pcie_bus clock source missing or invalid\n");
581 return PTR_ERR(imx6_pcie->pcie_bus);
584 imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
585 if (IS_ERR(imx6_pcie->pcie)) {
587 "pcie clock source missing or invalid\n");
588 return PTR_ERR(imx6_pcie->pcie);
591 /* Grab GPR config register range */
592 imx6_pcie->iomuxc_gpr =
593 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
594 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
595 dev_err(&pdev->dev, "unable to find iomuxc registers\n");
596 return PTR_ERR(imx6_pcie->iomuxc_gpr);
599 /* Grab PCIe PHY Tx Settings */
600 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
601 &imx6_pcie->tx_deemph_gen1))
602 imx6_pcie->tx_deemph_gen1 = 0;
604 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
605 &imx6_pcie->tx_deemph_gen2_3p5db))
606 imx6_pcie->tx_deemph_gen2_3p5db = 0;
608 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
609 &imx6_pcie->tx_deemph_gen2_6db))
610 imx6_pcie->tx_deemph_gen2_6db = 20;
612 if (of_property_read_u32(node, "fsl,tx-swing-full",
613 &imx6_pcie->tx_swing_full))
614 imx6_pcie->tx_swing_full = 127;
616 if (of_property_read_u32(node, "fsl,tx-swing-low",
617 &imx6_pcie->tx_swing_low))
618 imx6_pcie->tx_swing_low = 127;
620 ret = imx6_add_pcie_port(pp, pdev);
624 platform_set_drvdata(pdev, imx6_pcie);
628 static void imx6_pcie_shutdown(struct platform_device *pdev)
630 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
632 /* bring down link, so bootloader gets clean state in case of reboot */
633 imx6_pcie_assert_core_reset(&imx6_pcie->pp);
636 static const struct of_device_id imx6_pcie_of_match[] = {
637 { .compatible = "fsl,imx6q-pcie", },
640 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
642 static struct platform_driver imx6_pcie_driver = {
644 .name = "imx6q-pcie",
645 .of_match_table = imx6_pcie_of_match,
647 .shutdown = imx6_pcie_shutdown,
650 /* Freescale PCIe driver does not allow module unload */
652 static int __init imx6_pcie_init(void)
654 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
656 module_init(imx6_pcie_init);
658 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
659 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
660 MODULE_LICENSE("GPL v2");