2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_device.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/resource.h>
27 #include <linux/signal.h>
28 #include <linux/types.h>
29 #include <linux/interrupt.h>
31 #include "pcie-designware.h"
33 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
35 enum imx6_pcie_variants {
43 bool gpio_active_high;
46 struct clk *pcie_inbound_axi;
49 struct regmap *iomuxc_gpr;
50 enum imx6_pcie_variants variant;
51 void __iomem *mem_base;
53 u32 tx_deemph_gen2_3p5db;
54 u32 tx_deemph_gen2_6db;
60 /* PCIe Root Complex registers (memory-mapped) */
61 #define PCIE_RC_LCR 0x7c
62 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
63 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
64 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
66 #define PCIE_RC_LCSR 0x80
68 /* PCIe Port Logic registers (memory-mapped) */
69 #define PL_OFFSET 0x700
70 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
71 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
72 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
73 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
74 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
75 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
76 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
78 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
79 #define PCIE_PHY_CTRL_DATA_LOC 0
80 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
81 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
82 #define PCIE_PHY_CTRL_WR_LOC 18
83 #define PCIE_PHY_CTRL_RD_LOC 19
85 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
86 #define PCIE_PHY_STAT_ACK_LOC 16
88 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
89 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
91 /* PHY registers (not memory-mapped) */
92 #define PCIE_PHY_RX_ASIC_OUT 0x100D
93 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
95 #define PHY_RX_OVRD_IN_LO 0x1005
96 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
97 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
99 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
102 u32 max_iterations = 10;
103 u32 wait_counter = 0;
106 val = readl(dbi_base + PCIE_PHY_STAT);
107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
114 } while (wait_counter < max_iterations);
119 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
124 val = addr << PCIE_PHY_CTRL_DATA_LOC;
125 writel(val, dbi_base + PCIE_PHY_CTRL);
127 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
128 writel(val, dbi_base + PCIE_PHY_CTRL);
130 ret = pcie_phy_poll_ack(dbi_base, 1);
134 val = addr << PCIE_PHY_CTRL_DATA_LOC;
135 writel(val, dbi_base + PCIE_PHY_CTRL);
137 return pcie_phy_poll_ack(dbi_base, 0);
140 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
141 static int pcie_phy_read(void __iomem *dbi_base, int addr, int *data)
146 ret = pcie_phy_wait_ack(dbi_base, addr);
150 /* assert Read signal */
151 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
152 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
154 ret = pcie_phy_poll_ack(dbi_base, 1);
158 val = readl(dbi_base + PCIE_PHY_STAT);
159 *data = val & 0xffff;
161 /* deassert Read signal */
162 writel(0x00, dbi_base + PCIE_PHY_CTRL);
164 return pcie_phy_poll_ack(dbi_base, 0);
167 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
174 ret = pcie_phy_wait_ack(dbi_base, addr);
178 var = data << PCIE_PHY_CTRL_DATA_LOC;
179 writel(var, dbi_base + PCIE_PHY_CTRL);
182 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
183 writel(var, dbi_base + PCIE_PHY_CTRL);
185 ret = pcie_phy_poll_ack(dbi_base, 1);
189 /* deassert cap data */
190 var = data << PCIE_PHY_CTRL_DATA_LOC;
191 writel(var, dbi_base + PCIE_PHY_CTRL);
193 /* wait for ack de-assertion */
194 ret = pcie_phy_poll_ack(dbi_base, 0);
198 /* assert wr signal */
199 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
200 writel(var, dbi_base + PCIE_PHY_CTRL);
203 ret = pcie_phy_poll_ack(dbi_base, 1);
207 /* deassert wr signal */
208 var = data << PCIE_PHY_CTRL_DATA_LOC;
209 writel(var, dbi_base + PCIE_PHY_CTRL);
211 /* wait for ack de-assertion */
212 ret = pcie_phy_poll_ack(dbi_base, 0);
216 writel(0x0, dbi_base + PCIE_PHY_CTRL);
221 static void imx6_pcie_reset_phy(struct pcie_port *pp)
225 pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
226 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
227 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
228 pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
230 usleep_range(2000, 3000);
232 pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);
233 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
234 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
235 pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);
238 /* Added for PCI abort handling */
239 static int imx6q_pcie_abort_handler(unsigned long addr,
240 unsigned int fsr, struct pt_regs *regs)
245 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
247 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
248 u32 val, gpr1, gpr12;
250 switch (imx6_pcie->variant) {
252 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
253 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
254 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
255 /* Force PCIe PHY reset */
256 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
257 IMX6SX_GPR5_PCIE_BTNRST_RESET,
258 IMX6SX_GPR5_PCIE_BTNRST_RESET);
261 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
262 IMX6Q_GPR1_PCIE_SW_RST,
263 IMX6Q_GPR1_PCIE_SW_RST);
267 * If the bootloader already enabled the link we need some
268 * special handling to get the core back into a state where
269 * it is safe to touch it for configuration. As there is
270 * no dedicated reset signal wired up for MX6QDL, we need
271 * to manually force LTSSM into "detect" state before
272 * completely disabling LTSSM, which is a prerequisite for
273 * core configuration.
275 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we
276 * have a strong indication that the bootloader activated
279 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
280 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
282 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
283 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
284 val = readl(pp->dbi_base + PCIE_PL_PFLR);
285 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
286 val |= PCIE_PL_PFLR_FORCE_LINK;
287 writel(val, pp->dbi_base + PCIE_PL_PFLR);
289 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
290 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
293 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
294 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
295 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
296 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
303 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
305 struct pcie_port *pp = &imx6_pcie->pp;
308 switch (imx6_pcie->variant) {
310 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
312 dev_err(pp->dev, "unable to enable pcie_axi clock\n");
316 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
317 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
319 case IMX6QP: /* FALLTHROUGH */
321 /* power up core phy and enable ref clock */
322 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
323 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
325 * the async reset input need ref clock to sync internally,
326 * when the ref clock comes after reset, internal synced
327 * reset time is too short, cannot meet the requirement.
328 * add one ~10us delay here.
331 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
332 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
339 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
341 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
344 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
346 dev_err(pp->dev, "unable to enable pcie_phy clock\n");
350 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
352 dev_err(pp->dev, "unable to enable pcie_bus clock\n");
356 ret = clk_prepare_enable(imx6_pcie->pcie);
358 dev_err(pp->dev, "unable to enable pcie clock\n");
362 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
364 dev_err(pp->dev, "unable to enable pcie ref clock\n");
368 /* allow the clocks to stabilize */
369 usleep_range(200, 500);
371 /* Some boards don't have PCIe reset GPIO. */
372 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
373 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
374 imx6_pcie->gpio_active_high);
376 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
377 !imx6_pcie->gpio_active_high);
380 switch (imx6_pcie->variant) {
382 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
383 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
386 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
387 IMX6Q_GPR1_PCIE_SW_RST, 0);
389 usleep_range(200, 500);
391 case IMX6Q: /* Nothing to do */
398 clk_disable_unprepare(imx6_pcie->pcie);
400 clk_disable_unprepare(imx6_pcie->pcie_bus);
402 clk_disable_unprepare(imx6_pcie->pcie_phy);
407 static void imx6_pcie_init_phy(struct pcie_port *pp)
409 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
411 if (imx6_pcie->variant == IMX6SX)
412 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
413 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
414 IMX6SX_GPR12_PCIE_RX_EQ_2);
416 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
417 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
419 /* configure constant input signal to the pcie ctrl and phy */
420 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
421 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
422 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
423 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
425 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
426 IMX6Q_GPR8_TX_DEEMPH_GEN1,
427 imx6_pcie->tx_deemph_gen1 << 0);
428 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
429 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
430 imx6_pcie->tx_deemph_gen2_3p5db << 6);
431 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
432 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
433 imx6_pcie->tx_deemph_gen2_6db << 12);
434 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
435 IMX6Q_GPR8_TX_SWING_FULL,
436 imx6_pcie->tx_swing_full << 18);
437 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
438 IMX6Q_GPR8_TX_SWING_LOW,
439 imx6_pcie->tx_swing_low << 25);
442 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
444 /* check if the link is up or not */
445 if (!dw_pcie_wait_for_link(pp))
448 dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
449 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
450 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
454 static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
457 unsigned int retries;
459 for (retries = 0; retries < 200; retries++) {
460 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
461 /* Test if the speed change finished. */
462 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
464 usleep_range(100, 1000);
467 dev_err(pp->dev, "Speed change timeout\n");
471 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
473 struct pcie_port *pp = arg;
475 return dw_handle_msi_irq(pp);
478 static int imx6_pcie_establish_link(struct pcie_port *pp)
480 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
485 * Force Gen1 operation when starting the link. In case the link is
486 * started in Gen2 mode, there is a possibility the devices on the
487 * bus will not be detected at all. This happens with PCIe switches.
489 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
490 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
491 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
492 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
495 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
496 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
498 ret = imx6_pcie_wait_for_link(pp);
500 dev_info(pp->dev, "Link never came up\n");
504 if (imx6_pcie->link_gen == 2) {
505 /* Allow Gen2 mode after the link is up. */
506 tmp = readl(pp->dbi_base + PCIE_RC_LCR);
507 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
508 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
509 writel(tmp, pp->dbi_base + PCIE_RC_LCR);
511 dev_info(pp->dev, "Link: Gen2 disabled\n");
515 * Start Directed Speed Change so the best possible speed both link
516 * partners support can be negotiated.
518 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
519 tmp |= PORT_LOGIC_SPEED_CHANGE;
520 writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
522 ret = imx6_pcie_wait_for_speed_change(pp);
524 dev_err(pp->dev, "Failed to bring link up!\n");
528 /* Make sure link training is finished as well! */
529 ret = imx6_pcie_wait_for_link(pp);
531 dev_err(pp->dev, "Failed to bring link up!\n");
535 tmp = readl(pp->dbi_base + PCIE_RC_LCSR);
536 dev_info(pp->dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
540 dev_dbg(pp->dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
541 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
542 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
543 imx6_pcie_reset_phy(pp);
548 static void imx6_pcie_host_init(struct pcie_port *pp)
550 imx6_pcie_assert_core_reset(pp);
552 imx6_pcie_init_phy(pp);
554 imx6_pcie_deassert_core_reset(pp);
556 dw_pcie_setup_rc(pp);
558 imx6_pcie_establish_link(pp);
560 if (IS_ENABLED(CONFIG_PCI_MSI))
561 dw_pcie_msi_init(pp);
564 static int imx6_pcie_link_up(struct pcie_port *pp)
566 return readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) &
567 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
570 static struct pcie_host_ops imx6_pcie_host_ops = {
571 .link_up = imx6_pcie_link_up,
572 .host_init = imx6_pcie_host_init,
575 static int __init imx6_add_pcie_port(struct pcie_port *pp,
576 struct platform_device *pdev)
580 if (IS_ENABLED(CONFIG_PCI_MSI)) {
581 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
582 if (pp->msi_irq <= 0) {
583 dev_err(&pdev->dev, "failed to get MSI irq\n");
587 ret = devm_request_irq(&pdev->dev, pp->msi_irq,
588 imx6_pcie_msi_handler,
589 IRQF_SHARED | IRQF_NO_THREAD,
592 dev_err(&pdev->dev, "failed to request MSI irq\n");
597 pp->root_bus_nr = -1;
598 pp->ops = &imx6_pcie_host_ops;
600 ret = dw_pcie_host_init(pp);
602 dev_err(&pdev->dev, "failed to initialize host\n");
609 static int __init imx6_pcie_probe(struct platform_device *pdev)
611 struct imx6_pcie *imx6_pcie;
612 struct pcie_port *pp;
613 struct device_node *np = pdev->dev.of_node;
614 struct resource *dbi_base;
615 struct device_node *node = pdev->dev.of_node;
618 imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
623 pp->dev = &pdev->dev;
626 (enum imx6_pcie_variants)of_device_get_match_data(&pdev->dev);
628 /* Added for PCI abort handling */
629 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
630 "imprecise external abort");
632 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
633 pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
634 if (IS_ERR(pp->dbi_base))
635 return PTR_ERR(pp->dbi_base);
638 imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
639 imx6_pcie->gpio_active_high = of_property_read_bool(np,
640 "reset-gpio-active-high");
641 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
642 ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
643 imx6_pcie->gpio_active_high ?
644 GPIOF_OUT_INIT_HIGH :
648 dev_err(&pdev->dev, "unable to get reset gpio\n");
654 imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
655 if (IS_ERR(imx6_pcie->pcie_phy)) {
657 "pcie_phy clock source missing or invalid\n");
658 return PTR_ERR(imx6_pcie->pcie_phy);
661 imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
662 if (IS_ERR(imx6_pcie->pcie_bus)) {
664 "pcie_bus clock source missing or invalid\n");
665 return PTR_ERR(imx6_pcie->pcie_bus);
668 imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
669 if (IS_ERR(imx6_pcie->pcie)) {
671 "pcie clock source missing or invalid\n");
672 return PTR_ERR(imx6_pcie->pcie);
675 if (imx6_pcie->variant == IMX6SX) {
676 imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
678 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
680 "pcie_incbound_axi clock missing or invalid\n");
681 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
685 /* Grab GPR config register range */
686 imx6_pcie->iomuxc_gpr =
687 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
688 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
689 dev_err(&pdev->dev, "unable to find iomuxc registers\n");
690 return PTR_ERR(imx6_pcie->iomuxc_gpr);
693 /* Grab PCIe PHY Tx Settings */
694 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
695 &imx6_pcie->tx_deemph_gen1))
696 imx6_pcie->tx_deemph_gen1 = 0;
698 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
699 &imx6_pcie->tx_deemph_gen2_3p5db))
700 imx6_pcie->tx_deemph_gen2_3p5db = 0;
702 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
703 &imx6_pcie->tx_deemph_gen2_6db))
704 imx6_pcie->tx_deemph_gen2_6db = 20;
706 if (of_property_read_u32(node, "fsl,tx-swing-full",
707 &imx6_pcie->tx_swing_full))
708 imx6_pcie->tx_swing_full = 127;
710 if (of_property_read_u32(node, "fsl,tx-swing-low",
711 &imx6_pcie->tx_swing_low))
712 imx6_pcie->tx_swing_low = 127;
714 /* Limit link speed */
715 ret = of_property_read_u32(pp->dev->of_node, "fsl,max-link-speed",
716 &imx6_pcie->link_gen);
718 imx6_pcie->link_gen = 1;
720 ret = imx6_add_pcie_port(pp, pdev);
724 platform_set_drvdata(pdev, imx6_pcie);
728 static void imx6_pcie_shutdown(struct platform_device *pdev)
730 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
732 /* bring down link, so bootloader gets clean state in case of reboot */
733 imx6_pcie_assert_core_reset(&imx6_pcie->pp);
736 static const struct of_device_id imx6_pcie_of_match[] = {
737 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
738 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
739 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
743 static struct platform_driver imx6_pcie_driver = {
745 .name = "imx6q-pcie",
746 .of_match_table = imx6_pcie_of_match,
748 .shutdown = imx6_pcie_shutdown,
751 static int __init imx6_pcie_init(void)
753 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
755 device_initcall(imx6_pcie_init);