2 * PCIe host controller driver for Freescale Layerscape SoCs
4 * Copyright (C) 2014 Freescale Semiconductor.
6 * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of_pci.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/resource.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include "pcie-designware.h"
28 /* PEX1/2 Misc Ports Status Register */
29 #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
30 #define LTSSM_STATE_SHIFT 20
31 #define LTSSM_STATE_MASK 0x3f
32 #define LTSSM_PCIE_L0 0x11 /* L0 state */
34 /* PEX Internal Configuration Registers */
35 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
36 #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
38 /* PEX LUT registers */
39 #define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
41 struct ls_pcie_drvdata {
44 struct pcie_host_ops *ops;
52 const struct ls_pcie_drvdata *drvdata;
56 #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
58 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
62 header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
65 return header_type == PCI_HEADER_TYPE_BRIDGE;
68 /* Clear multi-function bit */
69 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
71 iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
75 static void ls_pcie_fix_class(struct ls_pcie *pcie)
77 iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
80 static int ls1021_pcie_link_up(struct pcie_port *pp)
83 struct ls_pcie *pcie = to_ls_pcie(pp);
88 regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
89 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
91 if (state < LTSSM_PCIE_L0)
97 static void ls1021_pcie_host_init(struct pcie_port *pp)
99 struct ls_pcie *pcie = to_ls_pcie(pp);
102 pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
104 if (IS_ERR(pcie->scfg)) {
105 dev_err(pp->dev, "No syscfg phandle specified\n");
110 if (of_property_read_u32_array(pp->dev->of_node,
111 "fsl,pcie-scfg", index, 2)) {
115 pcie->index = index[1];
117 dw_pcie_setup_rc(pp);
120 * LS1021A Workaround for internal TKT228622
121 * to fix the INTx hang issue
123 val = ioread32(pcie->dbi + PCIE_STRFMR1);
125 iowrite32(val, pcie->dbi + PCIE_STRFMR1);
128 static int ls_pcie_link_up(struct pcie_port *pp)
130 struct ls_pcie *pcie = to_ls_pcie(pp);
133 state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
134 pcie->drvdata->ltssm_shift) &
137 if (state < LTSSM_PCIE_L0)
143 static void ls_pcie_host_init(struct pcie_port *pp)
145 struct ls_pcie *pcie = to_ls_pcie(pp);
147 iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
148 ls_pcie_fix_class(pcie);
149 ls_pcie_clear_multifunction(pcie);
150 iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
153 static int ls_pcie_msi_host_init(struct pcie_port *pp,
154 struct msi_controller *chip)
156 struct device_node *msi_node;
157 struct device_node *np = pp->dev->of_node;
160 * The MSI domain is set by the generic of_msi_configure(). This
161 * .msi_host_init() function keeps us from doing the default MSI
162 * domain setup in dw_pcie_host_init() and also enforces the
163 * requirement that "msi-parent" exists.
165 msi_node = of_parse_phandle(np, "msi-parent", 0);
167 dev_err(pp->dev, "failed to find msi-parent\n");
174 static struct pcie_host_ops ls1021_pcie_host_ops = {
175 .link_up = ls1021_pcie_link_up,
176 .host_init = ls1021_pcie_host_init,
177 .msi_host_init = ls_pcie_msi_host_init,
180 static struct pcie_host_ops ls_pcie_host_ops = {
181 .link_up = ls_pcie_link_up,
182 .host_init = ls_pcie_host_init,
183 .msi_host_init = ls_pcie_msi_host_init,
186 static struct ls_pcie_drvdata ls1021_drvdata = {
187 .ops = &ls1021_pcie_host_ops,
190 static struct ls_pcie_drvdata ls1043_drvdata = {
191 .lut_offset = 0x10000,
193 .ops = &ls_pcie_host_ops,
196 static struct ls_pcie_drvdata ls2080_drvdata = {
197 .lut_offset = 0x80000,
199 .ops = &ls_pcie_host_ops,
202 static const struct of_device_id ls_pcie_of_match[] = {
203 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
204 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
205 { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
208 MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
210 static int __init ls_add_pcie_port(struct pcie_port *pp,
211 struct platform_device *pdev)
214 struct ls_pcie *pcie = to_ls_pcie(pp);
216 pp->dev = &pdev->dev;
217 pp->dbi_base = pcie->dbi;
218 pp->ops = pcie->drvdata->ops;
220 ret = dw_pcie_host_init(pp);
222 dev_err(pp->dev, "failed to initialize host\n");
229 static int __init ls_pcie_probe(struct platform_device *pdev)
231 const struct of_device_id *match;
232 struct ls_pcie *pcie;
233 struct resource *dbi_base;
236 match = of_match_device(ls_pcie_of_match, &pdev->dev);
240 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
244 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
245 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
246 if (IS_ERR(pcie->dbi)) {
247 dev_err(&pdev->dev, "missing *regs* space\n");
248 return PTR_ERR(pcie->dbi);
251 pcie->drvdata = match->data;
252 pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
254 if (!ls_pcie_is_bridge(pcie))
257 ret = ls_add_pcie_port(&pcie->pp, pdev);
261 platform_set_drvdata(pdev, pcie);
266 static struct platform_driver ls_pcie_driver = {
268 .name = "layerscape-pcie",
269 .of_match_table = ls_pcie_of_match,
273 module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
275 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
276 MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
277 MODULE_LICENSE("GPL v2");