2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/mbus.h>
14 #include <linux/slab.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
22 * PCIe unit register offsets.
24 #define PCIE_DEV_ID_OFF 0x0000
25 #define PCIE_CMD_OFF 0x0004
26 #define PCIE_DEV_REV_OFF 0x0008
27 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
28 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
29 #define PCIE_HEADER_LOG_4_OFF 0x0128
30 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
31 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
32 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
33 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
34 #define PCIE_WIN5_CTRL_OFF 0x1880
35 #define PCIE_WIN5_BASE_OFF 0x1884
36 #define PCIE_WIN5_REMAP_OFF 0x188c
37 #define PCIE_CONF_ADDR_OFF 0x18f8
38 #define PCIE_CONF_ADDR_EN 0x80000000
39 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
40 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
41 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
42 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
43 #define PCIE_CONF_ADDR(bus, devfn, where) \
44 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
45 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
47 #define PCIE_CONF_DATA_OFF 0x18fc
48 #define PCIE_MASK_OFF 0x1910
49 #define PCIE_MASK_ENABLE_INTS 0x0f000000
50 #define PCIE_CTRL_OFF 0x1a00
51 #define PCIE_CTRL_X1_MODE 0x0001
52 #define PCIE_STAT_OFF 0x1a04
53 #define PCIE_STAT_BUS 0xff00
54 #define PCIE_STAT_DEV 0x1f0000
55 #define PCIE_STAT_LINK_DOWN BIT(0)
56 #define PCIE_DEBUG_CTRL 0x1a60
57 #define PCIE_DEBUG_SOFT_RESET BIT(20)
60 * This product ID is registered by Marvell, and used when the Marvell
61 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
62 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
65 #define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
67 /* PCI configuration space of a PCI-to-PCI bridge */
68 struct mvebu_sw_pci_bridge {
83 u8 secondary_latency_timer;
104 struct mvebu_pcie_port;
106 /* Structure representing all PCIe interfaces */
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
111 struct resource realio;
113 struct resource busn;
117 /* Structure representing one PCIe interface */
118 struct mvebu_pcie_port {
121 spinlock_t conf_lock;
127 struct mvebu_sw_pci_bridge bridge;
128 struct device_node *dn;
129 struct mvebu_pcie *pcie;
130 phys_addr_t memwin_base;
132 phys_addr_t iowin_base;
136 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
138 return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
141 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
145 stat = readl(port->base + PCIE_STAT_OFF);
146 stat &= ~PCIE_STAT_BUS;
148 writel(stat, port->base + PCIE_STAT_OFF);
151 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
155 stat = readl(port->base + PCIE_STAT_OFF);
156 stat &= ~PCIE_STAT_DEV;
158 writel(stat, port->base + PCIE_STAT_OFF);
162 * Setup PCIE BARs and Address Decode Wins:
163 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
164 * WIN[0-3] -> DRAM bank[0-3]
166 static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
168 const struct mbus_dram_target_info *dram;
172 dram = mv_mbus_dram_info();
174 /* First, disable and clear BARs and windows. */
175 for (i = 1; i < 3; i++) {
176 writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
177 writel(0, port->base + PCIE_BAR_LO_OFF(i));
178 writel(0, port->base + PCIE_BAR_HI_OFF(i));
181 for (i = 0; i < 5; i++) {
182 writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
183 writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
184 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
187 writel(0, port->base + PCIE_WIN5_CTRL_OFF);
188 writel(0, port->base + PCIE_WIN5_BASE_OFF);
189 writel(0, port->base + PCIE_WIN5_REMAP_OFF);
191 /* Setup windows for DDR banks. Count total DDR size on the fly. */
193 for (i = 0; i < dram->num_cs; i++) {
194 const struct mbus_dram_window *cs = dram->cs + i;
196 writel(cs->base & 0xffff0000,
197 port->base + PCIE_WIN04_BASE_OFF(i));
198 writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
199 writel(((cs->size - 1) & 0xffff0000) |
200 (cs->mbus_attr << 8) |
201 (dram->mbus_dram_target_id << 4) | 1,
202 port->base + PCIE_WIN04_CTRL_OFF(i));
207 /* Round up 'size' to the nearest power of two. */
208 if ((size & (size - 1)) != 0)
209 size = 1 << fls(size);
211 /* Setup BAR[1] to all DRAM banks. */
212 writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
213 writel(0, port->base + PCIE_BAR_HI_OFF(1));
214 writel(((size - 1) & 0xffff0000) | 1,
215 port->base + PCIE_BAR_CTRL_OFF(1));
218 static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
223 /* Point PCIe unit MBUS decode windows to DRAM space. */
224 mvebu_pcie_setup_wins(port);
226 /* Master + slave enable. */
227 cmd = readw(port->base + PCIE_CMD_OFF);
228 cmd |= PCI_COMMAND_IO;
229 cmd |= PCI_COMMAND_MEMORY;
230 cmd |= PCI_COMMAND_MASTER;
231 writew(cmd, port->base + PCIE_CMD_OFF);
233 /* Enable interrupt lines A-D. */
234 mask = readl(port->base + PCIE_MASK_OFF);
235 mask |= PCIE_MASK_ENABLE_INTS;
236 writel(mask, port->base + PCIE_MASK_OFF);
239 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
241 u32 devfn, int where, int size, u32 *val)
243 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
244 port->base + PCIE_CONF_ADDR_OFF);
246 *val = readl(port->base + PCIE_CONF_DATA_OFF);
249 *val = (*val >> (8 * (where & 3))) & 0xff;
251 *val = (*val >> (8 * (where & 3))) & 0xffff;
253 return PCIBIOS_SUCCESSFUL;
256 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
258 u32 devfn, int where, int size, u32 val)
260 int ret = PCIBIOS_SUCCESSFUL;
262 writel(PCIE_CONF_ADDR(bus->number, devfn, where),
263 port->base + PCIE_CONF_ADDR_OFF);
266 writel(val, port->base + PCIE_CONF_DATA_OFF);
268 writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
270 writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
272 ret = PCIBIOS_BAD_REGISTER_NUMBER;
277 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
281 /* Are the new iobase/iolimit values invalid? */
282 if (port->bridge.iolimit < port->bridge.iobase ||
283 port->bridge.iolimitupper < port->bridge.iobaseupper) {
285 /* If a window was configured, remove it */
286 if (port->iowin_base) {
287 mvebu_mbus_del_window(port->iowin_base,
289 port->iowin_base = 0;
290 port->iowin_size = 0;
297 * We read the PCI-to-PCI bridge emulated registers, and
298 * calculate the base address and size of the address decoding
299 * window to setup, according to the PCI-to-PCI bridge
300 * specifications. iobase is the bus address, port->iowin_base
301 * is the CPU address.
303 iobase = ((port->bridge.iobase & 0xF0) << 8) |
304 (port->bridge.iobaseupper << 16);
305 port->iowin_base = port->pcie->io.start + iobase;
306 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
307 (port->bridge.iolimitupper << 16)) -
310 mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
315 pci_ioremap_io(iobase, port->iowin_base);
318 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
320 /* Are the new membase/memlimit values invalid? */
321 if (port->bridge.memlimit < port->bridge.membase) {
323 /* If a window was configured, remove it */
324 if (port->memwin_base) {
325 mvebu_mbus_del_window(port->memwin_base,
327 port->memwin_base = 0;
328 port->memwin_size = 0;
335 * We read the PCI-to-PCI bridge emulated registers, and
336 * calculate the base address and size of the address decoding
337 * window to setup, according to the PCI-to-PCI bridge
340 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
342 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
345 mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
352 * Initialize the configuration space of the PCI-to-PCI bridge
353 * associated with the given PCIe interface.
355 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
357 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
359 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
361 bridge->class = PCI_CLASS_BRIDGE_PCI;
362 bridge->vendor = PCI_VENDOR_ID_MARVELL;
363 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
364 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
365 bridge->cache_line_size = 0x10;
367 /* We support 32 bits I/O addressing */
368 bridge->iobase = PCI_IO_RANGE_TYPE_32;
369 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
373 * Read the configuration space of the PCI-to-PCI bridge associated to
374 * the given PCIe interface.
376 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
377 unsigned int where, int size, u32 *value)
379 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
381 switch (where & ~3) {
383 *value = bridge->device << 16 | bridge->vendor;
387 *value = bridge->command;
390 case PCI_CLASS_REVISION:
391 *value = bridge->class << 16 | bridge->interface << 8 |
395 case PCI_CACHE_LINE_SIZE:
396 *value = bridge->bist << 24 | bridge->header_type << 16 |
397 bridge->latency_timer << 8 | bridge->cache_line_size;
400 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
401 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
404 case PCI_PRIMARY_BUS:
405 *value = (bridge->secondary_latency_timer << 24 |
406 bridge->subordinate_bus << 16 |
407 bridge->secondary_bus << 8 |
408 bridge->primary_bus);
412 *value = (bridge->secondary_status << 16 |
413 bridge->iolimit << 8 |
417 case PCI_MEMORY_BASE:
418 *value = (bridge->memlimit << 16 | bridge->membase);
421 case PCI_PREF_MEMORY_BASE:
422 *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
425 case PCI_PREF_BASE_UPPER32:
426 *value = bridge->prefbaseupper;
429 case PCI_PREF_LIMIT_UPPER32:
430 *value = bridge->preflimitupper;
433 case PCI_IO_BASE_UPPER16:
434 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
437 case PCI_ROM_ADDRESS1:
443 return PCIBIOS_BAD_REGISTER_NUMBER;
447 *value = (*value >> (8 * (where & 3))) & 0xffff;
449 *value = (*value >> (8 * (where & 3))) & 0xff;
451 return PCIBIOS_SUCCESSFUL;
454 /* Write to the PCI-to-PCI bridge configuration space */
455 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
456 unsigned int where, int size, u32 value)
458 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
465 mask = ~(0xffff << ((where & 3) * 8));
467 mask = ~(0xff << ((where & 3) * 8));
469 return PCIBIOS_BAD_REGISTER_NUMBER;
471 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
475 value = (reg & mask) | value << ((where & 3) * 8);
477 switch (where & ~3) {
479 bridge->command = value & 0xffff;
482 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
483 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
488 * We also keep bit 1 set, it is a read-only bit that
489 * indicates we support 32 bits addressing for the
492 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
493 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
494 bridge->secondary_status = value >> 16;
495 mvebu_pcie_handle_iobase_change(port);
498 case PCI_MEMORY_BASE:
499 bridge->membase = value & 0xffff;
500 bridge->memlimit = value >> 16;
501 mvebu_pcie_handle_membase_change(port);
504 case PCI_PREF_MEMORY_BASE:
505 bridge->prefmembase = value & 0xffff;
506 bridge->prefmemlimit = value >> 16;
509 case PCI_PREF_BASE_UPPER32:
510 bridge->prefbaseupper = value;
513 case PCI_PREF_LIMIT_UPPER32:
514 bridge->preflimitupper = value;
517 case PCI_IO_BASE_UPPER16:
518 bridge->iobaseupper = value & 0xffff;
519 bridge->iolimitupper = value >> 16;
520 mvebu_pcie_handle_iobase_change(port);
523 case PCI_PRIMARY_BUS:
524 bridge->primary_bus = value & 0xff;
525 bridge->secondary_bus = (value >> 8) & 0xff;
526 bridge->subordinate_bus = (value >> 16) & 0xff;
527 bridge->secondary_latency_timer = (value >> 24) & 0xff;
528 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
535 return PCIBIOS_SUCCESSFUL;
538 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
540 return sys->private_data;
543 static struct mvebu_pcie_port *
544 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
549 for (i = 0; i < pcie->nports; i++) {
550 struct mvebu_pcie_port *port = &pcie->ports[i];
551 if (bus->number == 0 && port->devfn == devfn)
553 if (bus->number != 0 &&
554 bus->number >= port->bridge.secondary_bus &&
555 bus->number <= port->bridge.subordinate_bus)
562 /* PCI configuration space write function */
563 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
564 int where, int size, u32 val)
566 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
567 struct mvebu_pcie_port *port;
571 port = mvebu_pcie_find_port(pcie, bus, devfn);
573 return PCIBIOS_DEVICE_NOT_FOUND;
575 /* Access the emulated PCI-to-PCI bridge */
576 if (bus->number == 0)
577 return mvebu_sw_pci_bridge_write(port, where, size, val);
580 return PCIBIOS_DEVICE_NOT_FOUND;
583 * On the secondary bus, we don't want to expose any other
584 * device than the device physically connected in the PCIe
585 * slot, visible in slot 0. In slot 1, there's a special
586 * Marvell device that only makes sense when the Armada is
587 * used as a PCIe endpoint.
589 if (bus->number == port->bridge.secondary_bus &&
590 PCI_SLOT(devfn) != 0)
591 return PCIBIOS_DEVICE_NOT_FOUND;
593 /* Access the real PCIe interface */
594 spin_lock_irqsave(&port->conf_lock, flags);
595 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
597 spin_unlock_irqrestore(&port->conf_lock, flags);
602 /* PCI configuration space read function */
603 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
606 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
607 struct mvebu_pcie_port *port;
611 port = mvebu_pcie_find_port(pcie, bus, devfn);
614 return PCIBIOS_DEVICE_NOT_FOUND;
617 /* Access the emulated PCI-to-PCI bridge */
618 if (bus->number == 0)
619 return mvebu_sw_pci_bridge_read(port, where, size, val);
621 if (!port->haslink) {
623 return PCIBIOS_DEVICE_NOT_FOUND;
627 * On the secondary bus, we don't want to expose any other
628 * device than the device physically connected in the PCIe
629 * slot, visible in slot 0. In slot 1, there's a special
630 * Marvell device that only makes sense when the Armada is
631 * used as a PCIe endpoint.
633 if (bus->number == port->bridge.secondary_bus &&
634 PCI_SLOT(devfn) != 0) {
636 return PCIBIOS_DEVICE_NOT_FOUND;
639 /* Access the real PCIe interface */
640 spin_lock_irqsave(&port->conf_lock, flags);
641 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
643 spin_unlock_irqrestore(&port->conf_lock, flags);
648 static struct pci_ops mvebu_pcie_ops = {
649 .read = mvebu_pcie_rd_conf,
650 .write = mvebu_pcie_wr_conf,
653 static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
655 struct mvebu_pcie *pcie = sys_to_pcie(sys);
658 pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
659 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
660 pci_add_resource(&sys->resources, &pcie->busn);
662 for (i = 0; i < pcie->nports; i++) {
663 struct mvebu_pcie_port *port = &pcie->ports[i];
664 mvebu_pcie_setup_hw(port);
670 static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
675 ret = of_irq_map_pci(dev, &oirq);
679 return irq_create_of_mapping(oirq.controller, oirq.specifier,
683 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
685 struct mvebu_pcie *pcie = sys_to_pcie(sys);
688 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
689 &mvebu_pcie_ops, sys, &sys->resources);
693 pci_scan_child_bus(bus);
698 resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
699 const struct resource *res,
700 resource_size_t start,
701 resource_size_t size,
702 resource_size_t align)
704 if (dev->bus->number != 0)
708 * On the PCI-to-PCI bridge side, the I/O windows must have at
709 * least a 64 KB size and be aligned on their size, and the
710 * memory windows must have at least a 1 MB size and be
711 * aligned on their size
713 if (res->flags & IORESOURCE_IO)
714 return round_up(start, max((resource_size_t)SZ_64K, size));
715 else if (res->flags & IORESOURCE_MEM)
716 return round_up(start, max((resource_size_t)SZ_1M, size));
721 static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
725 memset(&hw, 0, sizeof(hw));
727 hw.nr_controllers = 1;
728 hw.private_data = (void **)&pcie;
729 hw.setup = mvebu_pcie_setup;
730 hw.scan = mvebu_pcie_scan_bus;
731 hw.map_irq = mvebu_pcie_map_irq;
732 hw.ops = &mvebu_pcie_ops;
733 hw.align_resource = mvebu_pcie_align_resource;
735 pci_common_init(&hw);
739 * Looks up the list of register addresses encoded into the reg =
740 * <...> property for one that matches the given port/lane. Once
743 static void __iomem * __init
744 mvebu_pcie_map_registers(struct platform_device *pdev,
745 struct device_node *np,
746 struct mvebu_pcie_port *port)
748 struct resource regs;
751 ret = of_address_to_resource(np, 0, ®s);
755 return devm_request_and_ioremap(&pdev->dev, ®s);
758 static int __init mvebu_pcie_probe(struct platform_device *pdev)
760 struct mvebu_pcie *pcie;
761 struct device_node *np = pdev->dev.of_node;
762 struct of_pci_range range;
763 struct of_pci_range_parser parser;
764 struct device_node *child;
767 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
774 if (of_pci_range_parser_init(&parser, np))
777 /* Get the I/O and memory ranges from DT */
778 for_each_of_pci_range(&parser, &range) {
779 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
780 if (restype == IORESOURCE_IO) {
781 of_pci_range_to_resource(&range, np, &pcie->io);
782 of_pci_range_to_resource(&range, np, &pcie->realio);
783 pcie->io.name = "I/O";
784 pcie->realio.start = max_t(resource_size_t,
787 pcie->realio.end = min_t(resource_size_t,
789 range.pci_addr + range.size);
791 if (restype == IORESOURCE_MEM) {
792 of_pci_range_to_resource(&range, np, &pcie->mem);
793 pcie->mem.name = "MEM";
797 /* Get the bus range */
798 ret = of_pci_parse_bus_range(np, &pcie->busn);
800 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
805 for_each_child_of_node(pdev->dev.of_node, child) {
806 if (!of_device_is_available(child))
811 pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
812 sizeof(struct mvebu_pcie_port),
818 for_each_child_of_node(pdev->dev.of_node, child) {
819 struct mvebu_pcie_port *port = &pcie->ports[i];
821 if (!of_device_is_available(child))
826 if (of_property_read_u32(child, "marvell,pcie-port",
829 "ignoring PCIe DT node, missing pcie-port property\n");
833 if (of_property_read_u32(child, "marvell,pcie-lane",
837 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
838 port->port, port->lane);
840 port->devfn = of_pci_get_devfn(child);
844 port->base = mvebu_pcie_map_registers(pdev, child, port);
846 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
847 port->port, port->lane);
851 mvebu_pcie_set_local_dev_nr(port, 1);
853 if (mvebu_pcie_link_up(port)) {
855 dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
856 port->port, port->lane);
859 dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
860 port->port, port->lane);
863 port->clk = of_clk_get_by_name(child, NULL);
864 if (IS_ERR(port->clk)) {
865 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
866 port->port, port->lane);
874 clk_prepare_enable(port->clk);
875 spin_lock_init(&port->conf_lock);
877 mvebu_sw_pci_bridge_init(port);
882 mvebu_pcie_enable(pcie);
887 static const struct of_device_id mvebu_pcie_of_match_table[] = {
888 { .compatible = "marvell,armada-xp-pcie", },
889 { .compatible = "marvell,armada-370-pcie", },
890 { .compatible = "marvell,kirkwood-pcie", },
893 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
895 static struct platform_driver mvebu_pcie_driver = {
897 .owner = THIS_MODULE,
898 .name = "mvebu-pcie",
900 of_match_ptr(mvebu_pcie_of_match_table),
904 static int __init mvebu_pcie_init(void)
906 return platform_driver_probe(&mvebu_pcie_driver,
910 subsys_initcall(mvebu_pcie_init);
912 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
913 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
914 MODULE_LICENSE("GPLv2");