2 * pci-rcar-gen2: internal PCI bus support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Cogent Embedded, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/sizes.h>
22 #include <linux/slab.h>
24 /* AHB-PCI Bridge PCI communication registers */
25 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
27 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
28 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
29 #define RCAR_PCIAHB_PREFETCH0 0x0
30 #define RCAR_PCIAHB_PREFETCH4 0x1
31 #define RCAR_PCIAHB_PREFETCH8 0x2
32 #define RCAR_PCIAHB_PREFETCH16 0x3
34 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
35 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
36 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
37 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
38 #define RCAR_AHBPCI_WIN1_HOST (1 << 30)
39 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
41 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
42 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
43 #define RCAR_PCI_INT_SIGTABORT (1 << 0)
44 #define RCAR_PCI_INT_SIGRETABORT (1 << 1)
45 #define RCAR_PCI_INT_REMABORT (1 << 2)
46 #define RCAR_PCI_INT_PERR (1 << 3)
47 #define RCAR_PCI_INT_SIGSERR (1 << 4)
48 #define RCAR_PCI_INT_RESERR (1 << 5)
49 #define RCAR_PCI_INT_WIN1ERR (1 << 12)
50 #define RCAR_PCI_INT_WIN2ERR (1 << 13)
51 #define RCAR_PCI_INT_A (1 << 16)
52 #define RCAR_PCI_INT_B (1 << 17)
53 #define RCAR_PCI_INT_PME (1 << 19)
54 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
55 RCAR_PCI_INT_SIGRETABORT | \
56 RCAR_PCI_INT_SIGRETABORT | \
57 RCAR_PCI_INT_REMABORT | \
59 RCAR_PCI_INT_SIGSERR | \
60 RCAR_PCI_INT_RESERR | \
61 RCAR_PCI_INT_WIN1ERR | \
64 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
65 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
66 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
67 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
68 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
69 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
70 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
71 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
72 RCAR_AHB_BUS_MMODE_WR_INCR | \
73 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
74 RCAR_AHB_BUS_SMODE_READYCTR)
76 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
77 #define RCAR_USBCTR_USBH_RST (1 << 0)
78 #define RCAR_USBCTR_PCICLK_MASK (1 << 1)
79 #define RCAR_USBCTR_PLL_RST (1 << 2)
80 #define RCAR_USBCTR_DIRPD (1 << 8)
81 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
82 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
83 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
84 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
85 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
86 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
88 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
89 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
90 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
91 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
93 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
95 struct rcar_pci_priv {
98 struct resource io_res;
99 struct resource mem_res;
100 struct resource *cfg_res;
102 unsigned long window_size;
105 /* PCI configuration space operations */
106 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
109 struct pci_sys_data *sys = bus->sysdata;
110 struct rcar_pci_priv *priv = sys->private_data;
113 if (sys->busnr != bus->number || PCI_FUNC(devfn))
116 /* Only one EHCI/OHCI device built-in */
117 slot = PCI_SLOT(devfn);
121 /* bridge logic only has registers to 0x40 */
122 if (slot == 0x0 && where >= 0x40)
125 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
126 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
128 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
129 return priv->reg + (slot >> 1) * 0x100 + where;
132 static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
133 int where, int size, u32 *val)
135 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
138 return PCIBIOS_DEVICE_NOT_FOUND;
145 *val = ioread16(reg);
148 *val = ioread32(reg);
152 return PCIBIOS_SUCCESSFUL;
155 static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
156 int where, int size, u32 val)
158 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
161 return PCIBIOS_DEVICE_NOT_FOUND;
175 return PCIBIOS_SUCCESSFUL;
178 /* PCI interrupt mapping */
179 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
181 struct pci_sys_data *sys = dev->bus->sysdata;
182 struct rcar_pci_priv *priv = sys->private_data;
187 #ifdef CONFIG_PCI_DEBUG
188 /* if debug enabled, then attach an error handler irq to the bridge */
190 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
192 struct rcar_pci_priv *priv = pw;
193 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
195 if (status & RCAR_PCI_INT_ALLERRORS) {
196 dev_err(priv->dev, "error irq: status %08x\n", status);
198 /* clear the error(s) */
199 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
200 priv->reg + RCAR_PCI_INT_STATUS_REG);
207 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
212 ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
213 IRQF_SHARED, "error irq", priv);
215 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
219 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
220 val |= RCAR_PCI_INT_ALLERRORS;
221 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
224 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
227 /* PCI host controller setup */
228 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
230 struct rcar_pci_priv *priv = sys->private_data;
231 void __iomem *reg = priv->reg;
234 pm_runtime_enable(priv->dev);
235 pm_runtime_get_sync(priv->dev);
237 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
238 dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
240 /* Disable Direct Power Down State and assert reset */
241 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
242 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
243 iowrite32(val, reg + RCAR_USBCTR_REG);
246 /* De-assert reset and reset PCIAHB window1 size */
247 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
248 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
250 /* Setup PCIAHB window1 size */
251 switch (priv->window_size) {
253 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
256 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
259 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
262 pr_warn("unknown window size %ld - defaulting to 256M\n",
264 priv->window_size = SZ_256M;
267 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
270 iowrite32(val, reg + RCAR_USBCTR_REG);
272 /* Configure AHB master and slave modes */
273 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
275 /* Configure PCI arbiter */
276 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
277 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
278 RCAR_PCI_ARBITER_PCIBP_MODE;
279 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
281 /* PCI-AHB mapping: 0x40000000 base */
282 iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
283 reg + RCAR_PCIAHB_WIN1_CTR_REG);
285 /* AHB-PCI mapping: OHCI/EHCI registers */
286 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
287 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
289 /* Enable AHB-PCI bridge PCI configuration access */
290 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
291 reg + RCAR_AHBPCI_WIN1_CTR_REG);
292 /* Set PCI-AHB Window1 address */
293 iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
294 reg + PCI_BASE_ADDRESS_1);
295 /* Set AHB-PCI bridge PCI communication area address */
296 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
297 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
299 val = ioread32(reg + PCI_COMMAND);
300 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
301 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
302 iowrite32(val, reg + PCI_COMMAND);
304 /* Enable PCI interrupts */
305 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
306 reg + RCAR_PCI_INT_ENABLE_REG);
309 rcar_pci_setup_errirq(priv);
311 /* Add PCI resources */
312 pci_add_resource(&sys->resources, &priv->io_res);
313 pci_add_resource(&sys->resources, &priv->mem_res);
315 /* Setup bus number based on platform device id */
316 sys->busnr = to_platform_device(priv->dev)->id;
320 static struct pci_ops rcar_pci_ops = {
321 .read = rcar_pci_read_config,
322 .write = rcar_pci_write_config,
325 static int rcar_pci_probe(struct platform_device *pdev)
327 struct resource *cfg_res, *mem_res;
328 struct rcar_pci_priv *priv;
333 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
334 reg = devm_ioremap_resource(&pdev->dev, cfg_res);
338 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
339 if (!mem_res || !mem_res->start)
342 priv = devm_kzalloc(&pdev->dev,
343 sizeof(struct rcar_pci_priv), GFP_KERNEL);
347 priv->mem_res = *mem_res;
349 * The controller does not support/use port I/O,
350 * so setup a dummy port I/O region here.
352 priv->io_res.start = priv->mem_res.start;
353 priv->io_res.end = priv->mem_res.end;
354 priv->io_res.flags = IORESOURCE_IO;
356 priv->cfg_res = cfg_res;
358 priv->irq = platform_get_irq(pdev, 0);
360 priv->dev = &pdev->dev;
363 dev_err(&pdev->dev, "no valid irq found\n");
367 priv->window_size = SZ_1G;
369 hw_private[0] = priv;
370 memset(&hw, 0, sizeof(hw));
371 hw.nr_controllers = ARRAY_SIZE(hw_private);
372 hw.private_data = hw_private;
373 hw.map_irq = rcar_pci_map_irq;
374 hw.ops = &rcar_pci_ops;
375 hw.setup = rcar_pci_setup;
376 pci_common_init_dev(&pdev->dev, &hw);
380 static struct platform_driver rcar_pci_driver = {
382 .name = "pci-rcar-gen2",
383 .owner = THIS_MODULE,
384 .suppress_bind_attrs = true,
386 .probe = rcar_pci_probe,
389 module_platform_driver(rcar_pci_driver);
391 MODULE_LICENSE("GPL v2");
392 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
393 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");