2 * APM X-Gene PCIe Driver
4 * Copyright (c) 2014 Applied Micro Circuits Corporation.
6 * Author: Tanmay Inamdar <tinamdar@apm.com>.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/delay.h>
22 #include <linux/jiffies.h>
23 #include <linux/memblock.h>
24 #include <linux/init.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
33 #define PCIECORE_CTLANDSTATUS 0x50
41 #define OMR1BARL 0x100
42 #define OMR2BARL 0x118
43 #define OMR3BARL 0x130
48 #define BRIDGE_CFG_0 0x2000
49 #define BRIDGE_CFG_4 0x2010
50 #define BRIDGE_STATUS_0 0x2600
52 #define LINK_UP_MASK 0x00000100
53 #define AXI_EP_CFG_ACCESS 0x10000
54 #define EN_COHERENCY 0xF0000000
55 #define EN_REG 0x00000001
56 #define OB_LO_IO 0x00000002
57 #define XGENE_PCIE_VENDORID 0x10E8
58 #define XGENE_PCIE_DEVICEID 0xE004
59 #define SZ_1T (SZ_1G*1024ULL)
60 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
62 #define ROOT_CAP_AND_CTRL 0x5C
65 #define XGENE_PCIE_IP_VER_UNKN 0
66 #define XGENE_PCIE_IP_VER_1 1
68 struct xgene_pcie_port {
69 struct device_node *node;
72 void __iomem *csr_base;
73 void __iomem *cfg_base;
74 unsigned long cfg_addr;
79 static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
81 return readl(port->csr_base + reg);
84 static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
86 writel(val, port->csr_base + reg);
89 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
91 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
95 * When the address bit [17:16] is 2'b01, the Configuration access will be
96 * treated as Type 1 and it will be forwarded to external PCIe device.
98 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
100 struct xgene_pcie_port *port = bus->sysdata;
102 if (bus->number >= (bus->primary + 1))
103 return port->cfg_base + AXI_EP_CFG_ACCESS;
105 return port->cfg_base;
109 * For Configuration request, RTDID register is used as Bus Number,
110 * Device Number and Function number of the header fields.
112 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
114 struct xgene_pcie_port *port = bus->sysdata;
115 unsigned int b, d, f;
122 if (!pci_is_root_bus(bus))
123 rtdid_val = (b << 8) | (d << 3) | f;
125 xgene_pcie_writel(port, RTDID, rtdid_val);
126 /* read the register back to ensure flush */
127 xgene_pcie_readl(port, RTDID);
131 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
132 * the translation from PCI bus to native BUS. Entire DDR region
133 * is mapped into PCIe space using these registers, so it can be
134 * reached by DMA from EP devices. The BAR0/1 of bridge should be
135 * hidden during enumeration to avoid the sizing and resource allocation
138 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
140 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
141 (offset == PCI_BASE_ADDRESS_1)))
147 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
150 if ((pci_is_root_bus(bus) && devfn != 0) ||
151 xgene_pcie_hide_rc_bars(bus, offset))
154 xgene_pcie_set_rtdid_reg(bus, devfn);
155 return xgene_pcie_get_cfg_base(bus) + offset;
158 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
159 int where, int size, u32 *val)
161 struct xgene_pcie_port *port = bus->sysdata;
163 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
165 return PCIBIOS_DEVICE_NOT_FOUND;
168 * The v1 controller has a bug in its Configuration Request
169 * Retry Status (CRS) logic: when CRS is enabled and we read the
170 * Vendor and Device ID of a non-existent device, the controller
171 * fabricates return data of 0xFFFF0001 ("device exists but is not
172 * ready") instead of 0xFFFFFFFF ("device does not exist"). This
173 * causes the PCI core to retry the read until it times out.
174 * Avoid this by not claiming to support CRS.
176 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
177 ((where & ~0x3) == ROOT_CAP_AND_CTRL))
178 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
181 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
183 return PCIBIOS_SUCCESSFUL;
186 static struct pci_ops xgene_pcie_ops = {
187 .map_bus = xgene_pcie_map_bus,
188 .read = xgene_pcie_config_read32,
189 .write = pci_generic_config_write32,
192 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
195 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
199 val32 = xgene_pcie_readl(port, addr);
200 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
201 xgene_pcie_writel(port, addr, val);
203 val32 = xgene_pcie_readl(port, addr + 0x04);
204 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
205 xgene_pcie_writel(port, addr + 0x04, val);
207 val32 = xgene_pcie_readl(port, addr + 0x04);
208 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
209 xgene_pcie_writel(port, addr + 0x04, val);
211 val32 = xgene_pcie_readl(port, addr + 0x08);
212 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
213 xgene_pcie_writel(port, addr + 0x08, val);
218 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
219 u32 *lanes, u32 *speed)
223 port->link_up = false;
224 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
225 if (val32 & LINK_UP_MASK) {
226 port->link_up = true;
227 *speed = PIPE_PHY_RATE_RD(val32);
228 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
229 *lanes = val32 >> 26;
233 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
235 struct device *dev = port->dev;
238 port->clk = clk_get(dev, NULL);
239 if (IS_ERR(port->clk)) {
240 dev_err(dev, "clock not available\n");
244 rc = clk_prepare_enable(port->clk);
246 dev_err(dev, "clock enable failed\n");
253 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
254 struct platform_device *pdev)
256 struct device *dev = port->dev;
257 struct resource *res;
259 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
260 port->csr_base = devm_ioremap_resource(dev, res);
261 if (IS_ERR(port->csr_base))
262 return PTR_ERR(port->csr_base);
264 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
265 port->cfg_base = devm_ioremap_resource(dev, res);
266 if (IS_ERR(port->cfg_base))
267 return PTR_ERR(port->cfg_base);
268 port->cfg_addr = res->start;
273 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
274 struct resource *res, u32 offset,
275 u64 cpu_addr, u64 pci_addr)
277 struct device *dev = port->dev;
278 resource_size_t size = resource_size(res);
279 u64 restype = resource_type(res);
284 if (restype == IORESOURCE_MEM) {
291 if (size >= min_size)
292 mask = ~(size - 1) | flag;
294 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
295 (u64)size, min_size);
297 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
298 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
299 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
300 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
301 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
302 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
305 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
307 u64 addr = port->cfg_addr;
309 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
310 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
311 xgene_pcie_writel(port, CFGCTL, EN_REG);
314 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
315 struct list_head *res,
316 resource_size_t io_base)
318 struct resource_entry *window;
319 struct device *dev = port->dev;
322 resource_list_for_each_entry(window, res) {
323 struct resource *res = window->res;
324 u64 restype = resource_type(res);
326 dev_dbg(dev, "%pR\n", res);
330 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
331 res->start - window->offset);
332 ret = pci_remap_iospace(res, io_base);
337 if (res->flags & IORESOURCE_PREFETCH)
338 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
343 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
351 dev_err(dev, "invalid resource %pR\n", res);
355 xgene_pcie_setup_cfg_reg(port);
359 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
362 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
363 xgene_pcie_writel(port, pim_reg + 0x04,
364 upper_32_bits(pim) | EN_COHERENCY);
365 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
366 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
370 * X-Gene PCIe support maximum 3 inbound memory regions
371 * This function helps to select a region based on size of region
373 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
375 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
376 *ib_reg_mask |= (1 << 1);
380 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
381 *ib_reg_mask |= (1 << 0);
385 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
386 *ib_reg_mask |= (1 << 2);
393 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
394 struct of_pci_range *range, u8 *ib_reg_mask)
396 void __iomem *cfg_base = port->cfg_base;
397 struct device *dev = port->dev;
400 u64 cpu_addr = range->cpu_addr;
401 u64 pci_addr = range->pci_addr;
402 u64 size = range->size;
403 u64 mask = ~(size - 1) | EN_REG;
404 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
408 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
410 dev_warn(dev, "invalid pcie dma-range config\n");
414 if (range->flags & IORESOURCE_PREFETCH)
415 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
417 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
420 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
421 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
422 writel(bar_low, bar_addr);
423 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
427 xgene_pcie_writel(port, IBAR2, bar_low);
428 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
432 xgene_pcie_writel(port, IBAR3L, bar_low);
433 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
434 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
435 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
440 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
443 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
444 struct device_node *node)
446 const int na = 3, ns = 2;
450 parser->pna = of_n_addr_cells(node);
451 parser->np = parser->pna + na + ns;
453 parser->range = of_get_property(node, "dma-ranges", &rlen);
456 parser->end = parser->range + rlen / sizeof(__be32);
461 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
463 struct device_node *np = port->node;
464 struct of_pci_range range;
465 struct of_pci_range_parser parser;
466 struct device *dev = port->dev;
469 if (pci_dma_range_parser_init(&parser, np)) {
470 dev_err(dev, "missing dma-ranges property\n");
474 /* Get the dma-ranges from DT */
475 for_each_of_pci_range(&parser, &range) {
476 u64 end = range.cpu_addr + range.size - 1;
478 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
479 range.flags, range.cpu_addr, end, range.pci_addr);
480 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
485 /* clear BAR configuration which was done by firmware */
486 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
490 for (i = PIM1_1L; i <= CFGCTL; i += 4)
491 xgene_pcie_writel(port, i, 0);
494 static int xgene_pcie_setup(struct xgene_pcie_port *port,
495 struct list_head *res,
496 resource_size_t io_base)
498 struct device *dev = port->dev;
499 u32 val, lanes = 0, speed = 0;
502 xgene_pcie_clear_config(port);
504 /* setup the vendor and device IDs correctly */
505 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
506 xgene_pcie_writel(port, BRIDGE_CFG_0, val);
508 ret = xgene_pcie_map_ranges(port, res, io_base);
512 ret = xgene_pcie_parse_map_dma_ranges(port);
516 xgene_pcie_linkup(port, &lanes, &speed);
518 dev_info(dev, "(rc) link down\n");
520 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
524 static int xgene_pcie_probe_bridge(struct platform_device *pdev)
526 struct device *dev = &pdev->dev;
527 struct device_node *dn = dev->of_node;
528 struct xgene_pcie_port *port;
529 resource_size_t iobase = 0;
534 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
538 port->node = of_node_get(dn);
541 port->version = XGENE_PCIE_IP_VER_UNKN;
542 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
543 port->version = XGENE_PCIE_IP_VER_1;
545 ret = xgene_pcie_map_reg(port, pdev);
549 ret = xgene_pcie_init_port(port);
553 ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
557 ret = devm_request_pci_bus_resources(dev, &res);
561 ret = xgene_pcie_setup(port, &res, iobase);
565 bus = pci_create_root_bus(dev, 0, &xgene_pcie_ops, port, &res);
571 pci_scan_child_bus(bus);
572 pci_assign_unassigned_bus_resources(bus);
573 pci_bus_add_devices(bus);
577 pci_free_resource_list(&res);
581 static const struct of_device_id xgene_pcie_match_table[] = {
582 {.compatible = "apm,xgene-pcie",},
586 static struct platform_driver xgene_pcie_driver = {
588 .name = "xgene-pcie",
589 .of_match_table = of_match_ptr(xgene_pcie_match_table),
591 .probe = xgene_pcie_probe_bridge,
593 builtin_platform_driver(xgene_pcie_driver);