2 * APM X-Gene PCIe Driver
4 * Copyright (c) 2014 Applied Micro Circuits Corporation.
6 * Author: Tanmay Inamdar <tinamdar@apm.com>.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/delay.h>
22 #include <linux/jiffies.h>
23 #include <linux/memblock.h>
24 #include <linux/init.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_pci.h>
29 #include <linux/pci.h>
30 #include <linux/pci-acpi.h>
31 #include <linux/pci-ecam.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
35 #define PCIECORE_CTLANDSTATUS 0x50
43 #define OMR1BARL 0x100
44 #define OMR2BARL 0x118
45 #define OMR3BARL 0x130
50 #define BRIDGE_CFG_0 0x2000
51 #define BRIDGE_CFG_4 0x2010
52 #define BRIDGE_STATUS_0 0x2600
54 #define LINK_UP_MASK 0x00000100
55 #define AXI_EP_CFG_ACCESS 0x10000
56 #define EN_COHERENCY 0xF0000000
57 #define EN_REG 0x00000001
58 #define OB_LO_IO 0x00000002
59 #define XGENE_PCIE_VENDORID 0x10E8
60 #define XGENE_PCIE_DEVICEID 0xE004
61 #define SZ_1T (SZ_1G*1024ULL)
62 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
64 #define ROOT_CAP_AND_CTRL 0x5C
67 #define XGENE_PCIE_IP_VER_UNKN 0
68 #define XGENE_PCIE_IP_VER_1 1
69 #define XGENE_PCIE_IP_VER_2 2
71 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
72 struct xgene_pcie_port {
73 struct device_node *node;
76 void __iomem *csr_base;
77 void __iomem *cfg_base;
78 unsigned long cfg_addr;
83 static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
85 return readl(port->csr_base + reg);
88 static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
90 writel(val, port->csr_base + reg);
93 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
95 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
98 static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
100 struct pci_config_window *cfg;
103 return (struct xgene_pcie_port *)(bus->sysdata);
106 return (struct xgene_pcie_port *)(cfg->priv);
110 * When the address bit [17:16] is 2'b01, the Configuration access will be
111 * treated as Type 1 and it will be forwarded to external PCIe device.
113 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
115 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
117 if (bus->number >= (bus->primary + 1))
118 return port->cfg_base + AXI_EP_CFG_ACCESS;
120 return port->cfg_base;
124 * For Configuration request, RTDID register is used as Bus Number,
125 * Device Number and Function number of the header fields.
127 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
129 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
130 unsigned int b, d, f;
137 if (!pci_is_root_bus(bus))
138 rtdid_val = (b << 8) | (d << 3) | f;
140 xgene_pcie_writel(port, RTDID, rtdid_val);
141 /* read the register back to ensure flush */
142 xgene_pcie_readl(port, RTDID);
146 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
147 * the translation from PCI bus to native BUS. Entire DDR region
148 * is mapped into PCIe space using these registers, so it can be
149 * reached by DMA from EP devices. The BAR0/1 of bridge should be
150 * hidden during enumeration to avoid the sizing and resource allocation
153 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
155 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
156 (offset == PCI_BASE_ADDRESS_1)))
162 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
165 if ((pci_is_root_bus(bus) && devfn != 0) ||
166 xgene_pcie_hide_rc_bars(bus, offset))
169 xgene_pcie_set_rtdid_reg(bus, devfn);
170 return xgene_pcie_get_cfg_base(bus) + offset;
173 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
174 int where, int size, u32 *val)
176 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
178 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
180 return PCIBIOS_DEVICE_NOT_FOUND;
183 * The v1 controller has a bug in its Configuration Request
184 * Retry Status (CRS) logic: when CRS is enabled and we read the
185 * Vendor and Device ID of a non-existent device, the controller
186 * fabricates return data of 0xFFFF0001 ("device exists but is not
187 * ready") instead of 0xFFFFFFFF ("device does not exist"). This
188 * causes the PCI core to retry the read until it times out.
189 * Avoid this by not claiming to support CRS.
191 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
192 ((where & ~0x3) == ROOT_CAP_AND_CTRL))
193 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
196 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
198 return PCIBIOS_SUCCESSFUL;
202 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
203 static int xgene_get_csr_resource(struct acpi_device *adev,
204 struct resource *res)
206 struct device *dev = &adev->dev;
207 struct resource_entry *entry;
208 struct list_head list;
212 INIT_LIST_HEAD(&list);
213 flags = IORESOURCE_MEM;
214 ret = acpi_dev_get_resources(adev, &list,
215 acpi_dev_filter_resource_type_cb,
218 dev_err(dev, "failed to parse _CRS method, error code %d\n",
224 dev_err(dev, "no IO and memory resources present in _CRS\n");
228 entry = list_first_entry(&list, struct resource_entry, node);
230 acpi_dev_free_resource_list(&list);
234 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
236 struct device *dev = cfg->parent;
237 struct acpi_device *adev = to_acpi_device(dev);
238 struct xgene_pcie_port *port;
242 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
246 ret = xgene_get_csr_resource(adev, &csr);
248 dev_err(dev, "can't get CSR resource\n");
251 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
252 if (IS_ERR(port->csr_base))
253 return PTR_ERR(port->csr_base);
255 port->cfg_base = cfg->win;
256 port->version = ipversion;
262 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
264 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
267 struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
269 .init = xgene_v1_pcie_ecam_init,
271 .map_bus = xgene_pcie_map_bus,
272 .read = xgene_pcie_config_read32,
273 .write = pci_generic_config_write,
277 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
279 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
282 struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
284 .init = xgene_v2_pcie_ecam_init,
286 .map_bus = xgene_pcie_map_bus,
287 .read = xgene_pcie_config_read32,
288 .write = pci_generic_config_write,
293 #if defined(CONFIG_PCI_XGENE)
294 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
297 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
301 val32 = xgene_pcie_readl(port, addr);
302 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
303 xgene_pcie_writel(port, addr, val);
305 val32 = xgene_pcie_readl(port, addr + 0x04);
306 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
307 xgene_pcie_writel(port, addr + 0x04, val);
309 val32 = xgene_pcie_readl(port, addr + 0x04);
310 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
311 xgene_pcie_writel(port, addr + 0x04, val);
313 val32 = xgene_pcie_readl(port, addr + 0x08);
314 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
315 xgene_pcie_writel(port, addr + 0x08, val);
320 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
321 u32 *lanes, u32 *speed)
325 port->link_up = false;
326 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
327 if (val32 & LINK_UP_MASK) {
328 port->link_up = true;
329 *speed = PIPE_PHY_RATE_RD(val32);
330 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
331 *lanes = val32 >> 26;
335 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
337 struct device *dev = port->dev;
340 port->clk = clk_get(dev, NULL);
341 if (IS_ERR(port->clk)) {
342 dev_err(dev, "clock not available\n");
346 rc = clk_prepare_enable(port->clk);
348 dev_err(dev, "clock enable failed\n");
355 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
356 struct platform_device *pdev)
358 struct device *dev = port->dev;
359 struct resource *res;
361 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
362 port->csr_base = devm_pci_remap_cfg_resource(dev, res);
363 if (IS_ERR(port->csr_base))
364 return PTR_ERR(port->csr_base);
366 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
367 port->cfg_base = devm_ioremap_resource(dev, res);
368 if (IS_ERR(port->cfg_base))
369 return PTR_ERR(port->cfg_base);
370 port->cfg_addr = res->start;
375 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
376 struct resource *res, u32 offset,
377 u64 cpu_addr, u64 pci_addr)
379 struct device *dev = port->dev;
380 resource_size_t size = resource_size(res);
381 u64 restype = resource_type(res);
386 if (restype == IORESOURCE_MEM) {
393 if (size >= min_size)
394 mask = ~(size - 1) | flag;
396 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
397 (u64)size, min_size);
399 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
400 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
401 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
402 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
403 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
404 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
407 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
409 u64 addr = port->cfg_addr;
411 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
412 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
413 xgene_pcie_writel(port, CFGCTL, EN_REG);
416 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
417 struct list_head *res,
418 resource_size_t io_base)
420 struct resource_entry *window;
421 struct device *dev = port->dev;
424 resource_list_for_each_entry(window, res) {
425 struct resource *res = window->res;
426 u64 restype = resource_type(res);
428 dev_dbg(dev, "%pR\n", res);
432 xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
433 res->start - window->offset);
434 ret = pci_remap_iospace(res, io_base);
439 if (res->flags & IORESOURCE_PREFETCH)
440 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
445 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
453 dev_err(dev, "invalid resource %pR\n", res);
457 xgene_pcie_setup_cfg_reg(port);
461 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
464 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
465 xgene_pcie_writel(port, pim_reg + 0x04,
466 upper_32_bits(pim) | EN_COHERENCY);
467 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
468 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
472 * X-Gene PCIe support maximum 3 inbound memory regions
473 * This function helps to select a region based on size of region
475 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
477 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
478 *ib_reg_mask |= (1 << 1);
482 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
483 *ib_reg_mask |= (1 << 0);
487 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
488 *ib_reg_mask |= (1 << 2);
495 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
496 struct of_pci_range *range, u8 *ib_reg_mask)
498 void __iomem *cfg_base = port->cfg_base;
499 struct device *dev = port->dev;
502 u64 cpu_addr = range->cpu_addr;
503 u64 pci_addr = range->pci_addr;
504 u64 size = range->size;
505 u64 mask = ~(size - 1) | EN_REG;
506 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
510 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
512 dev_warn(dev, "invalid pcie dma-range config\n");
516 if (range->flags & IORESOURCE_PREFETCH)
517 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
519 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
522 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
523 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
524 writel(bar_low, bar_addr);
525 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
529 xgene_pcie_writel(port, IBAR2, bar_low);
530 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
534 xgene_pcie_writel(port, IBAR3L, bar_low);
535 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
536 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
537 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
542 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
545 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
546 struct device_node *node)
548 const int na = 3, ns = 2;
552 parser->pna = of_n_addr_cells(node);
553 parser->np = parser->pna + na + ns;
555 parser->range = of_get_property(node, "dma-ranges", &rlen);
558 parser->end = parser->range + rlen / sizeof(__be32);
563 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
565 struct device_node *np = port->node;
566 struct of_pci_range range;
567 struct of_pci_range_parser parser;
568 struct device *dev = port->dev;
571 if (pci_dma_range_parser_init(&parser, np)) {
572 dev_err(dev, "missing dma-ranges property\n");
576 /* Get the dma-ranges from DT */
577 for_each_of_pci_range(&parser, &range) {
578 u64 end = range.cpu_addr + range.size - 1;
580 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
581 range.flags, range.cpu_addr, end, range.pci_addr);
582 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
587 /* clear BAR configuration which was done by firmware */
588 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
592 for (i = PIM1_1L; i <= CFGCTL; i += 4)
593 xgene_pcie_writel(port, i, 0);
596 static int xgene_pcie_setup(struct xgene_pcie_port *port,
597 struct list_head *res,
598 resource_size_t io_base)
600 struct device *dev = port->dev;
601 u32 val, lanes = 0, speed = 0;
604 xgene_pcie_clear_config(port);
606 /* setup the vendor and device IDs correctly */
607 val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
608 xgene_pcie_writel(port, BRIDGE_CFG_0, val);
610 ret = xgene_pcie_map_ranges(port, res, io_base);
614 ret = xgene_pcie_parse_map_dma_ranges(port);
618 xgene_pcie_linkup(port, &lanes, &speed);
620 dev_info(dev, "(rc) link down\n");
622 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
626 static struct pci_ops xgene_pcie_ops = {
627 .map_bus = xgene_pcie_map_bus,
628 .read = xgene_pcie_config_read32,
629 .write = pci_generic_config_write32,
632 static int xgene_pcie_probe_bridge(struct platform_device *pdev)
634 struct device *dev = &pdev->dev;
635 struct device_node *dn = dev->of_node;
636 struct xgene_pcie_port *port;
637 resource_size_t iobase = 0;
638 struct pci_bus *bus, *child;
639 struct pci_host_bridge *bridge;
643 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
647 port = pci_host_bridge_priv(bridge);
649 port->node = of_node_get(dn);
652 port->version = XGENE_PCIE_IP_VER_UNKN;
653 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
654 port->version = XGENE_PCIE_IP_VER_1;
656 ret = xgene_pcie_map_reg(port, pdev);
660 ret = xgene_pcie_init_port(port);
664 ret = of_pci_get_host_bridge_resources(dn, 0, 0xff, &res, &iobase);
668 ret = devm_request_pci_bus_resources(dev, &res);
672 ret = xgene_pcie_setup(port, &res, iobase);
676 list_splice_init(&res, &bridge->windows);
677 bridge->dev.parent = dev;
678 bridge->sysdata = port;
680 bridge->ops = &xgene_pcie_ops;
681 bridge->map_irq = of_irq_parse_and_map_pci;
682 bridge->swizzle_irq = pci_common_swizzle;
684 ret = pci_scan_root_bus_bridge(bridge);
690 pci_scan_child_bus(bus);
691 pci_assign_unassigned_bus_resources(bus);
692 list_for_each_entry(child, &bus->children, node)
693 pcie_bus_configure_settings(child);
694 pci_bus_add_devices(bus);
698 pci_free_resource_list(&res);
702 static const struct of_device_id xgene_pcie_match_table[] = {
703 {.compatible = "apm,xgene-pcie",},
707 static struct platform_driver xgene_pcie_driver = {
709 .name = "xgene-pcie",
710 .of_match_table = of_match_ptr(xgene_pcie_match_table),
711 .suppress_bind_attrs = true,
713 .probe = xgene_pcie_probe_bridge,
715 builtin_platform_driver(xgene_pcie_driver);