2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/types.h>
25 #include "pcie-designware.h"
27 /* Synopsis specific PCIE configuration registers */
28 #define PCIE_PORT_LINK_CONTROL 0x710
29 #define PORT_LINK_MODE_MASK (0x3f << 16)
30 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
31 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
32 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
35 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
36 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
37 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
38 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
41 #define PCIE_MSI_ADDR_LO 0x820
42 #define PCIE_MSI_ADDR_HI 0x824
43 #define PCIE_MSI_INTR0_ENABLE 0x828
44 #define PCIE_MSI_INTR0_MASK 0x82C
45 #define PCIE_MSI_INTR0_STATUS 0x830
47 #define PCIE_ATU_VIEWPORT 0x900
48 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
49 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
50 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
51 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
52 #define PCIE_ATU_CR1 0x904
53 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
54 #define PCIE_ATU_TYPE_IO (0x2 << 0)
55 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
56 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
57 #define PCIE_ATU_CR2 0x908
58 #define PCIE_ATU_ENABLE (0x1 << 31)
59 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
60 #define PCIE_ATU_LOWER_BASE 0x90C
61 #define PCIE_ATU_UPPER_BASE 0x910
62 #define PCIE_ATU_LIMIT 0x914
63 #define PCIE_ATU_LOWER_TARGET 0x918
64 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
65 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
66 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
67 #define PCIE_ATU_UPPER_TARGET 0x91C
69 static struct hw_pci dw_pci;
71 static unsigned long global_io_offset;
73 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75 return sys->private_data;
78 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
83 *val = (*val >> (8 * (where & 3))) & 0xff;
85 *val = (*val >> (8 * (where & 3))) & 0xffff;
87 return PCIBIOS_BAD_REGISTER_NUMBER;
89 return PCIBIOS_SUCCESSFUL;
92 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
97 writew(val, addr + (where & 2));
99 writeb(val, addr + (where & 3));
101 return PCIBIOS_BAD_REGISTER_NUMBER;
103 return PCIBIOS_SUCCESSFUL;
106 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
108 if (pp->ops->readl_rc)
109 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
111 *val = readl(pp->dbi_base + reg);
114 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
116 if (pp->ops->writel_rc)
117 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
119 writel(val, pp->dbi_base + reg);
122 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
127 if (pp->ops->rd_own_conf)
128 ret = pp->ops->rd_own_conf(pp, where, size, val);
130 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
136 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
141 if (pp->ops->wr_own_conf)
142 ret = pp->ops->wr_own_conf(pp, where, size, val);
144 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
150 static struct irq_chip dw_msi_irq_chip = {
152 .irq_enable = unmask_msi_irq,
153 .irq_disable = mask_msi_irq,
154 .irq_mask = mask_msi_irq,
155 .irq_unmask = unmask_msi_irq,
158 /* MSI int handler */
159 void dw_handle_msi_irq(struct pcie_port *pp)
164 for (i = 0; i < MAX_MSI_CTRLS; i++) {
165 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
169 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
170 irq = irq_find_mapping(pp->irq_domain,
172 dw_pcie_wr_own_conf(pp,
173 PCIE_MSI_INTR0_STATUS + i * 12,
175 generic_handle_irq(irq);
182 void dw_pcie_msi_init(struct pcie_port *pp)
184 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
186 /* program the msi_data */
187 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
188 virt_to_phys((void *)pp->msi_data));
189 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
192 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
197 pos = find_next_zero_bit(pp->msi_irq_in_use,
199 /*if you have reached to the end then get out from here.*/
200 if (pos == MAX_MSI_IRQS)
203 * Check if this position is at correct offset.nvec is always a
204 * power of two. pos0 must be nvec bit aligned.
207 pos += msgvec - (pos % msgvec);
216 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
217 unsigned int nvec, unsigned int pos)
219 unsigned int i, res, bit, val;
221 for (i = 0; i < nvec; i++) {
222 irq_set_msi_desc_off(irq_base, i, NULL);
223 clear_bit(pos + i, pp->msi_irq_in_use);
224 /* Disable corresponding interrupt on MSI controller */
225 res = ((pos + i) / 32) * 12;
226 bit = (pos + i) % 32;
227 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
229 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
233 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
235 int res, bit, irq, pos0, pos1, i;
237 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
244 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
246 if (pos0 % no_irqs) {
247 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
251 pos1 = find_next_bit(pp->msi_irq_in_use,
253 /* there must be nvec number of consecutive free bits */
254 while ((pos1 - pos0) < no_irqs) {
255 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
257 pos1 = find_next_bit(pp->msi_irq_in_use,
262 irq = irq_find_mapping(pp->irq_domain, pos0);
267 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
268 * descs so there is no need to allocate descs here. We can therefore
269 * assume that if irq_find_mapping above returns non-zero, then the
270 * descs are also successfully allocated.
273 for (i = 0; i < no_irqs; i++) {
274 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
275 clear_irq_range(pp, irq, i, pos0);
278 set_bit(pos0 + i, pp->msi_irq_in_use);
279 /*Enable corresponding interrupt in MSI interrupt controller */
280 res = ((pos0 + i) / 32) * 12;
281 bit = (pos0 + i) % 32;
282 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
284 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
295 static void clear_irq(unsigned int irq)
297 unsigned int pos, nvec;
298 struct msi_desc *msi;
299 struct pcie_port *pp;
300 struct irq_data *data = irq_get_irq_data(irq);
302 /* get the port structure */
303 msi = irq_data_get_msi(data);
304 pp = sys_to_pcie(msi->dev->bus->sysdata);
310 /* undo what was done in assign_irq */
312 nvec = 1 << msi->msi_attrib.multiple;
314 clear_irq_range(pp, irq, nvec, pos);
316 /* all irqs cleared; reset attributes */
318 msi->msi_attrib.multiple = 0;
321 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
322 struct msi_desc *desc)
324 int irq, pos, msgvec;
327 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
334 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
336 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
338 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
342 irq = assign_irq((1 << msgvec), desc, &pos);
347 * write_msi_msg() will update PCI_MSI_FLAGS so there is
348 * no need to explicitly call pci_write_config_word().
350 desc->msi_attrib.multiple = msgvec;
352 msg.address_lo = virt_to_phys((void *)pp->msi_data);
353 msg.address_hi = 0x0;
355 write_msi_msg(irq, &msg);
360 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
365 static struct msi_chip dw_pcie_msi_chip = {
366 .setup_irq = dw_msi_setup_irq,
367 .teardown_irq = dw_msi_teardown_irq,
370 int dw_pcie_link_up(struct pcie_port *pp)
372 if (pp->ops->link_up)
373 return pp->ops->link_up(pp);
378 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
379 irq_hw_number_t hwirq)
381 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
382 irq_set_chip_data(irq, domain->host_data);
383 set_irq_flags(irq, IRQF_VALID);
388 static const struct irq_domain_ops msi_domain_ops = {
389 .map = dw_pcie_msi_map,
392 int __init dw_pcie_host_init(struct pcie_port *pp)
394 struct device_node *np = pp->dev->of_node;
395 struct of_pci_range range;
396 struct of_pci_range_parser parser;
400 if (of_pci_range_parser_init(&parser, np)) {
401 dev_err(pp->dev, "missing ranges property\n");
405 /* Get the I/O and memory ranges from DT */
406 for_each_of_pci_range(&parser, &range) {
407 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
408 if (restype == IORESOURCE_IO) {
409 of_pci_range_to_resource(&range, np, &pp->io);
411 pp->io.start = max_t(resource_size_t,
413 range.pci_addr + global_io_offset);
414 pp->io.end = min_t(resource_size_t,
416 range.pci_addr + range.size
418 pp->config.io_size = resource_size(&pp->io);
419 pp->config.io_bus_addr = range.pci_addr;
420 pp->io_base = range.cpu_addr;
422 if (restype == IORESOURCE_MEM) {
423 of_pci_range_to_resource(&range, np, &pp->mem);
424 pp->mem.name = "MEM";
425 pp->config.mem_size = resource_size(&pp->mem);
426 pp->config.mem_bus_addr = range.pci_addr;
429 of_pci_range_to_resource(&range, np, &pp->cfg);
430 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
431 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
436 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
437 resource_size(&pp->cfg));
439 dev_err(pp->dev, "error with ioremap\n");
444 pp->cfg0_base = pp->cfg.start;
445 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
446 pp->mem_base = pp->mem.start;
448 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
449 pp->config.cfg0_size);
450 if (!pp->va_cfg0_base) {
451 dev_err(pp->dev, "error with ioremap in function\n");
454 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
455 pp->config.cfg1_size);
456 if (!pp->va_cfg1_base) {
457 dev_err(pp->dev, "error with ioremap\n");
461 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
462 dev_err(pp->dev, "Failed to parse the number of lanes\n");
466 if (IS_ENABLED(CONFIG_PCI_MSI)) {
467 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
468 MAX_MSI_IRQS, &msi_domain_ops,
470 if (!pp->irq_domain) {
471 dev_err(pp->dev, "irq domain init failed\n");
475 for (i = 0; i < MAX_MSI_IRQS; i++)
476 irq_create_mapping(pp->irq_domain, i);
479 if (pp->ops->host_init)
480 pp->ops->host_init(pp);
482 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
484 /* program correct class for RC */
485 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
487 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
488 val |= PORT_LOGIC_SPEED_CHANGE;
489 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
491 dw_pci.nr_controllers = 1;
492 dw_pci.private_data = (void **)&pp;
494 pci_common_init_dev(pp->dev, &dw_pci);
495 pci_assign_unassigned_resources();
496 #ifdef CONFIG_PCI_DOMAINS
503 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
505 /* Program viewport 0 : OUTBOUND : CFG0 */
506 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
508 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
509 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
510 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
512 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
513 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
514 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
515 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
518 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
520 /* Program viewport 1 : OUTBOUND : CFG1 */
521 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
523 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
524 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
525 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
526 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
528 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
529 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
530 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
533 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
535 /* Program viewport 0 : OUTBOUND : MEM */
536 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
538 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
539 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
540 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
541 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
543 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
544 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
545 PCIE_ATU_UPPER_TARGET);
546 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
549 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
551 /* Program viewport 1 : OUTBOUND : IO */
552 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
554 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
555 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
556 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
557 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
559 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
560 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
561 PCIE_ATU_UPPER_TARGET);
562 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
565 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
566 u32 devfn, int where, int size, u32 *val)
568 int ret = PCIBIOS_SUCCESSFUL;
571 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
572 PCIE_ATU_FUNC(PCI_FUNC(devfn));
573 address = where & ~0x3;
575 if (bus->parent->number == pp->root_bus_nr) {
576 dw_pcie_prog_viewport_cfg0(pp, busdev);
577 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
579 dw_pcie_prog_viewport_mem_outbound(pp);
581 dw_pcie_prog_viewport_cfg1(pp, busdev);
582 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
584 dw_pcie_prog_viewport_io_outbound(pp);
590 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
591 u32 devfn, int where, int size, u32 val)
593 int ret = PCIBIOS_SUCCESSFUL;
596 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
597 PCIE_ATU_FUNC(PCI_FUNC(devfn));
598 address = where & ~0x3;
600 if (bus->parent->number == pp->root_bus_nr) {
601 dw_pcie_prog_viewport_cfg0(pp, busdev);
602 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
604 dw_pcie_prog_viewport_mem_outbound(pp);
606 dw_pcie_prog_viewport_cfg1(pp, busdev);
607 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
609 dw_pcie_prog_viewport_io_outbound(pp);
615 static int dw_pcie_valid_config(struct pcie_port *pp,
616 struct pci_bus *bus, int dev)
618 /* If there is no link, then there is no device */
619 if (bus->number != pp->root_bus_nr) {
620 if (!dw_pcie_link_up(pp))
624 /* access only one slot on each root port */
625 if (bus->number == pp->root_bus_nr && dev > 0)
629 * do not read more than one device on the bus directly attached
630 * to RC's (Virtual Bridge's) DS side.
632 if (bus->primary == pp->root_bus_nr && dev > 0)
638 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
641 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
650 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
652 return PCIBIOS_DEVICE_NOT_FOUND;
655 spin_lock_irqsave(&pp->conf_lock, flags);
656 if (bus->number != pp->root_bus_nr)
657 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
660 ret = dw_pcie_rd_own_conf(pp, where, size, val);
661 spin_unlock_irqrestore(&pp->conf_lock, flags);
666 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
667 int where, int size, u32 val)
669 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
678 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
679 return PCIBIOS_DEVICE_NOT_FOUND;
681 spin_lock_irqsave(&pp->conf_lock, flags);
682 if (bus->number != pp->root_bus_nr)
683 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
686 ret = dw_pcie_wr_own_conf(pp, where, size, val);
687 spin_unlock_irqrestore(&pp->conf_lock, flags);
692 static struct pci_ops dw_pcie_ops = {
693 .read = dw_pcie_rd_conf,
694 .write = dw_pcie_wr_conf,
697 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
699 struct pcie_port *pp;
701 pp = sys_to_pcie(sys);
706 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
707 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
708 pci_ioremap_io(global_io_offset, pp->io_base);
709 global_io_offset += SZ_64K;
710 pci_add_resource_offset(&sys->resources, &pp->io,
714 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
715 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
720 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
723 struct pcie_port *pp = sys_to_pcie(sys);
726 pp->root_bus_nr = sys->busnr;
727 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
728 sys, &sys->resources);
737 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
739 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
742 irq = of_irq_parse_and_map_pci(dev, slot, pin);
749 static void dw_pcie_add_bus(struct pci_bus *bus)
751 if (IS_ENABLED(CONFIG_PCI_MSI)) {
752 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
754 dw_pcie_msi_chip.dev = pp->dev;
755 bus->msi = &dw_pcie_msi_chip;
759 static struct hw_pci dw_pci = {
760 .setup = dw_pcie_setup,
761 .scan = dw_pcie_scan_bus,
762 .map_irq = dw_pcie_map_irq,
763 .add_bus = dw_pcie_add_bus,
766 void dw_pcie_setup_rc(struct pcie_port *pp)
768 struct pcie_port_info *config = &pp->config;
773 /* set the number of lanes */
774 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
775 val &= ~PORT_LINK_MODE_MASK;
778 val |= PORT_LINK_MODE_1_LANES;
781 val |= PORT_LINK_MODE_2_LANES;
784 val |= PORT_LINK_MODE_4_LANES;
787 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
789 /* set link width speed control register */
790 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
791 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
794 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
797 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
800 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
803 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
806 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
807 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
809 /* setup interrupt pins */
810 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
813 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
815 /* setup bus numbers */
816 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
819 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
821 /* setup memory base, memory limit */
822 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
823 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
824 val = memlimit | membase;
825 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
827 /* setup command register */
828 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
830 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
831 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
832 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
835 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
836 MODULE_DESCRIPTION("Designware PCIe host controller driver");
837 MODULE_LICENSE("GPL v2");