2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/pci.h>
21 #include <linux/pci_regs.h>
22 #include <linux/types.h>
24 #include "pcie-designware.h"
26 /* Synopsis specific PCIE configuration registers */
27 #define PCIE_PORT_LINK_CONTROL 0x710
28 #define PORT_LINK_MODE_MASK (0x3f << 16)
29 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
30 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
31 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
33 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
34 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
35 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
36 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
37 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
38 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
40 #define PCIE_MSI_ADDR_LO 0x820
41 #define PCIE_MSI_ADDR_HI 0x824
42 #define PCIE_MSI_INTR0_ENABLE 0x828
43 #define PCIE_MSI_INTR0_MASK 0x82C
44 #define PCIE_MSI_INTR0_STATUS 0x830
46 #define PCIE_ATU_VIEWPORT 0x900
47 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
48 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
49 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
50 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
51 #define PCIE_ATU_CR1 0x904
52 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
53 #define PCIE_ATU_TYPE_IO (0x2 << 0)
54 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
55 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
56 #define PCIE_ATU_CR2 0x908
57 #define PCIE_ATU_ENABLE (0x1 << 31)
58 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
59 #define PCIE_ATU_LOWER_BASE 0x90C
60 #define PCIE_ATU_UPPER_BASE 0x910
61 #define PCIE_ATU_LIMIT 0x914
62 #define PCIE_ATU_LOWER_TARGET 0x918
63 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
64 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
65 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
66 #define PCIE_ATU_UPPER_TARGET 0x91C
68 static struct hw_pci dw_pci;
70 unsigned long global_io_offset;
72 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
74 return sys->private_data;
77 int cfg_read(void __iomem *addr, int where, int size, u32 *val)
82 *val = (*val >> (8 * (where & 3))) & 0xff;
84 *val = (*val >> (8 * (where & 3))) & 0xffff;
86 return PCIBIOS_BAD_REGISTER_NUMBER;
88 return PCIBIOS_SUCCESSFUL;
91 int cfg_write(void __iomem *addr, int where, int size, u32 val)
96 writew(val, addr + (where & 2));
98 writeb(val, addr + (where & 3));
100 return PCIBIOS_BAD_REGISTER_NUMBER;
102 return PCIBIOS_SUCCESSFUL;
105 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
107 if (pp->ops->readl_rc)
108 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
110 *val = readl(pp->dbi_base + reg);
113 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
115 if (pp->ops->writel_rc)
116 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
118 writel(val, pp->dbi_base + reg);
121 int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
126 if (pp->ops->rd_own_conf)
127 ret = pp->ops->rd_own_conf(pp, where, size, val);
129 ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
134 int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
139 if (pp->ops->wr_own_conf)
140 ret = pp->ops->wr_own_conf(pp, where, size, val);
142 ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
148 static struct irq_chip dw_msi_irq_chip = {
150 .irq_enable = unmask_msi_irq,
151 .irq_disable = mask_msi_irq,
152 .irq_mask = mask_msi_irq,
153 .irq_unmask = unmask_msi_irq,
156 /* MSI int handler */
157 void dw_handle_msi_irq(struct pcie_port *pp)
162 for (i = 0; i < MAX_MSI_CTRLS; i++) {
163 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
167 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
168 generic_handle_irq(pp->msi_irq_start
173 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
177 void dw_pcie_msi_init(struct pcie_port *pp)
179 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
181 /* program the msi_data */
182 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
183 virt_to_phys((void *)pp->msi_data));
184 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
187 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
192 pos = find_next_zero_bit(pp->msi_irq_in_use,
194 /*if you have reached to the end then get out from here.*/
195 if (pos == MAX_MSI_IRQS)
198 * Check if this position is at correct offset.nvec is always a
199 * power of two. pos0 must be nvec bit alligned.
202 pos += msgvec - (pos % msgvec);
211 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
213 int res, bit, irq, pos0, pos1, i;
215 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
222 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
224 if (pos0 % no_irqs) {
225 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
229 pos1 = find_next_bit(pp->msi_irq_in_use,
231 /* there must be nvec number of consecutive free bits */
232 while ((pos1 - pos0) < no_irqs) {
233 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
235 pos1 = find_next_bit(pp->msi_irq_in_use,
240 irq = (pp->msi_irq_start + pos0);
242 if ((irq + no_irqs) > (pp->msi_irq_start + MAX_MSI_IRQS-1))
246 while (i < no_irqs) {
247 set_bit(pos0 + i, pp->msi_irq_in_use);
248 irq_alloc_descs((irq + i), (irq + i), 1, 0);
249 irq_set_msi_desc(irq + i, desc);
250 /*Enable corresponding interrupt in MSI interrupt controller */
251 res = ((pos0 + i) / 32) * 12;
252 bit = (pos0 + i) % 32;
253 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
255 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
267 static void clear_irq(unsigned int irq)
269 int res, bit, val, pos;
270 struct irq_desc *desc;
271 struct msi_desc *msi;
272 struct pcie_port *pp;
274 /* get the port structure */
275 desc = irq_to_desc(irq);
276 msi = irq_desc_get_msi_desc(desc);
277 pp = sys_to_pcie(msi->dev->bus->sysdata);
283 pos = irq - pp->msi_irq_start;
287 clear_bit(pos, pp->msi_irq_in_use);
289 /* Disable corresponding interrupt on MSI interrupt controller */
290 res = (pos / 32) * 12;
292 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
294 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
297 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
298 struct msi_desc *desc)
300 int irq, pos, msgvec;
303 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
310 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
312 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
314 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
318 irq = assign_irq((1 << msgvec), desc, &pos);
322 msg_ctr &= ~PCI_MSI_FLAGS_QSIZE;
323 msg_ctr |= msgvec << 4;
324 pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
326 desc->msi_attrib.multiple = msgvec;
328 msg.address_lo = virt_to_phys((void *)pp->msi_data);
329 msg.address_hi = 0x0;
331 write_msi_msg(irq, &msg);
336 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
341 static struct msi_chip dw_pcie_msi_chip = {
342 .setup_irq = dw_msi_setup_irq,
343 .teardown_irq = dw_msi_teardown_irq,
346 int dw_pcie_link_up(struct pcie_port *pp)
348 if (pp->ops->link_up)
349 return pp->ops->link_up(pp);
354 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
355 irq_hw_number_t hwirq)
357 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
358 irq_set_chip_data(irq, domain->host_data);
359 set_irq_flags(irq, IRQF_VALID);
364 static const struct irq_domain_ops msi_domain_ops = {
365 .map = dw_pcie_msi_map,
368 int __init dw_pcie_host_init(struct pcie_port *pp)
370 struct device_node *np = pp->dev->of_node;
371 struct of_pci_range range;
372 struct of_pci_range_parser parser;
375 struct irq_domain *irq_domain;
377 if (of_pci_range_parser_init(&parser, np)) {
378 dev_err(pp->dev, "missing ranges property\n");
382 /* Get the I/O and memory ranges from DT */
383 for_each_of_pci_range(&parser, &range) {
384 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
385 if (restype == IORESOURCE_IO) {
386 of_pci_range_to_resource(&range, np, &pp->io);
388 pp->io.start = max_t(resource_size_t,
390 range.pci_addr + global_io_offset);
391 pp->io.end = min_t(resource_size_t,
393 range.pci_addr + range.size
395 pp->config.io_size = resource_size(&pp->io);
396 pp->config.io_bus_addr = range.pci_addr;
398 if (restype == IORESOURCE_MEM) {
399 of_pci_range_to_resource(&range, np, &pp->mem);
400 pp->mem.name = "MEM";
401 pp->config.mem_size = resource_size(&pp->mem);
402 pp->config.mem_bus_addr = range.pci_addr;
405 of_pci_range_to_resource(&range, np, &pp->cfg);
406 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
407 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
412 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
413 resource_size(&pp->cfg));
415 dev_err(pp->dev, "error with ioremap\n");
420 pp->cfg0_base = pp->cfg.start;
421 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
422 pp->io_base = pp->io.start;
423 pp->mem_base = pp->mem.start;
425 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
426 pp->config.cfg0_size);
427 if (!pp->va_cfg0_base) {
428 dev_err(pp->dev, "error with ioremap in function\n");
431 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
432 pp->config.cfg1_size);
433 if (!pp->va_cfg1_base) {
434 dev_err(pp->dev, "error with ioremap\n");
438 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
439 dev_err(pp->dev, "Failed to parse the number of lanes\n");
443 if (IS_ENABLED(CONFIG_PCI_MSI)) {
444 irq_domain = irq_domain_add_linear(pp->dev->of_node,
445 MAX_MSI_IRQS, &msi_domain_ops,
448 dev_err(pp->dev, "irq domain init failed\n");
452 pp->msi_irq_start = irq_find_mapping(irq_domain, 0);
455 if (pp->ops->host_init)
456 pp->ops->host_init(pp);
458 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
460 /* program correct class for RC */
461 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
463 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
464 val |= PORT_LOGIC_SPEED_CHANGE;
465 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
467 dw_pci.nr_controllers = 1;
468 dw_pci.private_data = (void **)&pp;
470 pci_common_init(&dw_pci);
471 pci_assign_unassigned_resources();
472 #ifdef CONFIG_PCI_DOMAINS
479 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
481 /* Program viewport 0 : OUTBOUND : CFG0 */
482 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
484 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
485 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
486 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
488 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
489 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
490 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
491 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
494 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
496 /* Program viewport 1 : OUTBOUND : CFG1 */
497 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
499 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
500 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
501 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
502 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
503 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
505 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
506 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
509 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
511 /* Program viewport 0 : OUTBOUND : MEM */
512 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
514 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
515 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
516 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
517 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
518 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
520 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
521 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
522 PCIE_ATU_UPPER_TARGET);
525 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
527 /* Program viewport 1 : OUTBOUND : IO */
528 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
530 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
531 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
532 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
533 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
534 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
536 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
537 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
538 PCIE_ATU_UPPER_TARGET);
541 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
542 u32 devfn, int where, int size, u32 *val)
544 int ret = PCIBIOS_SUCCESSFUL;
547 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
548 PCIE_ATU_FUNC(PCI_FUNC(devfn));
549 address = where & ~0x3;
551 if (bus->parent->number == pp->root_bus_nr) {
552 dw_pcie_prog_viewport_cfg0(pp, busdev);
553 ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
554 dw_pcie_prog_viewport_mem_outbound(pp);
556 dw_pcie_prog_viewport_cfg1(pp, busdev);
557 ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
558 dw_pcie_prog_viewport_io_outbound(pp);
564 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
565 u32 devfn, int where, int size, u32 val)
567 int ret = PCIBIOS_SUCCESSFUL;
570 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
571 PCIE_ATU_FUNC(PCI_FUNC(devfn));
572 address = where & ~0x3;
574 if (bus->parent->number == pp->root_bus_nr) {
575 dw_pcie_prog_viewport_cfg0(pp, busdev);
576 ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
577 dw_pcie_prog_viewport_mem_outbound(pp);
579 dw_pcie_prog_viewport_cfg1(pp, busdev);
580 ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
581 dw_pcie_prog_viewport_io_outbound(pp);
588 static int dw_pcie_valid_config(struct pcie_port *pp,
589 struct pci_bus *bus, int dev)
591 /* If there is no link, then there is no device */
592 if (bus->number != pp->root_bus_nr) {
593 if (!dw_pcie_link_up(pp))
597 /* access only one slot on each root port */
598 if (bus->number == pp->root_bus_nr && dev > 0)
602 * do not read more than one device on the bus directly attached
603 * to RC's (Virtual Bridge's) DS side.
605 if (bus->primary == pp->root_bus_nr && dev > 0)
611 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
614 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
623 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
625 return PCIBIOS_DEVICE_NOT_FOUND;
628 spin_lock_irqsave(&pp->conf_lock, flags);
629 if (bus->number != pp->root_bus_nr)
630 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
633 ret = dw_pcie_rd_own_conf(pp, where, size, val);
634 spin_unlock_irqrestore(&pp->conf_lock, flags);
639 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
640 int where, int size, u32 val)
642 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
651 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
652 return PCIBIOS_DEVICE_NOT_FOUND;
654 spin_lock_irqsave(&pp->conf_lock, flags);
655 if (bus->number != pp->root_bus_nr)
656 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
659 ret = dw_pcie_wr_own_conf(pp, where, size, val);
660 spin_unlock_irqrestore(&pp->conf_lock, flags);
665 static struct pci_ops dw_pcie_ops = {
666 .read = dw_pcie_rd_conf,
667 .write = dw_pcie_wr_conf,
670 int dw_pcie_setup(int nr, struct pci_sys_data *sys)
672 struct pcie_port *pp;
674 pp = sys_to_pcie(sys);
679 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
680 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
681 pci_ioremap_io(sys->io_offset, pp->io.start);
682 global_io_offset += SZ_64K;
683 pci_add_resource_offset(&sys->resources, &pp->io,
687 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
688 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
693 struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
696 struct pcie_port *pp = sys_to_pcie(sys);
699 pp->root_bus_nr = sys->busnr;
700 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
701 sys, &sys->resources);
710 int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
712 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
717 static void dw_pcie_add_bus(struct pci_bus *bus)
719 if (IS_ENABLED(CONFIG_PCI_MSI)) {
720 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
722 dw_pcie_msi_chip.dev = pp->dev;
723 bus->msi = &dw_pcie_msi_chip;
727 static struct hw_pci dw_pci = {
728 .setup = dw_pcie_setup,
729 .scan = dw_pcie_scan_bus,
730 .map_irq = dw_pcie_map_irq,
731 .add_bus = dw_pcie_add_bus,
734 void dw_pcie_setup_rc(struct pcie_port *pp)
736 struct pcie_port_info *config = &pp->config;
741 /* set the number of lines as 4 */
742 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
743 val &= ~PORT_LINK_MODE_MASK;
746 val |= PORT_LINK_MODE_1_LANES;
749 val |= PORT_LINK_MODE_2_LANES;
752 val |= PORT_LINK_MODE_4_LANES;
755 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
757 /* set link width speed control register */
758 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
759 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
762 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
765 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
768 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
771 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
774 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
775 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
777 /* setup interrupt pins */
778 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
781 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
783 /* setup bus numbers */
784 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
787 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
789 /* setup memory base, memory limit */
790 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
791 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
792 val = memlimit | membase;
793 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
795 /* setup command register */
796 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
798 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
799 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
800 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
803 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
804 MODULE_DESCRIPTION("Designware PCIe host controller driver");
805 MODULE_LICENSE("GPL v2");