2 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
3 * Copyright (C) 2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/msi.h>
18 #include <linux/clk.h>
19 #include <linux/module.h>
20 #include <linux/mbus.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_address.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/phy/phy.h>
32 #include "pcie-iproc.h"
34 #define EP_PERST_SOURCE_SELECT_SHIFT 2
35 #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
36 #define EP_MODE_SURVIVE_PERST_SHIFT 1
37 #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
38 #define RC_PCIE_RST_OUTPUT_SHIFT 0
39 #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
40 #define PAXC_RESET_MASK 0x7f
42 #define GIC_V3_CFG_SHIFT 0
43 #define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT)
45 #define MSI_ENABLE_CFG_SHIFT 0
46 #define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT)
48 #define CFG_IND_ADDR_MASK 0x00001ffc
50 #define CFG_ADDR_BUS_NUM_SHIFT 20
51 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
52 #define CFG_ADDR_DEV_NUM_SHIFT 15
53 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
54 #define CFG_ADDR_FUNC_NUM_SHIFT 12
55 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
56 #define CFG_ADDR_REG_NUM_SHIFT 2
57 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
58 #define CFG_ADDR_CFG_TYPE_SHIFT 0
59 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
61 #define SYS_RC_INTX_MASK 0xf
63 #define PCIE_PHYLINKUP_SHIFT 3
64 #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
65 #define PCIE_DL_ACTIVE_SHIFT 2
66 #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
68 #define APB_ERR_EN_SHIFT 0
69 #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
71 /* derive the enum index of the outbound/inbound mapping registers */
72 #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
75 * Maximum number of outbound mapping window sizes that can be supported by any
76 * OARR/OMAP mapping pair
78 #define MAX_NUM_OB_WINDOW_SIZES 4
80 #define OARR_VALID_SHIFT 0
81 #define OARR_VALID BIT(OARR_VALID_SHIFT)
82 #define OARR_SIZE_CFG_SHIFT 1
85 * Maximum number of inbound mapping region sizes that can be supported by an
88 #define MAX_NUM_IB_REGION_SIZES 9
90 #define IMAP_VALID_SHIFT 0
91 #define IMAP_VALID BIT(IMAP_VALID_SHIFT)
93 #define PCI_EXP_CAP 0xac
95 #define IPROC_PCIE_REG_INVALID 0xffff
98 * iProc PCIe outbound mapping controller specific parameters
100 * @window_sizes: list of supported outbound mapping window sizes in MB
101 * @nr_sizes: number of supported outbound mapping window sizes
103 struct iproc_pcie_ob_map {
104 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
105 unsigned int nr_sizes;
108 static const struct iproc_pcie_ob_map paxb_ob_map[] = {
111 .window_sizes = { 128, 256 },
116 .window_sizes = { 128, 256 },
121 static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
124 .window_sizes = { 128, 256 },
129 .window_sizes = { 128, 256 },
134 .window_sizes = { 128, 256, 512, 1024 },
139 .window_sizes = { 128, 256, 512, 1024 },
145 * iProc PCIe inbound mapping type
147 enum iproc_pcie_ib_map_type {
149 IPROC_PCIE_IB_MAP_MEM = 0,
151 /* for device I/O memory */
152 IPROC_PCIE_IB_MAP_IO,
154 /* invalid or unused */
155 IPROC_PCIE_IB_MAP_INVALID
159 * iProc PCIe inbound mapping controller specific parameters
161 * @type: inbound mapping region type
162 * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or
164 * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or
165 * GB, depedning on the size unit
166 * @nr_sizes: number of supported inbound mapping region sizes
167 * @nr_windows: number of supported inbound mapping windows for the region
168 * @imap_addr_offset: register offset between the upper and lower 32-bit
169 * IMAP address registers
170 * @imap_window_offset: register offset between each IMAP window
172 struct iproc_pcie_ib_map {
173 enum iproc_pcie_ib_map_type type;
174 unsigned int size_unit;
175 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
176 unsigned int nr_sizes;
177 unsigned int nr_windows;
178 u16 imap_addr_offset;
179 u16 imap_window_offset;
182 static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
185 .type = IPROC_PCIE_IB_MAP_IO,
187 .region_sizes = { 32 },
190 .imap_addr_offset = 0x40,
191 .imap_window_offset = 0x4,
194 /* IARR1/IMAP1 (currently unused) */
195 .type = IPROC_PCIE_IB_MAP_INVALID,
199 .type = IPROC_PCIE_IB_MAP_MEM,
201 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
205 .imap_addr_offset = 0x4,
206 .imap_window_offset = 0x8,
210 .type = IPROC_PCIE_IB_MAP_MEM,
212 .region_sizes = { 1, 2, 4, 8, 16, 32 },
215 .imap_addr_offset = 0x4,
216 .imap_window_offset = 0x8,
220 .type = IPROC_PCIE_IB_MAP_MEM,
222 .region_sizes = { 32, 64, 128, 256, 512 },
225 .imap_addr_offset = 0x4,
226 .imap_window_offset = 0x8,
231 * iProc PCIe host registers
233 enum iproc_pcie_reg {
234 /* clock/reset signal control */
235 IPROC_PCIE_CLK_CTRL = 0,
238 * To allow MSI to be steered to an external MSI controller (e.g., ARM
241 IPROC_PCIE_MSI_GIC_MODE,
244 * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the
245 * window where the MSI posted writes are written, for the writes to be
246 * interpreted as MSI writes.
248 IPROC_PCIE_MSI_BASE_ADDR,
249 IPROC_PCIE_MSI_WINDOW_SIZE,
252 * To hold the address of the register where the MSI writes are
253 * programed. When ARM GICv3 ITS is used, this should be programmed
254 * with the address of the GITS_TRANSLATER register.
256 IPROC_PCIE_MSI_ADDR_LO,
257 IPROC_PCIE_MSI_ADDR_HI,
260 IPROC_PCIE_MSI_EN_CFG,
262 /* allow access to root complex configuration space */
263 IPROC_PCIE_CFG_IND_ADDR,
264 IPROC_PCIE_CFG_IND_DATA,
266 /* allow access to device configuration space */
273 /* outbound address mapping */
283 /* inbound address mapping */
296 IPROC_PCIE_LINK_STATUS,
298 /* enable APB error for unsupported requests */
299 IPROC_PCIE_APB_ERR_EN,
301 /* total number of core registers */
302 IPROC_PCIE_MAX_NUM_REG,
305 /* iProc PCIe PAXB BCMA registers */
306 static const u16 iproc_pcie_reg_paxb_bcma[] = {
307 [IPROC_PCIE_CLK_CTRL] = 0x000,
308 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
309 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
310 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
311 [IPROC_PCIE_CFG_DATA] = 0x1fc,
312 [IPROC_PCIE_INTX_EN] = 0x330,
313 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
316 /* iProc PCIe PAXB registers */
317 static const u16 iproc_pcie_reg_paxb[] = {
318 [IPROC_PCIE_CLK_CTRL] = 0x000,
319 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
320 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
321 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
322 [IPROC_PCIE_CFG_DATA] = 0x1fc,
323 [IPROC_PCIE_INTX_EN] = 0x330,
324 [IPROC_PCIE_OARR0] = 0xd20,
325 [IPROC_PCIE_OMAP0] = 0xd40,
326 [IPROC_PCIE_OARR1] = 0xd28,
327 [IPROC_PCIE_OMAP1] = 0xd48,
328 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
329 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
332 /* iProc PCIe PAXB v2 registers */
333 static const u16 iproc_pcie_reg_paxb_v2[] = {
334 [IPROC_PCIE_CLK_CTRL] = 0x000,
335 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
336 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
337 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
338 [IPROC_PCIE_CFG_DATA] = 0x1fc,
339 [IPROC_PCIE_INTX_EN] = 0x330,
340 [IPROC_PCIE_OARR0] = 0xd20,
341 [IPROC_PCIE_OMAP0] = 0xd40,
342 [IPROC_PCIE_OARR1] = 0xd28,
343 [IPROC_PCIE_OMAP1] = 0xd48,
344 [IPROC_PCIE_OARR2] = 0xd60,
345 [IPROC_PCIE_OMAP2] = 0xd68,
346 [IPROC_PCIE_OARR3] = 0xdf0,
347 [IPROC_PCIE_OMAP3] = 0xdf8,
348 [IPROC_PCIE_IARR0] = 0xd00,
349 [IPROC_PCIE_IMAP0] = 0xc00,
350 [IPROC_PCIE_IARR2] = 0xd10,
351 [IPROC_PCIE_IMAP2] = 0xcc0,
352 [IPROC_PCIE_IARR3] = 0xe00,
353 [IPROC_PCIE_IMAP3] = 0xe08,
354 [IPROC_PCIE_IARR4] = 0xe68,
355 [IPROC_PCIE_IMAP4] = 0xe70,
356 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
357 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
360 /* iProc PCIe PAXC v1 registers */
361 static const u16 iproc_pcie_reg_paxc[] = {
362 [IPROC_PCIE_CLK_CTRL] = 0x000,
363 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
364 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
365 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
366 [IPROC_PCIE_CFG_DATA] = 0x1fc,
369 /* iProc PCIe PAXC v2 registers */
370 static const u16 iproc_pcie_reg_paxc_v2[] = {
371 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
372 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
373 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
374 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
375 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
376 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
377 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
378 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
379 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
380 [IPROC_PCIE_CFG_DATA] = 0x1fc,
383 static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
385 struct iproc_pcie *pcie;
387 struct pci_sys_data *sys = bus->sysdata;
389 pcie = sys->private_data;
396 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
398 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
401 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
402 enum iproc_pcie_reg reg)
404 return pcie->reg_offsets[reg];
407 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
408 enum iproc_pcie_reg reg)
410 u16 offset = iproc_pcie_reg_offset(pcie, reg);
412 if (iproc_pcie_reg_is_invalid(offset))
415 return readl(pcie->base + offset);
418 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
419 enum iproc_pcie_reg reg, u32 val)
421 u16 offset = iproc_pcie_reg_offset(pcie, reg);
423 if (iproc_pcie_reg_is_invalid(offset))
426 writel(val, pcie->base + offset);
430 * APB error forwarding can be disabled during access of configuration
431 * registers of the endpoint device, to prevent unsupported requests
432 * (typically seen during enumeration with multi-function devices) from
433 * triggering a system exception.
435 static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,
438 struct iproc_pcie *pcie = iproc_data(bus);
441 if (bus->number && pcie->has_apb_err_disable) {
442 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
447 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
452 * Note access to the configuration registers are protected at the higher layer
453 * by 'pci_lock' in drivers/pci/access.c
455 static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie,
460 unsigned slot = PCI_SLOT(devfn);
461 unsigned fn = PCI_FUNC(devfn);
465 /* root complex access */
467 if (slot > 0 || fn > 0)
470 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
471 where & CFG_IND_ADDR_MASK);
472 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
473 if (iproc_pcie_reg_is_invalid(offset))
476 return (pcie->base + offset);
480 * PAXC is connected to an internally emulated EP within the SoC. It
481 * allows only one device.
483 if (pcie->ep_is_internal)
487 /* EP device access */
488 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
489 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
490 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
491 (where & CFG_ADDR_REG_NUM_MASK) |
492 (1 & CFG_ADDR_CFG_TYPE_MASK);
493 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
494 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
495 if (iproc_pcie_reg_is_invalid(offset))
498 return (pcie->base + offset);
501 static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus,
505 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn,
509 static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
510 unsigned int devfn, int where,
515 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
518 return PCIBIOS_DEVICE_NOT_FOUND;
524 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
526 return PCIBIOS_SUCCESSFUL;
529 static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
530 unsigned int devfn, int where,
536 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
538 return PCIBIOS_DEVICE_NOT_FOUND;
542 return PCIBIOS_SUCCESSFUL;
545 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
546 tmp = readl(addr) & mask;
547 tmp |= val << ((where & 0x3) * 8);
550 return PCIBIOS_SUCCESSFUL;
553 static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
554 int where, int size, u32 *val)
558 iproc_pcie_apb_err_disable(bus, true);
559 ret = pci_generic_config_read32(bus, devfn, where, size, val);
560 iproc_pcie_apb_err_disable(bus, false);
565 static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn,
566 int where, int size, u32 val)
570 iproc_pcie_apb_err_disable(bus, true);
571 ret = pci_generic_config_write32(bus, devfn, where, size, val);
572 iproc_pcie_apb_err_disable(bus, false);
577 static struct pci_ops iproc_pcie_ops = {
578 .map_bus = iproc_pcie_bus_map_cfg_bus,
579 .read = iproc_pcie_config_read32,
580 .write = iproc_pcie_config_write32,
583 static void iproc_pcie_reset(struct iproc_pcie *pcie)
588 * PAXC and the internal emulated endpoint device downstream should not
589 * be reset. If firmware has been loaded on the endpoint device at an
590 * earlier boot stage, reset here causes issues.
592 if (pcie->ep_is_internal)
596 * Select perst_b signal as reset source. Put the device into reset,
597 * and then bring it out of reset
599 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
600 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
602 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
605 val |= RC_PCIE_RST_OUTPUT;
606 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
610 static int iproc_pcie_check_link(struct iproc_pcie *pcie)
612 struct device *dev = pcie->dev;
613 u32 hdr_type, link_ctrl, link_status, class, val;
614 u16 pos = PCI_EXP_CAP;
615 bool link_is_active = false;
618 * PAXC connects to emulated endpoint devices directly and does not
619 * have a Serdes. Therefore skip the link detection logic here.
621 if (pcie->ep_is_internal)
624 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
625 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
626 dev_err(dev, "PHY or data link is INACTIVE!\n");
630 /* make sure we are not in EP mode */
631 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);
632 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
633 dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type);
637 /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
638 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
639 #define PCI_CLASS_BRIDGE_MASK 0xffff00
640 #define PCI_CLASS_BRIDGE_SHIFT 8
641 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
643 class &= ~PCI_CLASS_BRIDGE_MASK;
644 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
645 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
648 /* check link status to see if link is active */
649 iproc_pci_raw_config_read32(pcie, 0, pos + PCI_EXP_LNKSTA,
651 if (link_status & PCI_EXP_LNKSTA_NLW)
652 link_is_active = true;
654 if (!link_is_active) {
655 /* try GEN 1 link speed */
656 #define PCI_TARGET_LINK_SPEED_MASK 0xf
657 #define PCI_TARGET_LINK_SPEED_GEN2 0x2
658 #define PCI_TARGET_LINK_SPEED_GEN1 0x1
659 iproc_pci_raw_config_read32(pcie, 0,
660 pos + PCI_EXP_LNKCTL2, 4,
662 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
663 PCI_TARGET_LINK_SPEED_GEN2) {
664 link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
665 link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
666 iproc_pci_raw_config_write32(pcie, 0,
667 pos + PCI_EXP_LNKCTL2,
671 iproc_pci_raw_config_read32(pcie, 0,
672 pos + PCI_EXP_LNKSTA,
674 if (link_status & PCI_EXP_LNKSTA_NLW)
675 link_is_active = true;
679 dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
681 return link_is_active ? 0 : -ENODEV;
684 static void iproc_pcie_enable(struct iproc_pcie *pcie)
686 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
689 static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
694 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
696 return !!(val & OARR_VALID);
699 static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
700 int size_idx, u64 axi_addr, u64 pci_addr)
702 struct device *dev = pcie->dev;
703 u16 oarr_offset, omap_offset;
706 * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based
709 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
711 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
713 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
714 iproc_pcie_reg_is_invalid(omap_offset))
718 * Program the OARR registers. The upper 32-bit OARR register is
719 * always right after the lower 32-bit OARR register.
721 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
722 OARR_VALID, pcie->base + oarr_offset);
723 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
725 /* now program the OMAP registers */
726 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
727 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
729 dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
730 window_idx, oarr_offset, &axi_addr, &pci_addr);
731 dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n",
732 readl(pcie->base + oarr_offset),
733 readl(pcie->base + oarr_offset + 4));
734 dev_info(dev, "omap lo 0x%x omap hi 0x%x\n",
735 readl(pcie->base + omap_offset),
736 readl(pcie->base + omap_offset + 4));
742 * Some iProc SoCs require the SW to configure the outbound address mapping
744 * Outbound address translation:
746 * iproc_pcie_address = axi_address - axi_offset
747 * OARR = iproc_pcie_address
750 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
752 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
753 u64 pci_addr, resource_size_t size)
755 struct iproc_pcie_ob *ob = &pcie->ob;
756 struct device *dev = pcie->dev;
757 int ret = -EINVAL, window_idx, size_idx;
759 if (axi_addr < ob->axi_offset) {
760 dev_err(dev, "axi address %pap less than offset %pap\n",
761 &axi_addr, &ob->axi_offset);
766 * Translate the AXI address to the internal address used by the iProc
767 * PCIe core before programming the OARR
769 axi_addr -= ob->axi_offset;
771 /* iterate through all OARR/OMAP mapping windows */
772 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
773 const struct iproc_pcie_ob_map *ob_map =
774 &pcie->ob_map[window_idx];
777 * If current outbound window is already in use, move on to the
780 if (iproc_pcie_ob_is_valid(pcie, window_idx))
784 * Iterate through all supported window sizes within the
785 * OARR/OMAP pair to find a match. Go through the window sizes
786 * in a descending order.
788 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
790 resource_size_t window_size =
791 ob_map->window_sizes[size_idx] * SZ_1M;
793 if (size < window_size)
796 if (!IS_ALIGNED(axi_addr, window_size) ||
797 !IS_ALIGNED(pci_addr, window_size)) {
799 "axi %pap or pci %pap not aligned\n",
800 &axi_addr, &pci_addr);
805 * Match found! Program both OARR and OMAP and mark
806 * them as a valid entry.
808 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
818 * If we are here, we are done with the current window,
819 * but not yet finished all mappings. Need to move on
820 * to the next window.
822 axi_addr += window_size;
823 pci_addr += window_size;
829 dev_err(dev, "unable to configure outbound mapping\n");
831 "axi %pap, axi offset %pap, pci %pap, res size %pap\n",
832 &axi_addr, &ob->axi_offset, &pci_addr, &size);
837 static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
838 struct list_head *resources)
840 struct device *dev = pcie->dev;
841 struct resource_entry *window;
844 resource_list_for_each_entry(window, resources) {
845 struct resource *res = window->res;
846 u64 res_type = resource_type(res);
853 ret = iproc_pcie_setup_ob(pcie, res->start,
854 res->start - window->offset,
860 dev_err(dev, "invalid resource %pR\n", res);
868 static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
871 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
874 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
876 return !!(val & (BIT(ib_map->nr_sizes) - 1));
879 static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
880 enum iproc_pcie_ib_map_type type)
882 return !!(ib_map->type == type);
885 static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
886 int size_idx, int nr_windows, u64 axi_addr,
887 u64 pci_addr, resource_size_t size)
889 struct device *dev = pcie->dev;
890 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
891 u16 iarr_offset, imap_offset;
895 iarr_offset = iproc_pcie_reg_offset(pcie,
896 MAP_REG(IPROC_PCIE_IARR0, region_idx));
897 imap_offset = iproc_pcie_reg_offset(pcie,
898 MAP_REG(IPROC_PCIE_IMAP0, region_idx));
899 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
900 iproc_pcie_reg_is_invalid(imap_offset))
903 dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
904 region_idx, iarr_offset, &axi_addr, &pci_addr);
907 * Program the IARR registers. The upper 32-bit IARR register is
908 * always right after the lower 32-bit IARR register.
910 writel(lower_32_bits(pci_addr) | BIT(size_idx),
911 pcie->base + iarr_offset);
912 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
914 dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n",
915 readl(pcie->base + iarr_offset),
916 readl(pcie->base + iarr_offset + 4));
919 * Now program the IMAP registers. Each IARR region may have one or
922 size >>= ilog2(nr_windows);
923 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
924 val = readl(pcie->base + imap_offset);
925 val |= lower_32_bits(axi_addr) | IMAP_VALID;
926 writel(val, pcie->base + imap_offset);
927 writel(upper_32_bits(axi_addr),
928 pcie->base + imap_offset + ib_map->imap_addr_offset);
930 dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
931 window_idx, readl(pcie->base + imap_offset),
932 readl(pcie->base + imap_offset +
933 ib_map->imap_addr_offset));
935 imap_offset += ib_map->imap_window_offset;
942 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
943 struct of_pci_range *range,
944 enum iproc_pcie_ib_map_type type)
946 struct device *dev = pcie->dev;
947 struct iproc_pcie_ib *ib = &pcie->ib;
949 unsigned int region_idx, size_idx;
950 u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr;
951 resource_size_t size = range->size;
953 /* iterate through all IARR mapping regions */
954 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
955 const struct iproc_pcie_ib_map *ib_map =
956 &pcie->ib_map[region_idx];
959 * If current inbound region is already in use or not a
960 * compatible type, move on to the next.
962 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
963 !iproc_pcie_ib_check_type(ib_map, type))
966 /* iterate through all supported region sizes to find a match */
967 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
968 resource_size_t region_size =
969 ib_map->region_sizes[size_idx] * ib_map->size_unit;
971 if (size != region_size)
974 if (!IS_ALIGNED(axi_addr, region_size) ||
975 !IS_ALIGNED(pci_addr, region_size)) {
977 "axi %pap or pci %pap not aligned\n",
978 &axi_addr, &pci_addr);
982 /* Match found! Program IARR and all IMAP windows. */
983 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
984 ib_map->nr_windows, axi_addr,
996 dev_err(dev, "unable to configure inbound mapping\n");
997 dev_err(dev, "axi %pap, pci %pap, res size %pap\n",
998 &axi_addr, &pci_addr, &size);
1003 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
1004 struct device_node *node)
1006 const int na = 3, ns = 2;
1009 parser->node = node;
1010 parser->pna = of_n_addr_cells(node);
1011 parser->np = parser->pna + na + ns;
1013 parser->range = of_get_property(node, "dma-ranges", &rlen);
1017 parser->end = parser->range + rlen / sizeof(__be32);
1021 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1023 struct of_pci_range range;
1024 struct of_pci_range_parser parser;
1027 /* Get the dma-ranges from DT */
1028 ret = pci_dma_range_parser_init(&parser, pcie->dev->of_node);
1032 for_each_of_pci_range(&parser, &range) {
1033 /* Each range entry corresponds to an inbound mapping region */
1034 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM);
1042 static int iproce_pcie_get_msi(struct iproc_pcie *pcie,
1043 struct device_node *msi_node,
1046 struct device *dev = pcie->dev;
1048 struct resource res;
1051 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only
1052 * supported external MSI controller that requires steering.
1054 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) {
1055 dev_err(dev, "unable to find compatible MSI controller\n");
1059 /* derive GITS_TRANSLATER address from GICv3 */
1060 ret = of_address_to_resource(msi_node, 0, &res);
1062 dev_err(dev, "unable to obtain MSI controller resources\n");
1066 *msi_addr = res.start + GITS_TRANSLATER;
1070 static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1073 struct of_pci_range range;
1075 memset(&range, 0, sizeof(range));
1076 range.size = SZ_32K;
1077 range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1);
1079 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO);
1083 static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1088 * Program bits [43:13] of address of GITS_TRANSLATER register into
1089 * bits [30:0] of the MSI base address register. In fact, in all iProc
1090 * based SoCs, all I/O register bases are well below the 32-bit
1091 * boundary, so we can safely assume bits [43:32] are always zeros.
1093 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR,
1094 (u32)(msi_addr >> 13));
1096 /* use a default 8K window size */
1097 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0);
1099 /* steering MSI to GICv3 ITS */
1100 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE);
1102 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val);
1105 * Program bits [43:2] of address of GITS_TRANSLATER register into the
1106 * iProc MSI address registers.
1109 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI,
1110 upper_32_bits(msi_addr));
1111 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO,
1112 lower_32_bits(msi_addr));
1115 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
1116 val |= MSI_ENABLE_CFG;
1117 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
1120 static int iproc_pcie_msi_steer(struct iproc_pcie *pcie,
1121 struct device_node *msi_node)
1123 struct device *dev = pcie->dev;
1127 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr);
1129 dev_err(dev, "msi steering failed\n");
1133 switch (pcie->type) {
1134 case IPROC_PCIE_PAXB_V2:
1135 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr);
1139 case IPROC_PCIE_PAXC_V2:
1140 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr);
1149 static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
1151 struct device_node *msi_node;
1155 * Either the "msi-parent" or the "msi-map" phandle needs to exist
1156 * for us to obtain the MSI node.
1159 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
1161 const __be32 *msi_map = NULL;
1165 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len);
1169 phandle = be32_to_cpup(msi_map + 1);
1170 msi_node = of_find_node_by_phandle(phandle);
1176 * Certain revisions of the iProc PCIe controller require additional
1177 * configurations to steer the MSI writes towards an external MSI
1180 if (pcie->need_msi_steer) {
1181 ret = iproc_pcie_msi_steer(pcie, msi_node);
1187 * If another MSI controller is being used, the call below should fail
1190 return iproc_msi_init(pcie, msi_node);
1193 static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
1195 iproc_msi_exit(pcie);
1198 static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
1200 struct device *dev = pcie->dev;
1201 unsigned int reg_idx;
1204 switch (pcie->type) {
1205 case IPROC_PCIE_PAXB_BCMA:
1206 regs = iproc_pcie_reg_paxb_bcma;
1208 case IPROC_PCIE_PAXB:
1209 regs = iproc_pcie_reg_paxb;
1210 pcie->has_apb_err_disable = true;
1211 if (pcie->need_ob_cfg) {
1212 pcie->ob_map = paxb_ob_map;
1213 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map);
1216 case IPROC_PCIE_PAXB_V2:
1217 regs = iproc_pcie_reg_paxb_v2;
1218 pcie->has_apb_err_disable = true;
1219 if (pcie->need_ob_cfg) {
1220 pcie->ob_map = paxb_v2_ob_map;
1221 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
1223 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
1224 pcie->ib_map = paxb_v2_ib_map;
1225 pcie->need_msi_steer = true;
1227 case IPROC_PCIE_PAXC:
1228 regs = iproc_pcie_reg_paxc;
1229 pcie->ep_is_internal = true;
1231 case IPROC_PCIE_PAXC_V2:
1232 regs = iproc_pcie_reg_paxc_v2;
1233 pcie->ep_is_internal = true;
1234 pcie->need_msi_steer = true;
1237 dev_err(dev, "incompatible iProc PCIe interface\n");
1241 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG,
1242 sizeof(*pcie->reg_offsets),
1244 if (!pcie->reg_offsets)
1247 /* go through the register table and populate all valid registers */
1248 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
1249 IPROC_PCIE_REG_INVALID : regs[0];
1250 for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++)
1251 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
1252 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
1257 int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
1262 struct pci_bus *child;
1263 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1267 ret = iproc_pcie_rev_init(pcie);
1269 dev_err(dev, "unable to initialize controller parameters\n");
1273 ret = devm_request_pci_bus_resources(dev, res);
1277 ret = phy_init(pcie->phy);
1279 dev_err(dev, "unable to initialize PCIe PHY\n");
1283 ret = phy_power_on(pcie->phy);
1285 dev_err(dev, "unable to power on PCIe PHY\n");
1289 iproc_pcie_reset(pcie);
1291 if (pcie->need_ob_cfg) {
1292 ret = iproc_pcie_map_ranges(pcie, res);
1294 dev_err(dev, "map failed\n");
1295 goto err_power_off_phy;
1299 ret = iproc_pcie_map_dma_ranges(pcie);
1300 if (ret && ret != -ENOENT)
1301 goto err_power_off_phy;
1304 pcie->sysdata.private_data = pcie;
1305 sysdata = &pcie->sysdata;
1310 ret = iproc_pcie_check_link(pcie);
1312 dev_err(dev, "no PCIe EP device detected\n");
1313 goto err_power_off_phy;
1316 iproc_pcie_enable(pcie);
1318 if (IS_ENABLED(CONFIG_PCI_MSI))
1319 if (iproc_pcie_msi_enable(pcie))
1320 dev_info(dev, "not using iProc MSI\n");
1322 list_splice_init(res, &host->windows);
1324 host->dev.parent = dev;
1325 host->ops = &iproc_pcie_ops;
1326 host->sysdata = sysdata;
1327 host->map_irq = pcie->map_irq;
1328 host->swizzle_irq = pci_common_swizzle;
1330 ret = pci_scan_root_bus_bridge(host);
1332 dev_err(dev, "failed to scan host: %d\n", ret);
1333 goto err_power_off_phy;
1336 pci_assign_unassigned_bus_resources(host->bus);
1338 pcie->root_bus = host->bus;
1340 list_for_each_entry(child, &host->bus->children, node)
1341 pcie_bus_configure_settings(child);
1343 pci_bus_add_devices(host->bus);
1348 phy_power_off(pcie->phy);
1350 phy_exit(pcie->phy);
1353 EXPORT_SYMBOL(iproc_pcie_setup);
1355 int iproc_pcie_remove(struct iproc_pcie *pcie)
1357 pci_stop_root_bus(pcie->root_bus);
1358 pci_remove_root_bus(pcie->root_bus);
1360 iproc_pcie_msi_disable(pcie);
1362 phy_power_off(pcie->phy);
1363 phy_exit(pcie->phy);
1367 EXPORT_SYMBOL(iproc_pcie_remove);
1369 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1370 MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
1371 MODULE_LICENSE("GPL v2");