2 * MediaTek PCIe host controller driver.
4 * Copyright (c) 2017 MediaTek Inc.
5 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/kernel.h>
20 #include <linux/of_address.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23 #include <linux/pci.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
29 /* PCIe shared registers */
30 #define PCIE_SYS_CFG 0x00
31 #define PCIE_INT_ENABLE 0x0c
32 #define PCIE_CFG_ADDR 0x20
33 #define PCIE_CFG_DATA 0x24
35 /* PCIe per port registers */
36 #define PCIE_BAR0_SETUP 0x10
37 #define PCIE_CLASS 0x34
38 #define PCIE_LINK_STATUS 0x50
40 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
41 #define PCIE_PORT_PERST(x) BIT(1 + (x))
42 #define PCIE_PORT_LINKUP BIT(0)
43 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
45 #define PCIE_BAR_ENABLE BIT(0)
46 #define PCIE_REVISION_ID BIT(0)
47 #define PCIE_CLASS_CODE (0x60400 << 8)
48 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
49 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
50 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
51 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
52 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
53 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
54 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
55 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
57 /* MediaTek specific configuration registers */
58 #define PCIE_FTS_NUM 0x70c
59 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
60 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
62 #define PCIE_FC_CREDIT 0x73c
63 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
64 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
67 * struct mtk_pcie_port - PCIe port information
68 * @base: IO mapped register base
70 * @pcie: pointer to PCIe host info
71 * @reset: pointer to port reset control
72 * @sys_ck: pointer to bus clock
73 * @phy: pointer to phy control block
77 struct mtk_pcie_port {
79 struct list_head list;
80 struct mtk_pcie *pcie;
81 struct reset_control *reset;
89 * struct mtk_pcie - PCIe host information
90 * @dev: pointer to PCIe device
91 * @base: IO mapped register base
92 * @free_ck: free-run reference clock
95 * @mem: non-prefetchable memory resource
97 * @offset: IO / Memory offset
98 * @ports: pointer to PCIe port information
108 struct resource busn;
113 struct list_head ports;
116 static inline bool mtk_pcie_link_up(struct mtk_pcie_port *port)
118 return !!(readl(port->base + PCIE_LINK_STATUS) & PCIE_PORT_LINKUP);
121 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
123 struct device *dev = pcie->dev;
125 clk_disable_unprepare(pcie->free_ck);
127 if (dev->pm_domain) {
128 pm_runtime_put_sync(dev);
129 pm_runtime_disable(dev);
133 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
135 struct mtk_pcie *pcie = port->pcie;
136 struct device *dev = pcie->dev;
138 devm_iounmap(dev, port->base);
139 list_del(&port->list);
140 devm_kfree(dev, port);
143 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
145 struct mtk_pcie_port *port, *tmp;
147 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
148 phy_power_off(port->phy);
149 clk_disable_unprepare(port->sys_ck);
150 mtk_pcie_port_free(port);
153 mtk_pcie_subsys_powerdown(pcie);
156 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
157 unsigned int devfn, int where)
159 struct pci_host_bridge *host = pci_find_host_bridge(bus);
160 struct mtk_pcie *pcie = pci_host_bridge_priv(host);
162 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
163 bus->number), pcie->base + PCIE_CFG_ADDR);
165 return pcie->base + PCIE_CFG_DATA + (where & 3);
168 static struct pci_ops mtk_pcie_ops = {
169 .map_bus = mtk_pcie_map_bus,
170 .read = pci_generic_config_read,
171 .write = pci_generic_config_write,
174 static void mtk_pcie_configure_rc(struct mtk_pcie_port *port)
176 struct mtk_pcie *pcie = port->pcie;
177 u32 func = PCI_FUNC(port->index << 3);
178 u32 slot = PCI_SLOT(port->index << 3);
181 /* enable interrupt */
182 val = readl(pcie->base + PCIE_INT_ENABLE);
183 val |= PCIE_PORT_INT_EN(port->index);
184 writel(val, pcie->base + PCIE_INT_ENABLE);
186 /* map to all DDR region. We need to set it before cfg operation. */
187 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
188 port->base + PCIE_BAR0_SETUP);
190 /* configure class code and revision ID */
191 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
193 /* configure FC credit */
194 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
195 pcie->base + PCIE_CFG_ADDR);
196 val = readl(pcie->base + PCIE_CFG_DATA);
197 val &= ~PCIE_FC_CREDIT_MASK;
198 val |= PCIE_FC_CREDIT_VAL(0x806c);
199 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
200 pcie->base + PCIE_CFG_ADDR);
201 writel(val, pcie->base + PCIE_CFG_DATA);
203 /* configure RC FTS number to 250 when it leaves L0s */
204 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
205 pcie->base + PCIE_CFG_ADDR);
206 val = readl(pcie->base + PCIE_CFG_DATA);
207 val &= ~PCIE_FTS_NUM_MASK;
208 val |= PCIE_FTS_NUM_L0(0x50);
209 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
210 pcie->base + PCIE_CFG_ADDR);
211 writel(val, pcie->base + PCIE_CFG_DATA);
214 static void mtk_pcie_assert_ports(struct mtk_pcie_port *port)
216 struct mtk_pcie *pcie = port->pcie;
219 /* assert port PERST_N */
220 val = readl(pcie->base + PCIE_SYS_CFG);
221 val |= PCIE_PORT_PERST(port->index);
222 writel(val, pcie->base + PCIE_SYS_CFG);
224 /* de-assert port PERST_N */
225 val = readl(pcie->base + PCIE_SYS_CFG);
226 val &= ~PCIE_PORT_PERST(port->index);
227 writel(val, pcie->base + PCIE_SYS_CFG);
229 /* PCIe v2.0 need at least 100ms delay to train from Gen1 to Gen2 */
233 static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
235 struct device *dev = port->pcie->dev;
238 err = clk_prepare_enable(port->sys_ck);
240 dev_err(dev, "failed to enable port%d clock\n", port->index);
244 reset_control_assert(port->reset);
245 reset_control_deassert(port->reset);
247 err = phy_power_on(port->phy);
249 dev_err(dev, "failed to power on port%d phy\n", port->index);
253 mtk_pcie_assert_ports(port);
255 /* if link up, then setup root port configuration space */
256 if (mtk_pcie_link_up(port)) {
257 mtk_pcie_configure_rc(port);
261 dev_info(dev, "Port%d link down\n", port->index);
263 phy_power_off(port->phy);
265 clk_disable_unprepare(port->sys_ck);
267 mtk_pcie_port_free(port);
270 static int mtk_pcie_parse_ports(struct mtk_pcie *pcie,
271 struct device_node *node,
274 struct mtk_pcie_port *port;
275 struct resource *regs;
276 struct device *dev = pcie->dev;
277 struct platform_device *pdev = to_platform_device(dev);
281 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
285 err = of_property_read_u32(node, "num-lanes", &port->lane);
287 dev_err(dev, "missing num-lanes property\n");
291 regs = platform_get_resource(pdev, IORESOURCE_MEM, index + 1);
292 port->base = devm_ioremap_resource(dev, regs);
293 if (IS_ERR(port->base)) {
294 dev_err(dev, "failed to map port%d base\n", index);
295 return PTR_ERR(port->base);
298 snprintf(name, sizeof(name), "sys_ck%d", index);
299 port->sys_ck = devm_clk_get(dev, name);
300 if (IS_ERR(port->sys_ck)) {
301 dev_err(dev, "failed to get port%d clock\n", index);
302 return PTR_ERR(port->sys_ck);
305 snprintf(name, sizeof(name), "pcie-rst%d", index);
306 port->reset = devm_reset_control_get_optional(dev, name);
307 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
308 return PTR_ERR(port->reset);
310 /* some platforms may use default PHY setting */
311 snprintf(name, sizeof(name), "pcie-phy%d", index);
312 port->phy = devm_phy_optional_get(dev, name);
313 if (IS_ERR(port->phy))
314 return PTR_ERR(port->phy);
319 INIT_LIST_HEAD(&port->list);
320 list_add_tail(&port->list, &pcie->ports);
325 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
327 struct device *dev = pcie->dev;
328 struct platform_device *pdev = to_platform_device(dev);
329 struct resource *regs;
332 /* get shared registers */
333 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
334 pcie->base = devm_ioremap_resource(dev, regs);
335 if (IS_ERR(pcie->base)) {
336 dev_err(dev, "failed to map shared register\n");
337 return PTR_ERR(pcie->base);
340 pcie->free_ck = devm_clk_get(dev, "free_ck");
341 if (IS_ERR(pcie->free_ck)) {
342 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
343 return -EPROBE_DEFER;
345 pcie->free_ck = NULL;
348 if (dev->pm_domain) {
349 pm_runtime_enable(dev);
350 pm_runtime_get_sync(dev);
353 /* enable top level clock */
354 err = clk_prepare_enable(pcie->free_ck);
356 dev_err(dev, "failed to enable free_ck\n");
363 if (dev->pm_domain) {
364 pm_runtime_put_sync(dev);
365 pm_runtime_disable(dev);
371 static int mtk_pcie_setup(struct mtk_pcie *pcie)
373 struct device *dev = pcie->dev;
374 struct device_node *node = dev->of_node, *child;
375 struct of_pci_range_parser parser;
376 struct of_pci_range range;
378 struct mtk_pcie_port *port, *tmp;
381 if (of_pci_range_parser_init(&parser, node)) {
382 dev_err(dev, "missing \"ranges\" property\n");
386 for_each_of_pci_range(&parser, &range) {
387 err = of_pci_range_to_resource(&range, node, &res);
391 switch (res.flags & IORESOURCE_TYPE_BITS) {
393 pcie->offset.io = res.start - range.pci_addr;
395 memcpy(&pcie->pio, &res, sizeof(res));
396 pcie->pio.name = node->full_name;
398 pcie->io.start = range.cpu_addr;
399 pcie->io.end = range.cpu_addr + range.size - 1;
400 pcie->io.flags = IORESOURCE_MEM;
401 pcie->io.name = "I/O";
403 memcpy(&res, &pcie->io, sizeof(res));
407 pcie->offset.mem = res.start - range.pci_addr;
409 memcpy(&pcie->mem, &res, sizeof(res));
410 pcie->mem.name = "non-prefetchable";
415 err = of_pci_parse_bus_range(node, &pcie->busn);
417 dev_err(dev, "failed to parse bus ranges property: %d\n", err);
418 pcie->busn.name = node->name;
419 pcie->busn.start = 0;
420 pcie->busn.end = 0xff;
421 pcie->busn.flags = IORESOURCE_BUS;
424 for_each_available_child_of_node(node, child) {
427 err = of_pci_get_devfn(child);
429 dev_err(dev, "failed to parse devfn: %d\n", err);
433 index = PCI_SLOT(err);
435 err = mtk_pcie_parse_ports(pcie, child, index);
440 err = mtk_pcie_subsys_powerup(pcie);
444 /* enable each port, and then check link status */
445 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
446 mtk_pcie_enable_ports(port);
448 /* power down PCIe subsys if slots are all empty (link down) */
449 if (list_empty(&pcie->ports))
450 mtk_pcie_subsys_powerdown(pcie);
455 static int mtk_pcie_request_resources(struct mtk_pcie *pcie)
457 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
458 struct list_head *windows = &host->windows;
459 struct device *dev = pcie->dev;
462 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
463 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
464 pci_add_resource(windows, &pcie->busn);
466 err = devm_request_pci_bus_resources(dev, windows);
470 pci_remap_iospace(&pcie->pio, pcie->io.start);
475 static int mtk_pcie_register_host(struct pci_host_bridge *host)
477 struct mtk_pcie *pcie = pci_host_bridge_priv(host);
478 struct pci_bus *child;
481 host->busnr = pcie->busn.start;
482 host->dev.parent = pcie->dev;
483 host->ops = &mtk_pcie_ops;
484 host->map_irq = of_irq_parse_and_map_pci;
485 host->swizzle_irq = pci_common_swizzle;
487 err = pci_scan_root_bus_bridge(host);
491 pci_bus_size_bridges(host->bus);
492 pci_bus_assign_resources(host->bus);
494 list_for_each_entry(child, &host->bus->children, node)
495 pcie_bus_configure_settings(child);
497 pci_bus_add_devices(host->bus);
502 static int mtk_pcie_probe(struct platform_device *pdev)
504 struct device *dev = &pdev->dev;
505 struct mtk_pcie *pcie;
506 struct pci_host_bridge *host;
509 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
513 pcie = pci_host_bridge_priv(host);
516 platform_set_drvdata(pdev, pcie);
517 INIT_LIST_HEAD(&pcie->ports);
519 err = mtk_pcie_setup(pcie);
523 err = mtk_pcie_request_resources(pcie);
527 err = mtk_pcie_register_host(host);
534 if (!list_empty(&pcie->ports))
535 mtk_pcie_put_resources(pcie);
540 static const struct of_device_id mtk_pcie_ids[] = {
541 { .compatible = "mediatek,mt7623-pcie"},
542 { .compatible = "mediatek,mt2701-pcie"},
546 static struct platform_driver mtk_pcie_driver = {
547 .probe = mtk_pcie_probe,
550 .of_match_table = mtk_pcie_ids,
551 .suppress_bind_attrs = true,
554 builtin_platform_driver(mtk_pcie_driver);