2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
10 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
34 #define DRV_NAME "rcar-pcie"
36 #define PCIECAR 0x000010
37 #define PCIECCTLR 0x000018
38 #define CONFIG_SEND_ENABLE (1 << 31)
39 #define TYPE0 (0 << 8)
40 #define TYPE1 (1 << 8)
41 #define PCIECDR 0x000020
42 #define PCIEMSR 0x000028
43 #define PCIEINTXR 0x000400
44 #define PCIEMSITXR 0x000840
46 /* Transfer control */
47 #define PCIETCTLR 0x02000
49 #define PCIETSTR 0x02004
50 #define DATA_LINK_ACTIVE 1
51 #define PCIEERRFR 0x02020
52 #define UNSUPPORTED_REQUEST (1 << 4)
53 #define PCIEMSIFR 0x02044
54 #define PCIEMSIALR 0x02048
56 #define PCIEMSIAUR 0x0204c
57 #define PCIEMSIIER 0x02050
59 /* root port address */
60 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
62 /* local address reg & mask */
63 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
64 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
65 #define LAM_PREFETCH (1 << 3)
66 #define LAM_64BIT (1 << 2)
67 #define LAR_ENABLE (1 << 1)
69 /* PCIe address reg & mask */
70 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
71 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
72 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
73 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
74 #define PAR_ENABLE (1 << 31)
75 #define IO_SPACE (1 << 8)
78 #define PCICONF(x) (0x010000 + ((x) * 0x4))
79 #define PMCAP(x) (0x010040 + ((x) * 0x4))
80 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
81 #define VCCAP(x) (0x010100 + ((x) * 0x4))
84 #define IDSETR1 0x011004
85 #define TLCTLR 0x011048
86 #define MACSR 0x011054
87 #define MACCTLR 0x011058
88 #define SCRAMBLE_DISABLE (1 << 27)
91 #define H1_PCIEPHYADRR 0x04000c
92 #define WRITE_CMD (1 << 16)
93 #define PHY_ACK (1 << 24)
97 #define H1_PCIEPHYDOUTR 0x040014
98 #define H1_PCIEPHYSR 0x040018
101 #define GEN2_PCIEPHYADDR 0x780
102 #define GEN2_PCIEPHYDATA 0x784
103 #define GEN2_PCIEPHYCTRL 0x78c
105 #define INT_PCI_MSI_NR 32
107 #define RCONF(x) (PCICONF(0)+(x))
108 #define RPMCAP(x) (PMCAP(0)+(x))
109 #define REXPCAP(x) (EXPCAP(0)+(x))
110 #define RVCCAP(x) (VCCAP(0)+(x))
112 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
113 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
114 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
116 #define RCAR_PCI_MAX_RESOURCES 4
117 #define MAX_NR_INBOUND_MAPS 6
120 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
121 struct irq_domain *domain;
122 struct msi_controller chip;
129 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
131 return container_of(chip, struct rcar_msi, chip);
134 /* Structure representing the PCIe interface */
138 struct list_head resources;
145 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
148 writel(val, pcie->base + reg);
151 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
154 return readl(pcie->base + reg);
158 RCAR_PCI_ACCESS_READ,
159 RCAR_PCI_ACCESS_WRITE,
162 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
164 int shift = 8 * (where & 3);
165 u32 val = rcar_pci_read_reg(pcie, where & ~3);
167 val &= ~(mask << shift);
168 val |= data << shift;
169 rcar_pci_write_reg(pcie, val, where & ~3);
172 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
174 int shift = 8 * (where & 3);
175 u32 val = rcar_pci_read_reg(pcie, where & ~3);
180 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
181 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
182 unsigned char access_type, struct pci_bus *bus,
183 unsigned int devfn, int where, u32 *data)
185 int dev, func, reg, index;
187 dev = PCI_SLOT(devfn);
188 func = PCI_FUNC(devfn);
193 * While each channel has its own memory-mapped extended config
194 * space, it's generally only accessible when in endpoint mode.
195 * When in root complex mode, the controller is unable to target
196 * itself with either type 0 or type 1 accesses, and indeed, any
197 * controller initiated target transfer to its own config space
198 * result in a completer abort.
200 * Each channel effectively only supports a single device, but as
201 * the same channel <-> device access works for any PCI_SLOT()
202 * value, we cheat a bit here and bind the controller's config
203 * space to devfn 0 in order to enable self-enumeration. In this
204 * case the regular ECAR/ECDR path is sidelined and the mangled
205 * config access itself is initiated as an internal bus transaction.
207 if (pci_is_root_bus(bus)) {
209 return PCIBIOS_DEVICE_NOT_FOUND;
211 if (access_type == RCAR_PCI_ACCESS_READ) {
212 *data = rcar_pci_read_reg(pcie, PCICONF(index));
214 /* Keep an eye out for changes to the root bus number */
215 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
216 pcie->root_bus_nr = *data & 0xff;
218 rcar_pci_write_reg(pcie, *data, PCICONF(index));
221 return PCIBIOS_SUCCESSFUL;
224 if (pcie->root_bus_nr < 0)
225 return PCIBIOS_DEVICE_NOT_FOUND;
228 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
230 /* Set the PIO address */
231 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
232 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
234 /* Enable the configuration access */
235 if (bus->parent->number == pcie->root_bus_nr)
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
238 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
240 /* Check for errors */
241 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
242 return PCIBIOS_DEVICE_NOT_FOUND;
244 /* Check for master and target aborts */
245 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
246 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
247 return PCIBIOS_DEVICE_NOT_FOUND;
249 if (access_type == RCAR_PCI_ACCESS_READ)
250 *data = rcar_pci_read_reg(pcie, PCIECDR);
252 rcar_pci_write_reg(pcie, *data, PCIECDR);
254 /* Disable the configuration access */
255 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
257 return PCIBIOS_SUCCESSFUL;
260 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
261 int where, int size, u32 *val)
263 struct rcar_pcie *pcie = bus->sysdata;
266 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
267 bus, devfn, where, val);
268 if (ret != PCIBIOS_SUCCESSFUL) {
274 *val = (*val >> (8 * (where & 3))) & 0xff;
276 *val = (*val >> (8 * (where & 2))) & 0xffff;
278 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
279 bus->number, devfn, where, size, (unsigned long)*val);
284 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
285 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
286 int where, int size, u32 val)
288 struct rcar_pcie *pcie = bus->sysdata;
292 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
293 bus, devfn, where, &data);
294 if (ret != PCIBIOS_SUCCESSFUL)
297 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
298 bus->number, devfn, where, size, (unsigned long)val);
301 shift = 8 * (where & 3);
302 data &= ~(0xff << shift);
303 data |= ((val & 0xff) << shift);
304 } else if (size == 2) {
305 shift = 8 * (where & 2);
306 data &= ~(0xffff << shift);
307 data |= ((val & 0xffff) << shift);
311 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
312 bus, devfn, where, &data);
317 static struct pci_ops rcar_pcie_ops = {
318 .read = rcar_pcie_read_conf,
319 .write = rcar_pcie_write_conf,
322 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
323 struct resource *res)
325 /* Setup PCIe address space mappings for each resource */
326 resource_size_t size;
327 resource_size_t res_start;
330 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
333 * The PAMR mask is calculated in units of 128Bytes, which
334 * keeps things pretty simple.
336 size = resource_size(res);
337 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
338 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
340 if (res->flags & IORESOURCE_IO)
341 res_start = pci_pio_to_address(res->start);
343 res_start = res->start;
345 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
346 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
349 /* First resource is for IO */
351 if (res->flags & IORESOURCE_IO)
354 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
357 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
359 struct resource_entry *win;
362 /* Setup PCI resources */
363 resource_list_for_each_entry(win, &pci->resources) {
364 struct resource *res = win->res;
369 switch (resource_type(res)) {
372 rcar_pcie_setup_window(i, pci, res);
376 pci->root_bus_nr = res->start;
382 pci_add_resource(resource, res);
388 static int rcar_pcie_enable(struct rcar_pcie *pcie)
390 struct pci_bus *bus, *child;
393 rcar_pcie_setup(&res, pcie);
395 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
397 if (IS_ENABLED(CONFIG_PCI_MSI))
398 bus = pci_scan_root_bus_msi(pcie->dev, pcie->root_bus_nr,
399 &rcar_pcie_ops, pcie, &res, &pcie->msi.chip);
401 bus = pci_scan_root_bus(pcie->dev, pcie->root_bus_nr,
402 &rcar_pcie_ops, pcie, &res);
405 dev_err(pcie->dev, "Scanning rootbus failed");
409 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
411 pci_bus_size_bridges(bus);
412 pci_bus_assign_resources(bus);
414 list_for_each_entry(child, &bus->children, node)
415 pcie_bus_configure_settings(child);
417 pci_bus_add_devices(bus);
422 static int phy_wait_for_ack(struct rcar_pcie *pcie)
424 unsigned int timeout = 100;
427 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
433 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
438 static void phy_write_reg(struct rcar_pcie *pcie,
439 unsigned int rate, unsigned int addr,
440 unsigned int lane, unsigned int data)
442 unsigned long phyaddr;
444 phyaddr = WRITE_CMD |
445 ((rate & 1) << RATE_POS) |
446 ((lane & 0xf) << LANE_POS) |
447 ((addr & 0xff) << ADR_POS);
450 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
451 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
453 /* Ignore errors as they will be dealt with if the data link is down */
454 phy_wait_for_ack(pcie);
457 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
458 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
460 /* Ignore errors as they will be dealt with if the data link is down */
461 phy_wait_for_ack(pcie);
464 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
466 unsigned int timeout = 10;
469 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
478 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
482 /* Begin initialization */
483 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
486 rcar_pci_write_reg(pcie, 1, PCIEMSR);
489 * Initial header for port config space is type 1, set the device
490 * class to match. Hardware takes care of propagating the IDSETR
491 * settings, so there is no need to bother with a quirk.
493 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
496 * Setup Secondary Bus Number & Subordinate Bus Number, even though
497 * they aren't used, to avoid bridge being detected as broken.
499 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
500 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
502 /* Initialize default capabilities. */
503 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
504 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
505 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
506 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
507 PCI_HEADER_TYPE_BRIDGE);
509 /* Enable data link layer active state reporting */
510 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
511 PCI_EXP_LNKCAP_DLLLARC);
513 /* Write out the physical slot number = 0 */
514 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
516 /* Set the completion timer timeout to the maximum 50ms. */
517 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
519 /* Terminate list of capabilities (Next Capability Offset=0) */
520 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
523 if (IS_ENABLED(CONFIG_PCI_MSI))
524 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
526 /* Finish initialization - establish a PCI Express link */
527 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
529 /* This will timeout if we don't have a link. */
530 err = rcar_pcie_wait_for_dl(pcie);
534 /* Enable INTx interrupts */
535 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
542 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
544 unsigned int timeout = 10;
546 /* Initialize the phy */
547 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
548 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
549 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
550 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
551 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
552 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
553 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
554 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
555 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
556 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
557 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
558 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
560 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
561 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
562 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
565 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
566 return rcar_pcie_hw_init(pcie);
574 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
577 * These settings come from the R-Car Series, 2nd Generation User's
578 * Manual, section 50.3.1 (2) Initialization of the physical layer.
580 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
581 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
582 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
583 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
585 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
586 /* The following value is for DC connection, no termination resistor */
587 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
588 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
589 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
591 return rcar_pcie_hw_init(pcie);
594 static int rcar_msi_alloc(struct rcar_msi *chip)
598 mutex_lock(&chip->lock);
600 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
601 if (msi < INT_PCI_MSI_NR)
602 set_bit(msi, chip->used);
606 mutex_unlock(&chip->lock);
611 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
615 mutex_lock(&chip->lock);
616 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
617 order_base_2(no_irqs));
618 mutex_unlock(&chip->lock);
623 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
625 mutex_lock(&chip->lock);
626 clear_bit(irq, chip->used);
627 mutex_unlock(&chip->lock);
630 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
632 struct rcar_pcie *pcie = data;
633 struct rcar_msi *msi = &pcie->msi;
636 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
638 /* MSI & INTx share an interrupt - we only handle MSI here */
643 unsigned int index = find_first_bit(®, 32);
646 /* clear the interrupt */
647 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
649 irq = irq_find_mapping(msi->domain, index);
651 if (test_bit(index, msi->used))
652 generic_handle_irq(irq);
654 dev_info(pcie->dev, "unhandled MSI\n");
656 /* Unknown MSI, just clear it */
657 dev_dbg(pcie->dev, "unexpected MSI\n");
660 /* see if there's any more pending in this vector */
661 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
667 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
668 struct msi_desc *desc)
670 struct rcar_msi *msi = to_rcar_msi(chip);
671 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
676 hwirq = rcar_msi_alloc(msi);
680 irq = irq_find_mapping(msi->domain, hwirq);
682 rcar_msi_free(msi, hwirq);
686 irq_set_msi_desc(irq, desc);
688 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
689 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
692 pci_write_msi_msg(irq, &msg);
697 static int rcar_msi_setup_irqs(struct msi_controller *chip,
698 struct pci_dev *pdev, int nvec, int type)
700 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
701 struct rcar_msi *msi = to_rcar_msi(chip);
702 struct msi_desc *desc;
708 /* MSI-X interrupts are not supported */
709 if (type == PCI_CAP_ID_MSIX)
712 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
713 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
715 hwirq = rcar_msi_alloc_region(msi, nvec);
719 irq = irq_find_mapping(msi->domain, hwirq);
723 for (i = 0; i < nvec; i++) {
725 * irq_create_mapping() called from rcar_pcie_probe() pre-
726 * allocates descs, so there is no need to allocate descs here.
727 * We can therefore assume that if irq_find_mapping() above
728 * returns non-zero, then the descs are also successfully
731 if (irq_set_msi_desc_off(irq, i, desc)) {
737 desc->nvec_used = nvec;
738 desc->msi_attrib.multiple = order_base_2(nvec);
740 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
741 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
744 pci_write_msi_msg(irq, &msg);
749 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
751 struct rcar_msi *msi = to_rcar_msi(chip);
752 struct irq_data *d = irq_get_irq_data(irq);
754 rcar_msi_free(msi, d->hwirq);
757 static struct irq_chip rcar_msi_irq_chip = {
758 .name = "R-Car PCIe MSI",
759 .irq_enable = pci_msi_unmask_irq,
760 .irq_disable = pci_msi_mask_irq,
761 .irq_mask = pci_msi_mask_irq,
762 .irq_unmask = pci_msi_unmask_irq,
765 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
766 irq_hw_number_t hwirq)
768 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
769 irq_set_chip_data(irq, domain->host_data);
774 static const struct irq_domain_ops msi_domain_ops = {
778 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
780 struct platform_device *pdev = to_platform_device(pcie->dev);
781 struct rcar_msi *msi = &pcie->msi;
785 mutex_init(&msi->lock);
787 msi->chip.dev = pcie->dev;
788 msi->chip.setup_irq = rcar_msi_setup_irq;
789 msi->chip.setup_irqs = rcar_msi_setup_irqs;
790 msi->chip.teardown_irq = rcar_msi_teardown_irq;
792 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
793 &msi_domain_ops, &msi->chip);
795 dev_err(&pdev->dev, "failed to create IRQ domain\n");
799 for (i = 0; i < INT_PCI_MSI_NR; i++)
800 irq_create_mapping(msi->domain, i);
802 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
803 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
804 IRQF_SHARED | IRQF_NO_THREAD,
805 rcar_msi_irq_chip.name, pcie);
807 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
811 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
812 IRQF_SHARED | IRQF_NO_THREAD,
813 rcar_msi_irq_chip.name, pcie);
815 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
819 /* setup MSI data target */
820 msi->pages = __get_free_pages(GFP_KERNEL, 0);
821 base = virt_to_phys((void *)msi->pages);
823 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
824 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
826 /* enable all MSI interrupts */
827 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
832 irq_domain_remove(msi->domain);
836 static int rcar_pcie_get_resources(struct platform_device *pdev,
837 struct rcar_pcie *pcie)
842 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
846 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
847 if (IS_ERR(pcie->base))
848 return PTR_ERR(pcie->base);
850 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
851 if (IS_ERR(pcie->clk)) {
852 dev_err(pcie->dev, "cannot get platform clock\n");
853 return PTR_ERR(pcie->clk);
855 err = clk_prepare_enable(pcie->clk);
859 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
860 if (IS_ERR(pcie->bus_clk)) {
861 dev_err(pcie->dev, "cannot get pcie bus clock\n");
862 err = PTR_ERR(pcie->bus_clk);
865 err = clk_prepare_enable(pcie->bus_clk);
869 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
871 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
877 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
879 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
888 clk_disable_unprepare(pcie->bus_clk);
890 clk_disable_unprepare(pcie->clk);
895 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
896 struct of_pci_range *range,
899 u64 restype = range->flags;
900 u64 cpu_addr = range->cpu_addr;
901 u64 cpu_end = range->cpu_addr + range->size;
902 u64 pci_addr = range->pci_addr;
903 u32 flags = LAM_64BIT | LAR_ENABLE;
908 if (restype & IORESOURCE_PREFETCH)
909 flags |= LAM_PREFETCH;
912 * If the size of the range is larger than the alignment of the start
913 * address, we have to use multiple entries to perform the mapping.
916 unsigned long nr_zeros = __ffs64(cpu_addr);
917 u64 alignment = 1ULL << nr_zeros;
919 size = min(range->size, alignment);
923 /* Hardware supports max 4GiB inbound region */
924 size = min(size, 1ULL << 32);
926 mask = roundup_pow_of_two(size) - 1;
929 while (cpu_addr < cpu_end) {
931 * Set up 64-bit inbound regions as the range parser doesn't
932 * distinguish between 32 and 64-bit types.
934 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
936 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
937 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
940 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
942 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
944 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
950 if (idx > MAX_NR_INBOUND_MAPS) {
951 dev_err(pcie->dev, "Failed to map inbound regions!\n");
960 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
961 struct device_node *node)
963 const int na = 3, ns = 2;
967 parser->pna = of_n_addr_cells(node);
968 parser->np = parser->pna + na + ns;
970 parser->range = of_get_property(node, "dma-ranges", &rlen);
974 parser->end = parser->range + rlen / sizeof(__be32);
978 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
979 struct device_node *np)
981 struct of_pci_range range;
982 struct of_pci_range_parser parser;
986 if (pci_dma_range_parser_init(&parser, np))
989 /* Get the dma-ranges from DT */
990 for_each_of_pci_range(&parser, &range) {
991 u64 end = range.cpu_addr + range.size - 1;
993 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
994 range.flags, range.cpu_addr, end, range.pci_addr);
996 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1004 static const struct of_device_id rcar_pcie_of_match[] = {
1005 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
1006 { .compatible = "renesas,pcie-rcar-gen2",
1007 .data = rcar_pcie_hw_init_gen2 },
1008 { .compatible = "renesas,pcie-r8a7790",
1009 .data = rcar_pcie_hw_init_gen2 },
1010 { .compatible = "renesas,pcie-r8a7791",
1011 .data = rcar_pcie_hw_init_gen2 },
1012 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
1016 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
1019 struct device *dev = pci->dev;
1020 struct device_node *np = dev->of_node;
1021 resource_size_t iobase;
1022 struct resource_entry *win;
1024 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
1029 err = devm_request_pci_bus_resources(dev, &pci->resources);
1031 goto out_release_res;
1033 resource_list_for_each_entry(win, &pci->resources) {
1034 struct resource *res = win->res;
1036 if (resource_type(res) == IORESOURCE_IO) {
1037 err = pci_remap_iospace(res, iobase);
1039 dev_warn(dev, "error %d: failed to map resource %pR\n",
1047 pci_free_resource_list(&pci->resources);
1051 static int rcar_pcie_probe(struct platform_device *pdev)
1053 struct rcar_pcie *pcie;
1055 const struct of_device_id *of_id;
1057 int (*hw_init_fn)(struct rcar_pcie *);
1059 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1063 pcie->dev = &pdev->dev;
1064 platform_set_drvdata(pdev, pcie);
1066 INIT_LIST_HEAD(&pcie->resources);
1068 rcar_pcie_parse_request_of_pci_ranges(pcie);
1070 err = rcar_pcie_get_resources(pdev, pcie);
1072 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
1076 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
1080 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
1081 if (!of_id || !of_id->data)
1083 hw_init_fn = of_id->data;
1085 pm_runtime_enable(pcie->dev);
1086 err = pm_runtime_get_sync(pcie->dev);
1088 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1089 goto err_pm_disable;
1092 /* Failure to get a link might just be that no cards are inserted */
1093 err = hw_init_fn(pcie);
1095 dev_info(&pdev->dev, "PCIe link down\n");
1100 data = rcar_pci_read_reg(pcie, MACSR);
1101 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1103 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1104 err = rcar_pcie_enable_msi(pcie);
1107 "failed to enable MSI support: %d\n",
1113 err = rcar_pcie_enable(pcie);
1120 pm_runtime_put(pcie->dev);
1123 pm_runtime_disable(pcie->dev);
1127 static struct platform_driver rcar_pcie_driver = {
1130 .of_match_table = rcar_pcie_of_match,
1131 .suppress_bind_attrs = true,
1133 .probe = rcar_pcie_probe,
1135 builtin_platform_driver(rcar_pcie_driver);